CN110262148B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN110262148B CN110262148B CN201910593124.8A CN201910593124A CN110262148B CN 110262148 B CN110262148 B CN 110262148B CN 201910593124 A CN201910593124 A CN 201910593124A CN 110262148 B CN110262148 B CN 110262148B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
Abstract
The invention discloses an array substrate, a display panel and a display device, wherein the array substrate comprises a display area and a non-display area positioned on at least one side of the display area, the array substrate also comprises a plurality of signal lines positioned in the non-display area, at least one signal line comprises a first part and a second part, and the first part and the second part of the at least one signal line are positioned on different metal layers; the line width of the first portion is larger than that of the second portion along a direction parallel to the array substrate. According to the technical scheme, the wiring space of the non-display area occupied by the signal lines in the non-display area is reduced, the narrow frame of the display device is facilitated to be realized, the influence of the broken signal lines in the non-display area on the signal transmission process is reduced, and the problems of abnormal display and waste of module materials caused by the broken signal lines in the non-display area are solved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
Currently, display devices such as Liquid Crystal Displays (LCDs) and Organic Light-Emitting diodes (OLEDs) are widely used in electronic devices such as televisions and portable computer systems.
The display device generally comprises a display area and a non-display area, wherein a plurality of signal lines are arranged in the non-display area, the plurality of signal lines in the non-display area generally adopt a single-layer wiring mode at present, the signal lines are easy to break due to abnormal array substrate manufacturing process, scratch and the like, the signal lines in the non-display area are used for transmitting signals for display to the display area, the display effect of the display device can be directly influenced or even abnormal display can be caused by the broken signal lines in the non-display area, and waste of module materials can be further caused.
Disclosure of Invention
The invention provides an array substrate, a display panel and a display device, which are beneficial to reducing the wiring space of a non-display area occupied by signal lines in the non-display area and realizing the narrow frame of the display device, and meanwhile, the influence of the broken signal lines in the non-display area on the signal transmission process is reduced, and the problems of abnormal display and waste of module materials caused by the broken signal lines in the non-display area are solved.
In a first aspect, an embodiment of the present invention provides an array substrate, including a display area and a non-display area located on at least one side of the display area, where the array substrate further includes:
a plurality of signal lines in the non-display area, at least one of the signal lines including a first portion and a second portion, the first portion and the second portion of the at least one of the signal lines being located in different metal layers;
the line width of the first portion is greater than the line width of the second portion along a direction parallel to the array substrate.
Furthermore, the first signal line and the second signal line are two adjacent signal lines, and along a direction perpendicular to the array substrate, an arrangement direction of a first portion of the first signal line relative to a second portion of the first signal line is opposite to an arrangement direction of a first portion of the second signal line relative to a second portion of the second signal line.
Further, the first portion of the first signal line and the second portion of the second signal line are located in the same metal layer, and the second portion of the first signal line and the first portion of the second signal line are located in the same metal layer.
Furthermore, the first portion of the first signal line is located in a first metal layer, the second portion of the first signal line and the second portion of the second signal line are both located in a second metal layer, and the first portion of the second signal line is located in a third metal layer.
Further, the vertical projection of the first portion of the signal line overlaps the vertical projection of the second portion of the signal line in a direction perpendicular to the array substrate.
Further, the first portion of the signal line includes a first edge and the second portion of the signal line includes a second edge along a direction perpendicular to the extending direction of the signal line, the first edge and the second edge being aligned along the direction perpendicular to the array substrate;
along a direction parallel to the array substrate, the arrangement direction of the first edge of the first signal line relative to the first signal line is a direction in which the first signal line deviates from the second signal line, and the arrangement direction of the first edge of the second signal line relative to the second signal line is a direction in which the second signal line deviates from the first signal line.
Furthermore, the first part of the signal line is electrically connected with the second part of the signal line through a via hole, and the vertical projection of the via hole covers the vertical projection of the corresponding second part along the direction vertical to the array substrate.
Furthermore, along the direction parallel to the array substrate, the line width of the first part is greater than 4 μm and less than or equal to 6 μm, and the line width of the second part is greater than or equal to 2 μm and less than or equal to 4 μm.
In a second aspect, an embodiment of the present invention further provides a display panel, including the array substrate according to the first aspect.
In a third aspect, an embodiment of the present invention further provides a display device, including the display panel according to the second aspect.
The embodiment of the invention provides an array substrate, a display panel and a display device, wherein the array substrate comprises a display area and a non-display area positioned on at least one side of the display area, the array substrate also comprises a plurality of signal lines positioned on the non-display area, at least one signal line comprises a first part and a second part, the first part and the second part of at least one signal line are positioned on different metal layers, and the line width of the first part is larger than that of the second part along the direction parallel to the array substrate.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 is a schematic top view of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic top view of another array substrate according to an embodiment of the present invention;
fig. 4 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the invention;
fig. 5 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;
FIG. 6 is a schematic top view of an array substrate according to the prior art;
fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures. Throughout this specification, the same or similar reference numbers refer to the same or similar structures, elements, or processes. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The embodiment of the invention provides an array substrate, which comprises a display area and a non-display area positioned on at least one side of the display area, and further comprises a plurality of signal lines positioned in the non-display area, wherein at least one signal line comprises a first part and a second part, the first part and the second part of the at least one signal line are positioned on different metal layers, and the line width of the first part is greater than that of the second part along the direction parallel to the array substrate.
The display device generally comprises a display area and a non-display area, wherein a plurality of signal lines are arranged in the non-display area, the plurality of signal lines in the non-display area generally adopt a single-layer wiring mode, the signal lines are easy to break due to abnormal array substrate manufacturing process, scratch and other reasons, the signal lines in the non-display area are used for transmitting signals for display to the display area, the display effect of the display device can be directly influenced or even abnormal display can be caused due to the broken signal lines in the non-display area, and the waste of module materials can be caused.
The array substrate provided by the embodiment of the invention comprises a display area and a non-display area positioned on at least one side of the display area, and further comprises a plurality of signal lines positioned in the non-display area, wherein at least one signal line comprises a first part and a second part, the first part and the second part of the at least one signal line are positioned on different metal layers, and the line width of the first part is larger than that of the second part along the direction parallel to the array substrate.
The above is the core idea of the present invention, and the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.
Fig. 1 is a schematic top view structure diagram of an array substrate according to an embodiment of the present invention, fig. 2 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present invention, and fig. 3 is a schematic top view structure diagram of another array substrate according to an embodiment of the present invention. Referring to fig. 1 to 3, the array substrate includes a display area AA and a non-display area NAA located at least one side of the display area AA, where the non-display area NAA is exemplarily disposed below the display area AA, the array substrate further includes a plurality of signal lines 1 located in the non-display area NAA, at least one signal line 1 includes a first portion 11 and a second portion 12, the first portion 11 and the second portion 12 of the at least one signal line 1 are located at different metal layers 2, and a line width of the first portion 11 is greater than a line width of the second portion 12 in a direction parallel to the array substrate, that is, d1 is greater than d 3.
Specifically, referring to fig. 1 to 3, the plurality of signal lines 1 located in the non-display area NAA are used to provide signals for display to the display area AA, the non-display area NAA is further provided with a pad bonding area a1, the driving chip provides signals for display to the display area AA through the corresponding pad a11 located in the pad bonding area a1 and the signal line 1 located in the non-display area NAA, the signal line 1 located in the non-display area NAA may include a data signal line, for example, and the driving chip may transmit data signals to the pixel cells of the display area AA through the corresponding pad a11 located in the pad bonding area a1 and the data signal line located in the non-display area NAA, and the specific signals transmitted on the signal lines 1 are not limited in the embodiment of the present invention.
At present, a single-layer wiring mode is generally adopted for a signal line 1 located in a non-display area NAA, and the array substrate is abnormal in manufacturing process, for example, in the manufacturing process of an array substrate, particles used for manufacturing the substrate of the signal line 1 located in the non-display area NAA can cause the signal line 1 located in the non-display area NAA to be easily broken, and the non-display area NAA scratch of a display device can also cause the signal line 1 to be easily broken, so that a driving chip cannot transmit a display signal to a display area AA through the signal line 1 located in the non-display area NAA, and the display effect of the display device is affected and even the display is abnormal. In addition, the signal line 1 in the non-display area NAA is generally completed in the manufacturing process of the array substrate, the manufacturing process of the array substrate further includes the manufacturing process of module materials, such as the driving chip, the printed circuit board, the flexible circuit board and other structures, and the disconnection of the signal line 1 in the non-display area NAA causes direct scrapping of the display device, which results in waste of the module materials.
Specifically, with reference to fig. 1 to 3, at least one signal line 1 located in the non-display area NAA is provided to include a first portion 11 and a second portion 12, where the first portion 11 and the second portion 12 of the at least one signal line 1 are located in different metal layers 2, so that, for the same signal line 1 located in the non-display area NAA, if the first portion 11 is disconnected, a corresponding signal transmitted on the signal line 1 may also be transmitted through the second portion 12, and if the second portion 12 is disconnected, a corresponding signal transmitted on the signal line 1 may also be transmitted through the first portion 11, thereby greatly reducing an influence of the disconnection of the signal line 1 located in the non-display area NAA on a signal transmission process, and improving problems of display abnormality and waste of module materials caused by the disconnection of the signal line 1 in the non-display area NAA. In addition, the arrangement that the line width of the first portion 11 is greater than the line width of the second portion 12 in the direction parallel to the array substrate, that is, d1 is greater than d3, is favorable for reducing the distance between adjacent signal lines 1, thus reducing the influence of the broken line of the signal line 1 located in the non-display area NAA on the signal transmission process, and simultaneously being favorable for reducing the wiring space of the non-display area NAA occupied by the signal line 1 located in the non-display area NAA.
In addition, as shown in fig. 1, the signal lines 1 located in the non-display area NAA are all oblique wires, that is, the routing directions of the signal lines 1 all have a certain angle, the more the number of the signal lines 1 of the non-display area NAA is, the larger the inclination angle of the signal line 1 relative to the horizontal direction is, the larger the width of the non-display area NAA along the vertical direction is, which is not favorable for realizing the narrow frame of the display device.
Optionally, with reference to fig. 1 to fig. 3, the first signal line 101 and the second signal line 102 are two adjacent signal lines 1, and along a direction perpendicular to the array substrate, an arrangement direction of the first portion 11 of the first signal line 101 with respect to the second portion 12 of the first signal line 101 is opposite to an arrangement direction of the first portion 11 of the second signal line 102 with respect to the second portion 12 of the second signal line 102, for example, the first portion 11 of the first signal line 101 is located above the second portion 12 of the first signal line 101, and the first portion 11 of the second signal line 102 is located below the second portion 12 of the second signal line 102.
Specifically, with reference to fig. 1 to 3, since the line width of the first portion 11 is greater than the line width of the second portion 12 along the direction parallel to the array substrate, the arrangement direction of the first portion 11 of the first signal line 101 relative to the second portion 12 of the first signal line 101 is opposite to the arrangement direction of the first portion 11 of the second signal line 102 relative to the second portion 12 of the second signal line 102, which is beneficial to forming a complementary structure between the first signal line 101 and the second signal line 102 to reduce the distance between adjacent signal lines 1, further reduce the wiring space of the non-display area NAA occupied by the signal line 1 located in the non-display area NAA, and facilitate implementation of a narrow bezel of the display device.
Optionally, with reference to fig. 1 to fig. 3, the first portion 11 of the first signal line 101 and the second portion 12 of the second signal line 102 may be disposed on the same metal layer 21, and the second portion 12 of the first signal line 101 and the first portion 11 of the second signal line 102 are disposed on the same metal layer 22, that is, the first signal line 101 and the second signal line 102 share the two metal layers 2 for routing.
Alternatively, in conjunction with fig. 1 to 3, the vertical projection of the first portion 11 of the signal line 1 may be arranged to overlap the vertical projection of the second portion 12 of the signal line 1 in a direction perpendicular to the array substrate. Specifically, with reference to fig. 1 to 3, in consideration of semiconductor process, there is a limit value for the line width of the signal line 1 and the distance between the signal lines 1, it is configured that, in the direction perpendicular to the array substrate, the vertical projection of the first portion 11 of the signal line 1 covers the vertical projection of the second portion 12 of the signal line 1, while the first portion 11 and the second portion 12 are used for two-layer routing to reduce the influence of the broken line of the signal line 1 located in the non-display area NAA on the signal transmission process, the first portion 11 of the signal line 1 is used to ensure that the signal line 1 has a sufficiently large line width to reduce the line resistance of the signal line 1, and the projection relationship between the first portion 11 and the second portion 12 of the signal line 1 is used to make one signal line 1 occupy a smaller routing space of the non-display area NAA, i.e. it is beneficial to reduce the routing space of the non-display area NAA occupied by the signal line 1 located in the non-display area NAA, the realization of the narrow frame of the display device is facilitated.
Alternatively, with reference to fig. 1 to 3, the first portion 11 of the signal line 1 includes a first edge 31 along a direction perpendicular to the extending direction of the signal line 1, the second portion 12 of the signal line 1 includes a second edge 32, the first edge 31 and the second edge 32 may be arranged in alignment along the direction perpendicular to the array substrate, and since the vertical projection of the first portion 11 of the signal line 1 may be arranged to cover the vertical projection of the second portion 12 of the signal line 1 along the direction perpendicular to the array substrate, the first edge 31 and the second edge 32 are the same side edge with respect to the signal line 1. The direction parallel to the array substrate may be set, the setting direction of the first edge 31 of the first signal line 101 relative to the first signal line 101 is a direction in which the first signal line 101 deviates from the second signal line 102, and the setting direction of the first edge 31 of the second signal line 102 relative to the second signal line 102 is a direction in which the second signal line 102 deviates from the first signal line 101, so that the first signal line 101 and the second signal line 102 form a perfect complementary structure, and further, the wiring space of the non-display area NAA occupied by the adjacent signal lines 1 located in the non-display area NAA is minimized, the wiring space of the non-display area NAA occupied by the signal lines 1 located in the non-display area NAA is further reduced, and the realization of a narrow frame of the display device is facilitated.
In addition, for the array substrate with the structure shown in fig. 2 and 3, a gap still remains between adjacent signal lines 1 located in the non-display area NAA, taking the display device as an example of a liquid crystal display device, a sealant (not shown in the figure) that bonds the array substrate and the color film substrate is further disposed between the array substrate and the color film substrate corresponding to the non-display area NAA, the sealant covers the signal lines 1 located in the non-display area NAA, ultraviolet light needs to be irradiated to the sealant through the signal lines 1 located in the non-display area NAA to achieve curing of the sealant, the gap between the adjacent signal lines 1 of the non-display area NAA can be used as a light-transmitting area, so that the ultraviolet light can be irradiated to the sealant to achieve curing of the sealant, for example, the light transmittance of the non-display area NAA of the array substrate corresponding to the sealant area can be set to be greater than 30%.
Fig. 4 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the present invention, and fig. 5 is a schematic top-view structure view of another array substrate according to an embodiment of the present invention, which is different from the array substrate with the structure shown in fig. 2 and 3, in the array substrate with the structure shown in fig. 4 and 5, a first portion 11 of a first signal line 101 is located in a first metal layer 21, a second portion 12 of the first signal line 101 and a second portion 12 of a second signal line 102 are both located in a second metal layer 22, and a first portion 11 of the second signal line 102 is located in a third metal layer 23, that is, the first signal line 101 and the second signal line 102 share a three-layer metal layer 2 for routing.
With reference to fig. 1, 4 and 5, along the direction parallel to the array substrate, for example, the first signal line 101 and the second signal line 102 may be set to ensure that the minimum value of the line widths of the respective line resistors is 5 μm, that is, the line widths d1 of the first portion 31 of the first signal line 101 and the first portion 11 of the second signal line 102 are both 5 μm, in addition, when the first portion 11 of the signal line 1 is disconnected, the corresponding signals need to be transmitted through the second portion 12 of the signal line 1, the first signal line 101 and the second signal line 102 may be set to ensure that the widths d3 of the second portions 12 of the respective line resistors are both 3 μm, and the minimum distance d2 between adjacent signal lines 1 in the same metal layer 2 is 4 μm.
In the prior art, signal lines disposed in the non-display area NAA are generally single-layer wires, and adjacent signal lines are alternately wired by using two metal layers, and fig. 6 is a schematic top view structure diagram of an array substrate adopted in the prior art. As shown in fig. 6, two adjacent signal lines 111 and 112 are routed alternately by using two metal layers, each signal line may be set to ensure that the minimum value d4 of the line width of the line resistor is also 5 μm, and for the case that the adjacent signal line 1 is routed alternately by using two metal layers 2, the minimum distance d5 between the adjacent signal lines 1 is 2 μm in the direction parallel to the array substrate, as can be seen from comparing fig. 4 and 6, in the array substrate of the structure shown in fig. 4, the distance between the outer edges of the adjacent signal lines 1 is equal to twice the value d1, i.e. 10 μm, then the distance between the signal lines 1 of the array substrate of the structure shown in fig. 4 shows the rule of alternating between 10 μm and 4 μm, and in the array substrate of the structure shown in fig. 6, the distance between the outer edges of the adjacent signal lines 1 is equal to twice the sum of d1 and d5, i.e. 12 μm, then the distance between the signal lines 1 of the array substrate of the structure shown in fig. 6 shows the rule of alternating between 12 μm and 2 μm, thus, compared with the prior art, under the condition that the wiring space of the non-display area NAA occupied by the signal wire 1 of the non-display area NAA is basically the same, the embodiment of the invention reduces the influence of the broken wire of the signal wire 1 positioned in the non-display area NAA on the signal transmission process, and improves the problems of abnormal display and waste of module materials caused by the broken wire of the signal wire 1 of the non-display area NAA.
Optionally, with reference to fig. 1 to 5, the first portion 11 of the signal line 1 is electrically connected to the second portion 12 of the signal line 1 through the via 5, and a vertical projection of the via 5 covers a vertical projection of the corresponding second portion 12 along a direction perpendicular to the array substrate. Specifically, with reference to fig. 1 to 5, at least one insulating layer 20 is disposed between adjacent metal layers 2, where the insulating layer 20 is disposed between the adjacent metal layers 2 by way of example, and the first portion 11 of the signal line 1 is electrically connected to the second portion 12 of the signal line 1 through the via 5, so that when there is a disconnection problem in the first portion 11 of the signal line 1, a corresponding signal can be transmitted through the second portion 12 of the signal line 1, or when there is a disconnection problem in the first portion of the signal line 1, a corresponding signal can be transmitted through the first portion 11 of the signal line 1, so as to reduce an influence of the disconnection of the signal line 1 located in the non-display area NAA on a signal transmission process. The vertical projection of the via hole 5 covers the vertical projection of the corresponding second part 12 along the direction vertical to the array substrate, so that the first part 11 and the second part 12 of one signal line 1 are contacted with each other in the largest area through the via hole 5, and thus, the probability that a signal path exists in the signal line 1 can be greatly improved no matter the disconnection position of the signal line 1 exists at any position of the first part 11 or any position of the second part 12, and the influence of the disconnection of the signal line 1 in the non-display area NAA on the signal transmission process is further reduced.
Alternatively, with reference to fig. 1 to 5, along a direction parallel to the array substrate, the line width d1 of the first portion 11 may be greater than 4 μm and less than or equal to 6 μm, and the line width d3 of the second portion 12 may be greater than or equal to 2 μm and less than or equal to 4 μm. Specifically, with reference to fig. 1 to 5, along a direction parallel to the array substrate, an excessively large line width of the first portion 11 in the signal line 1 may cause the signal line 1 to occupy a large wiring space of the non-display area NAA, and an excessively small line width of the first portion 11 in the signal line 1 may cause an excessively large line resistance of the signal line 1, so that a large voltage drop may exist in a signal transmitted on the actual signal line 1, which affects uniformity of a signal transmission process. The line width of the second portion 12 in the signal line 1 is too large to reduce the distance between the adjacent signal lines 1 in the non-display area NAA, and when the first portion 11 of the signal line 1 is broken, the corresponding signal needs to be transmitted through the second portion 12 of the signal line 1, and the line width of the second portion 12 of the signal line 1 is too small to increase the line resistance of the transmission path of the signal line 1, which affects the uniformity of the signal transmission process.
It should be noted that the drawings of the embodiments of the present invention only show the size of each element and the thickness of each film layer by way of example, and do not represent the actual size of each element and each film layer in the array substrate.
The array substrate provided by the embodiment of the invention comprises a display area and a non-display area positioned on at least one side of the display area, and the array substrate also comprises a plurality of signal lines positioned in the non-display area, wherein at least one signal line comprises a first part and a second part, the first part and the second part of at least one signal line are positioned on different metal layers, and the line width of the first part is greater than that of the second part along the direction parallel to the array substrate, so that the wiring space of the non-display area occupied by the signal lines positioned in the non-display area is favorably reduced, the realization of a narrow frame of a display device is favorably realized, the influence of the broken line of the signal lines positioned in the non-display area on the signal transmission process is reduced, and the problems of abnormal display and waste of module materials caused by the broken line of the signal lines positioned in the non-display area are solved.
The embodiment of the invention also provides a display panel, and fig. 7 is a schematic structural diagram of the display panel provided by the embodiment of the invention. As shown in fig. 7, the display panel 30 includes the array substrate 301 in the above embodiments, so that the display panel 30 provided in the embodiment of the present invention also has the beneficial effects described in the above embodiments, and the details are not repeated herein. The display panel 30 may be an organic light emitting display panel or a liquid crystal display panel, for example.
The embodiment of the invention also provides a display device, and fig. 8 is a schematic structural diagram of the display device provided by the embodiment of the invention. As shown in fig. 8, the display device 300 includes the display panel 30 in the above embodiment, and thus the display device 300 provided in the embodiment of the present invention also has the beneficial effects described in the above embodiment, which are not repeated herein. The display device 300 may be an electronic display device such as a mobile phone, a computer, or a television.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments illustrated herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (8)
1. An array substrate, comprising a display area and a non-display area located on at least one side of the display area, wherein the array substrate further comprises:
a plurality of signal lines in the non-display area, at least one of the signal lines including a first portion and a second portion, the first portion and the second portion of the at least one of the signal lines being located in different metal layers;
the first signal line and the second signal line are two adjacent signal lines, a first part of the first signal line and a second part of the second signal line are positioned on the same metal layer, and the second part of the first signal line and the first part of the second signal line are positioned on the same metal layer; the line width of the first portion is greater than the line width of the second portion along a direction parallel to the array substrate.
2. The array substrate of claim 1, wherein a direction of arrangement of the first portion of the first signal line with respect to the second portion of the first signal line is opposite to a direction of arrangement of the first portion of the second signal line with respect to the second portion of the second signal line in a direction perpendicular to the array substrate.
3. The array substrate of claim 1, wherein a vertical projection of the first portion of the signal line overlaps a vertical projection of the second portion of the signal line in a direction perpendicular to the array substrate.
4. The array substrate of claim 3, wherein the first portion of the signal line includes a first edge and the second portion of the signal line includes a second edge along a direction perpendicular to the direction in which the signal line extends, the first edge being aligned with the second edge along the direction perpendicular to the array substrate;
along a direction parallel to the array substrate, the arrangement direction of the first edge of the first signal line relative to the first signal line is a direction in which the first signal line deviates from the second signal line, and the arrangement direction of the first edge of the second signal line relative to the second signal line is a direction in which the second signal line deviates from the first signal line.
5. The array substrate of claim 3, wherein the first portion of the signal line is electrically connected to the second portion of the signal line through a via, and a vertical projection of the via covers a vertical projection of the corresponding second portion in a direction perpendicular to the array substrate.
6. The array substrate of claim 1, wherein the line width of the first portion is greater than 4 μm and less than or equal to 6 μm, and the line width of the second portion is greater than or equal to 2 μm and less than or equal to 4 μm along a direction parallel to the array substrate.
7. A display panel comprising the array substrate according to any one of claims 1 to 6.
8. A display device comprising the display panel according to claim 7.
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| CN104570515A (en) * | 2015-01-26 | 2015-04-29 | 京东方科技集团股份有限公司 | Array substrate and manufacture method thereof, display panel and display device |
| CN105158996A (en) * | 2015-10-13 | 2015-12-16 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN106526995A (en) * | 2016-10-31 | 2017-03-22 | 厦门天马微电子有限公司 | Array substrate and display panel |
| CN108732833A (en) * | 2018-05-24 | 2018-11-02 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display device |
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| TW588204B (en) * | 2002-03-14 | 2004-05-21 | Wintek Corp | Transparent conduction plate having low junction resistance and manufacturing method thereof |
| KR20040060619A (en) * | 2002-12-30 | 2004-07-06 | 삼성전자주식회사 | Liquid crystal display |
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| CN103336395A (en) * | 2013-06-18 | 2013-10-02 | 南京中电熊猫液晶显示科技有限公司 | Wiring structure |
| CN104570515A (en) * | 2015-01-26 | 2015-04-29 | 京东方科技集团股份有限公司 | Array substrate and manufacture method thereof, display panel and display device |
| CN105158996A (en) * | 2015-10-13 | 2015-12-16 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
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