CN103311142A - 封装结构及其封装工艺 - Google Patents

封装结构及其封装工艺 Download PDF

Info

Publication number
CN103311142A
CN103311142A CN2013102633269A CN201310263326A CN103311142A CN 103311142 A CN103311142 A CN 103311142A CN 2013102633269 A CN2013102633269 A CN 2013102633269A CN 201310263326 A CN201310263326 A CN 201310263326A CN 103311142 A CN103311142 A CN 103311142A
Authority
CN
China
Prior art keywords
substrate
bonding
wire
bonding point
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2013102633269A
Other languages
English (en)
Other versions
CN103311142B (zh
Inventor
杨秉谋
孙元鹏
万帮卫
方先华
林政�
方彬彬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Zhenhua Microelectronics Co Ltd
Original Assignee
Shenzhen Zhenhua Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Zhenhua Microelectronics Co Ltd filed Critical Shenzhen Zhenhua Microelectronics Co Ltd
Priority to CN201310263326.9A priority Critical patent/CN103311142B/zh
Publication of CN103311142A publication Critical patent/CN103311142A/zh
Application granted granted Critical
Publication of CN103311142B publication Critical patent/CN103311142B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48991—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on the semiconductor or solid-state body to be connected
    • H01L2224/48992—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4941—Connecting portions the connecting portions being stacked
    • H01L2224/49429—Wedge and ball bonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

一种封装结构，包括基板、安装于基板上的元器件、以及连接于基板与元器件之间的引线，所述引线包括第一端、第二端、以及位于第一端与第二端之间的连接点，所述第一端与元器件相连接并形成第一键合点，所述连接点与基板相连接并形成第二键合点，所述第二端与基板相连接并形成第三键合点，从而引线位于连接点与第二端之间尾丝部分经由第三键合点的连接固定在基板上，达到减少尾丝的目的，将尾丝长度完全控制在2倍引线直径以内。

Description

封装结构及其封装工艺
技术领域
本发明涉及封装，尤其涉及一种封装结构及其封装工艺。
背景技术
引线键合由于其工艺实现简单、成本低廉等特点被广泛地用于半导体芯片、厚膜电路的封装工艺中。引线键合是以细小的金属引线的两端分别连接基板以及半导体芯片、电阻、电容等元器件，使各元器件与基板上的电路电性连接。封装时，引线的一端结合于元器件上形成第一焊点，然后引线上升送线形成线弧，之后连接于基板上，拉断引线，进行电火花烧球后在基板上的引线端进行加固键合形成第二焊点，在形成第二焊点之后截断引线，进行下一元器件的连接，然而截断引线会在第二焊点位置形成尾丝，尾丝过长容易导致短路等问题，影响封装结构的电气安全。
发明内容
为解决上述问题，本发明提供一种能有效避免尾丝过长的封装结构及其封装工艺。
一种封装结构，包括基板、安装于基板上的元器件、以及连接于基板与元器件之间的引线，所述引线包括第一端、第二端、以及位于第一端与第二端之间的连接点，所述第一端与元器件相连接并形成第一键合点，所述连接点与基板相连接并形成第二键合点，所述第二端与基板相连接并形成第三键合点。
一种封装工艺，包括以下步骤：将引线键合于元器件上形成第一键合点；将引线键合于基板上并形成第二键合点；拉断引线；通过电火花烧球在第二键合点进行加固键合并将引线拉出形成尾丝；将尾丝固接于基板上并形成第三键合点。
相较于现有技术，本发明封装结构封装时对第二键合点处形成的尾丝进行压焊，将残留的尾丝压焊在基板上，有效控制尾丝的长度。
附图说明
图1为本发明封装结构一实施例的结构示意图。
图2为本发明封装工艺的流程图。
主要元件符号说明
元器件 10
第一键合点 20
基板 30
键合区 32
第二键合点 40
引线 50
第一端 52
连接点 54
第二端 56
第三键合点 60
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
如图1所示，本发明封装结构包括基板30、安装于基板30上的元器件10、以及连接元器件10与基板30的引线50。
所述元器件10可以为半导体芯片如发光二极管、电阻、电感、电容等，所述基板30上形成有电路，用于与元器件10电性连接，从而实现元器件10与外部电路的电气连接。所示基板30可以为印刷电路板(PCB)、金属芯电路板(MCPCB)、陶瓷基板等，可以将元器件10所产生的热量导出，避免元器件10过热。
元器件10以引线键合的方式与基板30上的电路相连接，也就是说，元器件10通过引线50与基板30相连接。所述引线键合可以是热压键合、超声波键合、或热压超声波键合等。所述引线50为细小的金属线，如金线等，包括第一端52、第二端56、以及位于第一端52与第二端56之间的连接点54，所述连接点54相对靠近于第二端56。所述第一端52与元器件10相连接，所述连接点54与基板30上的电路相连接，所述第二端56连接于基板30上，但在基板30上的电路中不起电性能作用，引线50的加固键合点40与第二端56的部分即为尾丝，通过将尾丝的端部连接于基板30上，从而有效控制引线50尾丝的长度，避免造成短路，使其满足GJB548B-2005《微电子器件试验方法和程序》方法2017.1中第3.1.5.8.g的要求，即不得使“键合引线50的尾丝在键合区32的长度超过引线50直径的2倍”。
本发明封装结构封装时，如图2所示，首先将引线50的第一端52键合于元器件10上并形成第一键合点20，然后引线50上升形成线弧，之后将引线50的连接点54键合于基板30上，拉断引线，进行电火花烧球后，在连接点54上进行加固键合并形成第二键合40点，如此将元器件10与基板30上的电路电性连接。在所述基板30上，在对应于电路连接处的位置可以形成键合区32，便于与引线50的连接。在形成第二键合40点之后，截断引线50，以进行下一元器件10的键合作业，引线50被截断的点即为引线50的第二端56。
形成第二键合40点后，被截断的引线50，在第二键合40点处构成尾丝，为避免尾丝的长度过长，将尾丝拉出进行压焊，即对其施加一定的超声和压力使其表面在固态下直接紧密接触并温度升高，通过调节超声，温度，压力和时间，使引线50的尾丝与基板30的接触面充分进行扩散而实现原子间结合，将尾丝固接于基板30上，尾丝的末端，即引线50的第二端56连接于基板30上形成第三键合点60。通常，是将尾丝压焊于基板30的键合区32内，第二键合40点与第三键合点60的距离约为0.05～1mm，引线50位于第二键合40点与第三键合点60之间的部分，即尾丝的弧高为0.05～1mm。
本发明在第二键合40点完成键合之后，将尾丝拉出进行压焊，将尾丝的末端固接于基板30的键合区32内，从而保证封装后的封装结构不至于从尾丝过长，使其满足GJB548B-2005《微电子器件试验方法和程序》方法2017.1中第3.1.5.8.g要求即不得接收“键合引线50的尾丝在键合区32的长度超过引线50直径的2倍”，工艺简单、制作方便，所形成的封装结构安全可靠。
以上内容是结合具体按例的实施方式对本发明所作的一种说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明由所提交的权利要求书确定的专利保护范围。

Claims (9)

1.一种封装结构，包括基板、安装于基板上的元器件、以及连接于基板与元器件之间的引线，其特征在于：所述引线包括第一端、第二端、以及位于第一端与第二端之间的连接点，所述第一端与元器件相连接并形成第一键合点，所述连接点与基板相连接并形成第二键合点，所述第二端与基板相连接并形成第三键合点。
2.根据权利要求1所述的封装结构，其特征在于：所述第二键合点与第三键合点的距离为0.05～1mm。
3.根据权利要求1所述的封装结构，其特征在于：所述引线位于第二键合点与第三键合点之间的部分的弧高为0.05～1mm。
4.根据权利要求1所述的封装结构，其特征在于：所述基板上形成有电路，所述引线的第二键合点与基板的电路相连接，第三键合点在基板的电路中不起电性能作用。
5.一种封装工艺，包括以下步骤：
提供元器件、基板以及引线；
将引线键合于元器件上形成第一键合点；
将引线键合于基板上并形成第二键合点；
拉断引线；
通过电火花烧球在第二键合点进行加固键合并将引线拉出形成尾丝；
将尾丝固接于基板上并形成第三键合点。
6.根据权利要求5所述的封装工艺，其特征在于：在第二键合点进行加固键合形成加固键合球。
7.根据权利要求5所述的封装工艺，其特征在于：所述第二键合点与第三键合点的距离为0.05～1mm。
8.根据权利要求5所述的封装工艺，其特征在于：所述引线位于第二键合点与第三键合点之间的部分的弧高为0.05～1mm。
9.根据权利要求5所述的封装工艺，其特征在于：通过压焊将尾丝固接于基板上。
CN201310263326.9A 2013-06-21 2013-06-21 封装结构及其封装工艺 Active CN103311142B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310263326.9A CN103311142B (zh) 2013-06-21 2013-06-21 封装结构及其封装工艺

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310263326.9A CN103311142B (zh) 2013-06-21 2013-06-21 封装结构及其封装工艺

Publications (2)

Publication Number Publication Date
CN103311142A true CN103311142A (zh) 2013-09-18
CN103311142B CN103311142B (zh) 2016-08-17

Family

ID=49136215

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310263326.9A Active CN103311142B (zh) 2013-06-21 2013-06-21 封装结构及其封装工艺

Country Status (1)

Country Link
CN (1) CN103311142B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105355617A (zh) * 2015-11-25 2016-02-24 江苏欧密格光电科技股份有限公司 一种裸芯片技术中增强焊线牢靠度的结构及其方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6310535A (ja) * 1986-06-30 1988-01-18 ロ−ベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング 半導体構造要素内の電気的接続の製作方法
CN1474442A (zh) * 2002-08-08 2004-02-11 ��ʽ���纣�� 引线键合方法以及凸点形成方法和凸点
US20090321952A1 (en) * 2008-06-27 2009-12-31 Liang Xingzhi Wire on wire stitch bonding in a semiconductor device
CN102184875A (zh) * 2011-04-05 2011-09-14 山东理工大学 一种钉头金凸点的制备方法
CN203351586U (zh) * 2013-06-21 2013-12-18 深圳市振华微电子有限公司 封装结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6310535A (ja) * 1986-06-30 1988-01-18 ロ−ベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング 半導体構造要素内の電気的接続の製作方法
CN1474442A (zh) * 2002-08-08 2004-02-11 ��ʽ���纣�� 引线键合方法以及凸点形成方法和凸点
US20090321952A1 (en) * 2008-06-27 2009-12-31 Liang Xingzhi Wire on wire stitch bonding in a semiconductor device
CN102184875A (zh) * 2011-04-05 2011-09-14 山东理工大学 一种钉头金凸点的制备方法
CN203351586U (zh) * 2013-06-21 2013-12-18 深圳市振华微电子有限公司 封装结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105355617A (zh) * 2015-11-25 2016-02-24 江苏欧密格光电科技股份有限公司 一种裸芯片技术中增强焊线牢靠度的结构及其方法

Also Published As

Publication number Publication date
CN103311142B (zh) 2016-08-17

Similar Documents

Publication Publication Date Title
CN106449538A (zh) 贴片式整流器件结构
CN103779295A (zh) 功率模块封装
CN104332419A (zh) 倒装形式的芯片封装方法
JP5008832B2 (ja) 半導体装置及び半導体装置の製造方法
JP2015026791A (ja) 半導体装置及びリードフレーム
CN203351586U (zh) 封装结构
CN103311142A (zh) 封装结构及其封装工艺
CN204792795U (zh) 终端设备
TWI528516B (zh) 晶片組裝結構及晶片組裝方法
CN103296153B (zh) Led芯片封装方法
CN201392850Y (zh) 一种耐热霍尔元件
JP2014220424A (ja) フォトカプラ
CN104363698B (zh) 线路板的列引脚封装结构及封装设计方法和线路板
KR100833187B1 (ko) 반도체 패키지의 와이어 본딩방법
CN106783773A (zh) 一种非绝缘双塔型二极管模块
CN103327737B (zh) 芯片组装结构及芯片组装方法
CN105977174A (zh) 指纹产品封装结构的金线打线方法
CN205920991U (zh) 一种led封装结构
CN208478331U (zh) 用于sot/tsot封装的引线框架
JP2007027645A (ja) 半導体装置
JP2007088220A (ja) 半導体装置の製造方法
CN204632803U (zh) 一种csp led及基板
CN102856281A (zh) 半导体封装件及其制造方法
CN202918107U (zh) 一种电机和一种电机三相引出线和接线端子组合件
CN102637611A (zh) 一种aap功率模块的制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant