CN103295994A - Packaging structure, substrate structure and manufacturing method thereof - Google Patents
Packaging structure, substrate structure and manufacturing method thereof Download PDFInfo
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- CN103295994A CN103295994A CN201210059515XA CN201210059515A CN103295994A CN 103295994 A CN103295994 A CN 103295994A CN 201210059515X A CN201210059515X A CN 201210059515XA CN 201210059515 A CN201210059515 A CN 201210059515A CN 103295994 A CN103295994 A CN 103295994A
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- Prior art keywords
- insulating protective
- protective layer
- layer
- scolder
- patterned metal
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- 239000000758 substrate Substances 0.000 title claims abstract description 7
- 238000004806 packaging method and process Methods 0.000 title description 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000011241 protective layer Substances 0.000 claims abstract description 107
- 239000010410 layer Substances 0.000 claims abstract description 78
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 11
- 239000000084 colloidal system Substances 0.000 claims description 10
- 238000012856 packing Methods 0.000 claims description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 3
- 238000007772 electroless plating Methods 0.000 claims description 2
- 238000005566 electron beam evaporation Methods 0.000 claims description 2
- 238000007639 printing Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000009713 electroplating Methods 0.000 claims 1
- 238000010079 rubber tapping Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract 3
- 238000005516 engineering process Methods 0.000 description 15
- 238000005530 etching Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008034 disappearance Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A package structure, a substrate structure and a method for fabricating the same, the substrate structure includes: the solder is formed in each concave part, the patterned metal layer is formed on the first insulating protective layer and the solder and connected with the solder, the patterned metal layer is provided with a plurality of electric connection pads, and the second insulating protective layer is formed on the patterned metal layer and the first insulating protective layer and provided with a plurality of second insulating protective layer open holes correspondingly exposing the electric connection pads. The invention can effectively improve the reworkability and simplify the process.
Description
Technical field
The present invention relates to a kind of encapsulating structure, board structure and method for making thereof, refer to that especially a kind of square surface does not have the encapsulating structure of pin, board structure and method for making thereof.
Background technology
Square surface does not have pin (Quad Flat No Lead, abbreviation QFN) semiconductor package part is a kind of encapsulation unit that makes chip carrier and pin bottom surface expose to the encapsulated layer lower surface, general surperficial adhesion technology (the surface mount technology that adopts, be called for short SMT) square surface leadless semiconductor packaging part is connect place on the printed circuit board (PCB), whereby to form a circuit module with specific function.
See also Fig. 1, it does not have the cutaway view of pin (QFN) encapsulating structure for existing square surface.As shown in the figure, traditional QFN packaging technology is that semiconductor chip 11 is arranged on the lead frame 12, and by routing (wire-bonding) technology electrically connecting, and coat packing colloid 13, disturb to protect this semiconductor chip 11 not to be subjected to external environment.
Yet aforementioned encapsulating structure is through after cutting list (singulation) technology, and the cutting of its cutter can cause the pin 14 of encapsulating structure that burr are arranged, when two these pin 14 spacings more hour, excessive burr can touch contiguous pin 14 and cause short circuit; In addition, in mold pressing (molding) process, packing colloid 13 is excessive and pollute the lower surface of pin 14 easily, makes the follow-up technology of removing pin 14 culls that also will additionally increase.
Disappearance in view of aforementioned prior art, then develop and (for example: Japan Patent 11-251505 QFN encapsulating structure of new generation, 09-312355,2001-024135 and 2005-317998 number), as shown in Figure 2, but this kind encapsulating structure by scolding tin with after being connected to printed circuit board (PCB) (PCB), if need carry out heavy industry (rework), and with encapsulating structure after printed circuit board (PCB) takes off, tend to cause the coating on the not good or pin of the coplanarity of pin to come off, and then make that the heavy industry (reworkability) of overall package structure is not good, and the pin problem that drops is arranged easily.
Therefore, how to avoid above-mentioned variety of problems of the prior art, be easy to generate the relatively poor problem of burr and heavy industry with the pin that solves the square surface non-leaded package, reality has become the problem of desiring most ardently solution at present.
Summary of the invention
Because the disappearance of above-mentioned prior art, main purpose of the present invention provides a kind of encapsulating structure, board structure and method for making thereof, can effectively improve heavy industry and simplify technology.
Board structure of the present invention, it comprises: bearing part, surface thereof have a plurality of recesses; First insulating protective layer, it is formed at this bearing part has on the surface of this recess, and is formed with a plurality of correspondences and exposes the respectively first insulating protective layer perforate of this recess; Scolder, it is formed at respectively in this recess; Patterned metal layer, it is formed on this first insulating protective layer and the scolder, and connects this scolder, and this patterned metal layer also has a plurality of electric connection pads; And second insulating protective layer, it is formed on this patterned metal layer and first insulating protective layer, and has a plurality of correspondences and expose the respectively second insulating protective layer perforate of this electric connection pad.
The present invention also provides a kind of encapsulating structure, and it comprises: a substrate, and it comprises: first insulating protective layer, a plurality of first insulating protective layer perforates that it has opposite first and second surface and runs through this first surface and second surface; Scolder, it is formed in respectively this first insulating protective layer perforate, and protrudes from this first surface; On the patterned metal layer, its second surface that is formed at this first insulating protective layer and scolder and be connected this scolder, and have a plurality of electric connection pads; And second insulating protective layer, it is formed on the second surface of this patterned metal layer and first insulating protective layer, and has a plurality of correspondences and expose the respectively second insulating protective layer perforate of this electric connection pad; Semiconductor chip, it is arranged on this substrate, and is electrically connected to this patterned metal layer; And packing colloid, it is formed on this second insulating protective layer, and coats this semiconductor chip and electric connection pad.
The present invention also provides a kind of method for making of board structure, it comprises: go up in a surface of a bearing part and form first insulating protective layer, this first insulating protective layer has a plurality of first insulating protective layer perforates that expose the part surface of this bearing part, wherein, this bearing part is to should the first insulating protective layer perforate having a plurality of recesses; In respectively inserting scolder in this recess; Form patterned metal layer on this first insulating protective layer and scolder, this patterned metal layer has a plurality of electric connection pads; And on this patterned metal layer and first insulating protective layer, forming second insulating protective layer, this second insulating protective layer has a plurality of correspondences and exposes the respectively second insulating protective layer perforate of this electric connection pad.
The present invention also provides a kind of method for making of encapsulating structure, and it comprises: a board structure is provided, and it comprises: bearing part, surface thereof have a plurality of recesses; First insulating protective layer, it is formed at this bearing part has on the surface of this recess, and is formed with a plurality of correspondences and exposes the respectively first insulating protective layer perforate of this recess; Scolder, it is inserted respectively in this recess; Patterned metal layer, it is formed on this first insulating protective layer and the scolder, and connects this scolder, and this patterned metal layer also has a plurality of electric connection pads; And second insulating protective layer, it is formed on this patterned metal layer and first insulating protective layer, and has a plurality of correspondences and expose the respectively second insulating protective layer perforate of this electric connection pad; The semiconductor chip is set, and this semiconductor chip is electrically connected to this patterned metal layer on this board structure; Form a packing colloid on this second insulating protective layer, to coat this semiconductor chip and electric connection pad; And remove this bearing part, reach respectively this scolder to expose this first insulating protective layer.
As from the foregoing, because the present invention is by firmly forming scolder (soldered ball) on pin in technology, and this scolder is just exposed in final step, so the coplanarity of this scolder and associativity are better, and residual stress is lower, and then has preferable heavy industry; In addition, technology of the present invention is comparatively simple, and can not produce burr at the pin place, so be conducive to the decline of whole cost and the rising of yield.
Description of drawings
Fig. 1 is the cutaway view of existing square surface non-leaded package.
Fig. 2 is the cutaway view of another kind of existing square surface non-leaded package.
Fig. 3 A to Fig. 3 M is the cutaway view of board structure of the present invention, encapsulating structure and method for making thereof.
The primary clustering symbol description
11,40 semiconductor chips, 12 lead frames
13,42 packing colloids, 14 pins
30 bearing parts, 300 recesses
31 first insulating protective layer 31a first surfaces
The 310 first insulating protective layer perforates of 31b second surface
32 scolders, 33 conductive layers
The 340 resistance layer perforates of 34 resistance layers
35 metal levels, 36 patterned metal layers
361 electric connection pads, 37 second insulating protective layers
370 second insulating protective layer perforates, 38 surface-treated layers
41 bonding wires.
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification discloses.
Notice, the appended graphic structure that illustrates of this specification, ratio, size etc., equal contents in order to cooperate specification to disclose only, understanding and reading for those skilled in the art, be not in order to limit the enforceable qualifications of the present invention, so technical essential meaning of tool not, the adjustment of the modification of any structure, the change of proportionate relationship or size, not influencing under the effect that the present invention can produce and the purpose that can reach, all should still drop on disclosed technology contents and get in the scope that can contain.Simultaneously, quote in this specification as " on " reach terms such as " one ", also understanding for ease of narration only, but not in order to limit the enforceable scope of the present invention, the change of its relativeness or adjustment are under no essence change technology contents, when also being considered as the enforceable category of the present invention.
See also Fig. 3 A to Fig. 3 M, it is the cutaway view of board structure of the present invention, encapsulating structure and method for making thereof.
At first; as shown in Figure 3A; one bearing part 30 is provided; go up mulched ground in a surface of this bearing part 30 and form first insulating protective layer 31; the material of this bearing part 30 can be the conductivity material; as aluminium, copper or other conductive metal, and the material that this first insulating protective layer 31 can be welding resisting layer (as green lacquer) or this first insulating protective layer 31 can be the insulating properties material, and this insulating properties material can be the sensing optical activity material.
Then; shown in Fig. 3 B; remove partly this first insulating protective layer 31; so that in this first insulating protective layer 31, form a plurality of first insulating protective layer perforates 310 that expose the part surface of this bearing part 30, the configuration when making this first insulating protective layer perforate 310 desire to be soldered to circuit board according to product and designing.In present embodiment, be to utilize the eurymeric photoresistance, and through after the exposure imaging technology, partly this first insulating protective layer 31 remove, to form this first insulating protective layer perforate 310.In other embodiment, also can utilize the minus photoresistance to reach The above results.
Shown in Fig. 3 C, remove this bearing part 30 of part in respectively this first insulating protective layer perforate 310, to form a plurality of recesses 300, wherein, the mode that removes this bearing part 30 can be etching or computer numerical control (CNC) processing.
Shown in Fig. 3 D, in respectively inserting scolder 32 in this recess 300, wherein, the mode of inserting this scolder 32 is plating or printing, and can carry out the reflow step again after inserting this scolder 32, to remove the hole (void) in this scolder 32.
Shown in Fig. 3 E, on this first insulating protective layer 31 and scolder 32, form conductive layer 33, wherein, the mode that forms this conductive layer 33 is electroless-plating, sputter or electron beam evaporation plating.
Shown in Fig. 3 F, on this conductive layer 33, form resistance layer 34, this resistance layer 34 has the resistance layer perforate 340 of this conductive layer 33 of a plurality of exposed parts.
Shown in Fig. 3 G, to electroplate on the conductive layer 33 in this resistance layer perforate 340 respectively and form metal level 35, the material of this metal level 35 for example is copper.
Shown in Fig. 3 H to Fig. 3 I, the conductive layer 33 that removes this resistance layer 34 and cover, at this moment, this metal level 35 constitutes this patterned metal layer 36 with conductive layer 33, and this patterned metal layer 36 has a plurality of electric connection pads 361.Wherein, this patterned metal layer 36 is a single layer structure, and flatly is arranged on this first insulating protective layer 31.
Shown in Fig. 3 J, on this patterned metal layer 36 and first insulating protective layer 31, form second insulating protective layer 37, this second insulating protective layer 37 has a plurality of correspondences and exposes the respectively second insulating protective layer perforate 370 of this electric connection pad 361.Wherein, partly this first insulating protective layer 31 directly contacts with this second insulating protective layer 37 of part.
Shown in Fig. 3 K, in respectively forming surface-treated layer 38 on this electric connection pad 361, the material of this surface-treated layer 38 is nickel/gold.So far namely constitute board structure of the present invention.
Shown in Fig. 3 L; on this second insulating protective layer 37, semiconductor chip 40 is set; and by a plurality of bonding wires 41 electric connections this semiconductor chips 40 and electric connection pad 361; and form packing colloid 42 on this second insulating protective layer 37, this packing colloid 42 coats this semiconductor chip 40, bonding wire 41 and electric connection pad 361.
Shown in Fig. 3 M, remove this bearing part 30, to expose respectively this scolder 32; For instance, can use alkaline etching liquid to carry out etching herein, with in this bearing part 30 of etching, this scolder 32 of not etching; Also can comprise this moment carries out reflow (reflow) technology.So far namely constitute encapsulating structure of the present invention.
The present invention also provides a kind of board structure, and it comprises: bearing part 30, surface thereof have a plurality of recesses 300; First insulating protective layer 31, it is formed at this bearing part 30 has on the surface of this recess 300, and is formed with a plurality of correspondences and exposes the respectively first insulating protective layer perforate 310 of this recess 300; Scolder 32, it is formed at respectively in this recess 300; Patterned metal layer 36, it is formed on this first insulating protective layer 31 and the scolder 32, and has a plurality of electric connection pads 361; And second insulating protective layer 37, it is formed on this patterned metal layer 36 and first insulating protective layer 31, and has a plurality of correspondences and expose the respectively second insulating protective layer perforate 370 of this electric connection pad 361.
The present invention provides a kind of encapsulating structure again, and it comprises: first insulating protective layer 31, and it has opposite first 31a and second surface 31b and runs through this first surface 31a and a plurality of first insulating protective layer perforates 310 of second surface 31b; Scolder 32, it is formed in respectively this first insulating protective layer perforate 310, and protrudes from this first surface 31a; Patterned metal layer 36, it is formed on the second surface 31b and scolder 32 of this first insulating protective layer 31, and has a plurality of electric connection pads 361; Second insulating protective layer 37, it is formed on the second surface 31b of this patterned metal layer 36 and first insulating protective layer 31, and has a plurality of correspondences and expose the respectively second insulating protective layer perforate 370 of this electric connection pad 361; Semiconductor chip 40, it is arranged on this second insulating protective layer 37; A plurality of bonding wires 41, it electrically connects this semiconductor chip 40 and electric connection pad 361; And packing colloid 42, it is formed on this second insulating protective layer 37, and coats this semiconductor chip 40, bonding wire 41 and electric connection pad 361.
In aforesaid board structure and encapsulating structure, also comprise surface-treated layer 38, it is formed at respectively on this electric connection pad 361.
In board structure of the present invention and encapsulating structure, the material of this surface-treated layer 38 is nickel/gold.
In described board structure and the encapsulating structure, this scolder 32 flushes in the surface of this first insulating protective layer 31.
Be noted that under identical enforcement concept, the present invention also can be applicable in the encapsulating structure of flip-chip (flip chip).
In sum, than prior art, because the present invention is by firmly forming scolder on pin in technology, and this scolder is just exposed in final step, therefore, coplanarity and the associativity of this scolder are better, and residual stress is lower, and then has preferable heavy industry; In addition, technology of the present invention is comparatively simple, and can not produce burr at the pin place, so be conducive to the decline of whole cost and the rising of yield.
Above-described embodiment is only in order to illustrative principle of the present invention and effect thereof, but not is used for restriction the present invention.Any those skilled in the art all can make amendment to above-described embodiment under spirit of the present invention and category.So the scope of the present invention, should be listed as claims.
Claims (11)
1. board structure, it comprises:
Bearing part, surface thereof have a plurality of recesses;
First insulating protective layer, it is formed at this bearing part has on the surface of this recess, and is formed with a plurality of correspondences and exposes the respectively first insulating protective layer perforate of this recess;
Scolder, it is formed at respectively in this recess;
Patterned metal layer, it is formed on this first insulating protective layer and the scolder, and connects this scolder, and this patterned metal layer also has a plurality of electric connection pads; And
Second insulating protective layer, it is formed on this patterned metal layer and first insulating protective layer, and has a plurality of correspondences and expose the respectively second insulating protective layer perforate of this electric connection pad.
2. encapsulating structure, it comprises:
One substrate, it comprises:
First insulating protective layer, a plurality of first insulating protective layer perforates that it has opposite first and second surface and runs through this first surface and second surface;
Scolder, it is formed in respectively this first insulating protective layer perforate, and protrudes from this first surface;
On the patterned metal layer, its second surface that is formed at this first insulating protective layer and scolder and be connected this scolder, and have a plurality of electric connection pads; And
Second insulating protective layer, it is formed on the second surface of this patterned metal layer and first insulating protective layer, and has a plurality of correspondences and expose the respectively second insulating protective layer perforate of this electric connection pad;
Semiconductor chip, it is arranged on this substrate, and is electrically connected to this patterned metal layer; And
Packing colloid, it is formed on this second insulating protective layer, and coats this semiconductor chip and electric connection pad.
3. structure according to claim 1 and 2 is characterized in that, this structure also comprises surface-treated layer, and it is formed at respectively on this electric connection pad.
4. structure according to claim 3 is characterized in that, the material of this surface-treated layer is nickel/gold.
5. the method for making of a board structure, it comprises:
Formation first insulating protective layer is gone up on a surface in a bearing part, and this first insulating protective layer has a plurality of first insulating protective layer perforates that expose the part surface of this bearing part, and wherein, this bearing part correspondence respectively this first insulating protective layer tapping has recess;
In respectively inserting scolder in this recess;
Form patterned metal layer on this first insulating protective layer and scolder, this patterned metal layer has a plurality of electric connection pads; And
Form second insulating protective layer on this patterned metal layer and first insulating protective layer, this second insulating protective layer has a plurality of correspondences and exposes the respectively second insulating protective layer perforate of this electric connection pad.
6. the method for making of an encapsulating structure, it comprises:
One board structure is provided, and it comprises:
Bearing part, surface thereof have a plurality of recesses;
First insulating protective layer, it is formed at this bearing part has on the surface of this recess, and is formed with a plurality of correspondences and exposes the respectively first insulating protective layer perforate of this recess;
Scolder, it is inserted respectively in this recess;
Patterned metal layer, it is formed on this first insulating protective layer and the scolder, and connects this scolder, and this patterned metal layer also has a plurality of electric connection pads; And
Second insulating protective layer, it is formed on this patterned metal layer and first insulating protective layer, and has a plurality of correspondences and expose the respectively second insulating protective layer perforate of this electric connection pad;
The semiconductor chip is set, and this semiconductor chip is electrically connected to this patterned metal layer on this board structure;
Form a packing colloid on this second insulating protective layer, to coat this semiconductor chip and electric connection pad; And
Remove this bearing part, reach respectively this scolder to expose this first insulating protective layer.
7. according to the method for making of claim 5 or 6 described structures, it is characterized in that the step that forms this patterned metal layer comprises:
On this first insulating protective layer and scolder, form conductive layer;
Form resistance layer on this conductive layer, this resistance layer has the resistance layer perforate of a plurality of these conductive layers of exposed parts;
Form metal level on the conductive layer in this resistance layer perforate respectively; And
The conductive layer that removes this resistance layer and cover, this metal level and conductive layer constitute this patterned metal layer.
8. according to the method for making of claim 5 or 6 described structures, it is characterized in that this method for making also is included in respectively and forms surface-treated layer on this electric connection pad.
9. the method for making of structure according to claim 8 is characterized in that, the material of this surface-treated layer is nickel/gold.
10. according to the method for making of claim 5 or 6 described structures, it is characterized in that, insert the mode of this scolder for electroplating or printing.
11. the method for making of structure according to claim 7 is characterized in that, the mode that forms this conductive layer is electroless-plating, sputter or electron beam evaporation plating.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101106482A TWI462255B (en) | 2012-02-29 | 2012-02-29 | Package structure, substrate structure and fabrication method thereof |
| TW101106482 | 2012-02-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103295994A true CN103295994A (en) | 2013-09-11 |
| CN103295994B CN103295994B (en) | 2016-02-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210059515.XA Expired - Fee Related CN103295994B (en) | 2012-02-29 | 2012-03-08 | packaging structure, substrate structure and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103295994B (en) |
| TW (1) | TWI462255B (en) |
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| US6020218A (en) * | 1997-01-28 | 2000-02-01 | Anam Semiconductor Inc. | Method of manufacturing ball grid array semiconductor package |
| US20040229398A1 (en) * | 2001-05-31 | 2004-11-18 | International Business Machines Corporation | Method of manufacture of silicon based package and devices manufactured thereby |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6306685B1 (en) * | 2000-02-01 | 2001-10-23 | Advanced Semiconductor Engineering, Inc. | Method of molding a bump chip carrier and structure made thereby |
| TW200503208A (en) * | 2003-07-08 | 2005-01-16 | Advanced Semiconductor Eng | Composite package |
| TWI292612B (en) * | 2006-02-27 | 2008-01-11 | Siliconware Precision Industries Co Ltd | Semiconductor package and fabrication method thereof |
| US20100044850A1 (en) * | 2008-08-21 | 2010-02-25 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
| US8124447B2 (en) * | 2009-04-10 | 2012-02-28 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
| TWI405312B (en) * | 2009-07-17 | 2013-08-11 | Advanced Semiconductor Eng | Semiconductor package structure, carrier thereof and manufacturing method for the same |
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2012
- 2012-02-29 TW TW101106482A patent/TWI462255B/en not_active IP Right Cessation
- 2012-03-08 CN CN201210059515.XA patent/CN103295994B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5953589A (en) * | 1996-12-30 | 1999-09-14 | Anam Semiconductor Inc. | Ball grid array semiconductor package with solder balls fused on printed circuit board and method for fabricating the same |
| US6020218A (en) * | 1997-01-28 | 2000-02-01 | Anam Semiconductor Inc. | Method of manufacturing ball grid array semiconductor package |
| CN1221982A (en) * | 1997-11-21 | 1999-07-07 | 罗姆股份有限公司 | Semiconductor device and its mfg. method |
| US20040229398A1 (en) * | 2001-05-31 | 2004-11-18 | International Business Machines Corporation | Method of manufacture of silicon based package and devices manufactured thereby |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103295994B (en) | 2016-02-03 |
| TW201336033A (en) | 2013-09-01 |
| TWI462255B (en) | 2014-11-21 |
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