CN103281069B - A kind of IO multiplexing port - Google Patents
A kind of IO multiplexing port Download PDFInfo
- Publication number
- CN103281069B CN103281069B CN201310233427.1A CN201310233427A CN103281069B CN 103281069 B CN103281069 B CN 103281069B CN 201310233427 A CN201310233427 A CN 201310233427A CN 103281069 B CN103281069 B CN 103281069B
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- China
- Prior art keywords
- driving amplifier
- port
- nmos pipe
- led lamp
- pmos
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Circuit Arrangement For Electric Light Sources In General (AREA)
Abstract
The invention discloses a kind of IO multiplexing port, comprise the first driving amplifier U1 and the second driving amplifier U2, described the first driving amplifier U1 and the second driving amplifier U2 are connected in parallel between port and internal circuit, also comprise a LED lamp control circuit, LED lamp control circuit comprises NMOS pipe Q3 and NMOS pipe Q4. The invention has the beneficial effects as follows: this circuit is being input and output the two supports port by electrical equipment port translation, the volume of the electrical equipment not only reducing, also facilitated use, then in IO port, a control circuit has been set, IO port can be accessed by LED lamp, control circuit can be controlled the brightness of LED lamp, make like this IO port be able to multiplexing, not only as the input and output of electronic equipment, in the time that electronic equipment breaks down, access LED lamp, convenient maintenance.
Description
Technical field
The present invention relates to a multiplexing port, particularly relate to a kind of IO multiplexing port.
Background technology
The input and output of existing a lot of devices are all divided into two ports, have increased like this volume of device, and two-port need to insert respectively input and output, also inconvenient when use.
Summary of the invention
The object of the invention is to overcome the shortcoming and defect of above-mentioned prior art, a kind of IO multiplexing port is provided, solve excessive, the awkward defect of device volume of existing dual-port (i.e. input, output port).
Object of the present invention is achieved through the following technical solutions: a kind of IO multiplexing port, comprise the first driving amplifier U1 and the second driving amplifier U2, described the first driving amplifier U1 and the second driving amplifier U2 are connected in parallel between port and internal circuit, the input of the first driving amplifier U1 is connected to port, output is connected to internal circuit, the input of the second driving amplifier U2 connects internal circuit, output connectivity port, also comprise a LED lamp control circuit, LED lamp control circuit comprises NMOS pipe Q3 and NMOS pipe Q4, all ground connection of source electrode of described NMOS pipe Q3 and NMOS pipe Q4, the drain electrode of NMOS pipe Q3 connects IO port, the drain electrode of NMOS pipe Q4 connects the grid of NMOS pipe Q3, the grid of NMOS pipe Q4 is connected to a relay J 2. in this circuit, relay J 2 is to control the master switch of LED lamp control circuit, and relay J 2 is controlled after the disconnection of LED lamp control circuit, when the first driving amplifier U1 starts, when the second amplifier U2 closes, from port to internal circuit, connect, port is input port, when the first driving amplifier U2 closes, the second driving amplifier U2 starts, and from internal circuit to port, connects, and port is output port. when closing the first driving amplifier U1 and the second driving amplifier U2, relay J 2 is opened LED lamp control circuit, and makes IO port access a LED lamp, LED lamp one termination IO port, another termination power, and can control by relay J 2 brightness of LED lamp.
Further, on the first above-mentioned driving amplifier U1 and the power circuit of the second driving amplifier U2, be respectively arranged with PMOS pipe Q1 and PMOS pipe Q2, the i.e. power cathode ground connection of the first driving amplifier U1 and the second driving amplifier U2, the positive source of the first driving amplifier U1 is managed Q1 by PMOS and is connected to power supply, and the positive source of the second driving amplifier U2 is managed Q2 by PMOS and is connected to power supply. Manage Q1 by PMOS and control the first driving amplifier U1, PMOS pipe Q2 controls the second driving amplifier U2, is convenient to the conversion of port input and output.
Further, the grid of above-mentioned PMOS pipe Q1 and PMOS pipe Q2 is connected to a controller, by controller control PMOS pipe Q1 and PMOS pipe Q2.
Further, between the power cathode of above-mentioned the first driving amplifier U1 and ground connection, be provided with a NMOS pipe Q5, between the power cathode of the second driving amplifier U2 and ground connection, be provided with a NMOS pipe Q6, the grid of NMOS pipe Q5 and NMOS pipe Q6 is also connected to controller, ground connection place arranges a FET again, the power supply of the first driving amplifier U1 can be managed Q1 and NMOS pipe Q5 control by PMOS, when PMOS pipe Q1 and NMOS pipe Q5 damage one, do not affect the use of whole device, the power supply of the second driving amplifier U2 can be managed Q2 and NMOS pipe Q6 control by PMOS simultaneously, Q2, when one of them damage of Q6, do not affect the use of whole device yet.
The invention has the beneficial effects as follows: this circuit is being input and output the two supports port by electrical equipment port translation, the volume of the electrical equipment not only reducing, also facilitated use, then in IO port, a control circuit has been set, IO port can be accessed by LED lamp, control circuit can be controlled the brightness of LED lamp, make like this IO port be able to multiplexing, not only as the input and output of electronic equipment, in the time that electronic equipment breaks down, access LED lamp, convenient maintenance.
Brief description of the drawings
Fig. 1 is the structural representation of embodiment 1;
Fig. 2 is the structural representation of embodiment 2;
Fig. 3 is the structural representation of embodiment 3.
Detailed description of the invention
Below in conjunction with embodiment, the present invention is described in further detail, but structure of the present invention is not limited only to following examples:
[embodiment 1]
As shown in Figure 1, a kind of IO multiplexing port, comprise the first driving amplifier U1 and the second driving amplifier U2, described the first driving amplifier U1 and the second driving amplifier U2 are connected in parallel between port and internal circuit, the input of the first driving amplifier U1 is connected to port, output is connected to internal circuit, and the input of the second driving amplifier U2 connects internal circuit, output connectivity port. In this circuit, relay J 2 is to control the master switch of LED lamp control circuit, and relay J 2 is controlled after the disconnection of LED lamp control circuit, when the first driving amplifier U1 starts, when the second amplifier U2 closes, from port to internal circuit, connect, port is input port; When the first driving amplifier U2 closes, the second driving amplifier U2 starts, and from internal circuit to port, connects, and port is output port. When closing the first driving amplifier U1 and the second driving amplifier U2, relay J 2 is opened LED lamp control circuit, and makes IO port access a LED lamp, LED lamp one termination IO port, another termination power, and can control by relay J 2 brightness of LED lamp.
[embodiment 2]
As shown in Figure 2, the present embodiment is on the basis of embodiment 1, on the power circuit of the first driving amplifier U1 and the second driving amplifier U2, be respectively arranged with PMOS pipe Q1 and PMOS pipe Q2, the i.e. power cathode ground connection of the first driving amplifier U1 and the second driving amplifier U2, the positive source of the first driving amplifier U1 is managed Q1 by PMOS and is connected to power supply, and the positive source of the second driving amplifier U2 is managed Q2 by PMOS and is connected to power supply. Manage Q1 by PMOS and control the first driving amplifier U1, PMOS pipe Q2 controls the second driving amplifier U2, is convenient to the conversion of port input and output.
The grid of above-mentioned PMOS pipe Q1 and PMOS pipe Q2 is connected to a controller, by controller control PMOS pipe Q1 and PMOS pipe Q2.
[embodiment 3]
As shown in Figure 3, the present embodiment is on the basis of embodiment 2, between the power cathode of the first driving amplifier U1 and ground connection, be provided with a NMOS pipe Q5, between the power cathode of the second driving amplifier U2 and ground connection, be provided with a NMOS pipe Q6, the grid of NMOS pipe Q5 and NMOS pipe Q6 is also connected to controller, ground connection place arranges a FET again, the power supply of the first driving amplifier U1 can be managed Q1 and NMOS pipe Q5 control by PMOS, when PMOS pipe Q1 and NMOS pipe Q5 damage one, do not affect the use of whole device, the power supply of the second driving amplifier U2 can be managed Q2 and NMOS pipe Q6 control by PMOS simultaneously, Q2, when one of them damage of Q6, do not affect the use of whole device yet.
Claims (2)
1. an IO multiplexing port, comprise the first driving amplifier (U1) and the second driving amplifier (U2), described the first driving amplifier (U1) and the second driving amplifier (U2) are connected in parallel between port and internal circuit, the input of the first driving amplifier (U1) is connected to port, output is connected to internal circuit, the input of the second driving amplifier (U2) connects internal circuit, output connectivity port, it is characterized in that, also comprise a LED lamp control circuit, LED lamp control circuit comprises NMOS pipe Q3 and NMOS pipe Q4, all ground connection of source electrode of described NMOS pipe Q3 and NMOS pipe Q4, the drain electrode of NMOS pipe Q3 connects IO port, the drain electrode of NMOS pipe Q4 connects the grid of NMOS pipe Q3, the grid of NMOS pipe Q4 is connected to a relay (J2),
On described the first driving amplifier (U1) and the power circuit of the second driving amplifier (U2), be respectively arranged with PMOS pipe Q1 and PMOS pipe Q2, the i.e. power cathode ground connection of the first driving amplifier (U1) and the second driving amplifier (U2), the positive source of the first driving amplifier (U1) is managed Q1 by PMOS and is connected to power supply, and the positive source of the second driving amplifier (U2) is managed Q2 by PMOS and is connected to power supply;
The grid of described PMOS pipe Q1 and PMOS pipe Q2 is connected to a controller (J1).
2. a kind of IO multiplexing port according to claim 1, it is characterized in that, between the power cathode of the first driving amplifier (U1) and ground connection, be provided with a NMOS pipe Q5, between the power cathode of the second driving amplifier (U2) and ground connection, be provided with a NMOS pipe Q6, the grid of NMOS pipe Q5 and NMOS pipe Q6 is also connected to controller (J1).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN201310233427.1A CN103281069B (en) | 2013-06-14 | 2013-06-14 | A kind of IO multiplexing port |
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CN201310233427.1A CN103281069B (en) | 2013-06-14 | 2013-06-14 | A kind of IO multiplexing port |
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CN103281069A CN103281069A (en) | 2013-09-04 |
CN103281069B true CN103281069B (en) | 2016-05-11 |
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CN201310233427.1A Expired - Fee Related CN103281069B (en) | 2013-06-14 | 2013-06-14 | A kind of IO multiplexing port |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN201219256Y (en) * | 2008-06-05 | 2009-04-08 | 苏州市华芯微电子有限公司 | Input/output bidirectional port |
CN101841321A (en) * | 2009-03-20 | 2010-09-22 | 广芯电子技术(上海)有限公司 | Two-way transmission interface circuit between two disconnected power supplies for changing rise time |
US7859294B1 (en) * | 2009-01-22 | 2010-12-28 | Xilinx, Inc. | Method and arrangement for reducing power in bidirectional input/output ports |
CN102809930A (en) * | 2012-07-27 | 2012-12-05 | 三一重工股份有限公司 | Input/output multiplexing port and controller |
-
2013
- 2013-06-14 CN CN201310233427.1A patent/CN103281069B/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN201219256Y (en) * | 2008-06-05 | 2009-04-08 | 苏州市华芯微电子有限公司 | Input/output bidirectional port |
US7859294B1 (en) * | 2009-01-22 | 2010-12-28 | Xilinx, Inc. | Method and arrangement for reducing power in bidirectional input/output ports |
CN101841321A (en) * | 2009-03-20 | 2010-09-22 | 广芯电子技术(上海)有限公司 | Two-way transmission interface circuit between two disconnected power supplies for changing rise time |
CN102809930A (en) * | 2012-07-27 | 2012-12-05 | 三一重工股份有限公司 | Input/output multiplexing port and controller |
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CN103281069A (en) | 2013-09-04 |
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Effective date of registration: 20200714 Address after: 233000 No.10, building 32, Zone 8, Guangcai market, bengshan District, Bengbu City, Anhui Province Patentee after: Bengbu Shangwei Intellectual Property Operations Co.,Ltd. Address before: 610000 Shiyang Industrial Park, hi tech Zone, Chengdu, Sichuan Patentee before: CHENGDU RUIYI INFORMATION TECHNOLOGY Co.,Ltd. |
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CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160511 |