CN101841321A

CN101841321A - Two-way transmission interface circuit between two disconnected power supplies for changing rise time

Info

Publication number: CN101841321A
Application number: CN200910047873A
Authority: CN
Inventors: 戴忠伟; 张远斌
Original assignee: BROADCHIP TECHNOLOGY GROUP Ltd
Current assignee: BROADCHIP TECHNOLOGY GROUP Ltd
Priority date: 2009-03-20
Filing date: 2009-03-20
Publication date: 2010-09-22

Abstract

The invention provides a two-way transmission interface circuit between two disconnected power supplies for changing rise time, comprising R1 for connecting VCC1, R2 for connecting VCC2, a first PMOS (P-channel Metal Oxide Semiconductor) tube and a second PMOS tube, wherein the other end of the R1 is connected with the source electrode of an NMOS (N-channel Metal Oxide Semiconductor) tube, the grid electrode of the NMOS tube is connected with the lower one in the VVC1 and the VCC2, and the drain electrode of the NMOS tube is connected with the other end of the R2; the first PMOS tube and the second PMOS tube are respectively connected with the R1 and the R2 in parallel; the source electrodes of the first PMOS tube and the second PMOS tube are respectively connected with the VVC1 and the VCC2, and the grid electrodes of the first PMOS tube and the second PMOS tube are respectively connected with the output ends of a first one shot and a second one shot; the input ends of the first one shot and the second one shot are respectively connected with the output ends of a first comparator and a second comparator; the inverted input ends of the first comparator and the second comparator are respectively connected with the drain electrodes of the first PMOS tube and the second PMOS tube, and the normal phase input ends of the first comparator and the second comparator are connected with a reference voltage. The invention has the advantage of shortening the rise time of a circuit during transmission with lower cost.

Description

Bidirectional transmission interface circuit between two non-communicated power supplies of change rise time

Technical field

The present invention relates to a kind of interface circuit, relate in particular to the bidirectional transmission interface circuit between a kind of two non-communicated power supply systems.

Background technology

As seen from Figure 1: wherein 1 end is connected the obstructed power-supply system (VCC1 and VCC2) of two covers respectively with 2 ends, transmission principle is: to be transmitted as example from 1 end to 2 ends, during the transmission low level, 1 node is driven by external open-drain N pipe and moves ground to, because the M1 pipe is conducting, and its conducting resistance is much smaller than R2, thus 2 also be pulled to ground, just low level has been transferred to 2 points; When external open-drain N pipe drive be turned off after, 1,2 liang of node is moved to separately supply voltage by R1, R2 respectively, thereby has finished the transmission of high level.Data are identical therewith to the transmission course of 1 end from 2 ends.

From the above: the transmission of high level is external open-drain N pipe driving to be closed to have no progeny draw high corresponding supply voltage by resistance R 1 and R2.This process is an example with 2 nodes as shown in Figure 2, and CL is a load capacitance, electric current by R2 charges to electric capacity, thereby makes 2 node voltages slowly rise to VCC2, when one timing of CL size, rise time, by the resistance decision of R2, the big more rise time of resistance was long more fully.Nowadays all require the rise time as far as possible little in the major applications, the resistance that is to say R2 in this structure also should be as far as possible little, if but the too little meeting of resistance of R2 when causing transmitting low level the power consumption of circuit excessive, and the driving force that at this moment external open-drain N pipe is driven requires higher.

Summary of the invention

The technical issues that need to address of the present invention have provided the bidirectional transmission interface circuit between a kind of two different electrical power that change the rise time, are intended to solve the above problems.

In order to solve the problems of the technologies described above, the present invention is achieved by the following technical solutions:

The present invention includes: first resistance and second resistance that is connected second source voltage that connect first supply voltage; The other end of first resistance connects the source electrode of NMOS pipe, and the grid of NMOS pipe and first supply voltage link to each other with junior in the second source voltage, and the drain electrode of NMOS pipe links to each other with the second resistance other end; Also comprise: PMOS pipe and the 2nd PMOS pipe; Described PMOS pipe and the 2nd PMOS manage respectively with first resistance and second resistance and connect; The one PMOS pipe links to each other with second source voltage with first supply voltage respectively with the source electrode of the 2nd PMOS pipe, and PMOS pipe links to each other with the output of first " circuits for triggering " and second " circuits for triggering " respectively with the grid of the 2nd PMOS pipe; The input of first " circuits for triggering " and second " circuits for triggering " links to each other with the output of first comparator with second comparator respectively; The inverting input of first comparator and second comparator links to each other with the drain electrode of the 2nd PMOS pipe with PMOS pipe respectively, and normal phase input end links to each other with reference voltage.

Compared with prior art, the invention has the beneficial effects as follows: utilize lower cost, the rise time shortens when making circuit transmission.

Description of drawings

Fig. 1 is the bidirectional transmission interface circuit figure between two different electrical power systems in the prior art;

Fig. 2 is a rise time schematic diagram (is example with resistance R 2) when adopting the circuit transmission of Fig. 1 structure;

Fig. 3 is structural representation of the present invention (another side of first resistance R 1 that is connected with 2 equivalences of second resistance R not shown in the figures).

Embodiment

Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail:

As seen from Figure 3: the present invention includes: first resistance R 1 and second resistance R 2 that is connected second source voltage VCC2 that connect the first supply voltage VCC1; The other end of first resistance R 1 connects the source electrode of NMOS pipe M1, and the grid of NMOS pipe M1 and the first supply voltage VCC1 link to each other with junior among the second source voltage VCC2, and the drain electrode that NMOS manages M1 links to each other with second resistance R, 2 other ends; Also comprise: PMOS pipe M2 and the 2nd PMOS pipe M3; Described PMOS pipe M2 and the 2nd PMOS pipe M3 are respectively with first resistance R 1 and second resistance R 2 and connect; The one PMOS pipe M2 links to each other with second source voltage VCC2 with the first supply voltage VCC1 respectively with the source electrode of the 2nd PMOS pipe M3, and PMOS pipe M2 links to each other with the output of first " circuits for triggering " (one shot) and second " circuits for triggering " respectively with the grid of the 2nd PMOS pipe M3; The input of first " circuits for triggering " and second " circuits for triggering " links to each other with the output of first comparator with second comparator respectively; The inverting input of first comparator and second comparator links to each other with the drain electrode of the 2nd PMOS pipe M3 with PMOS pipe M2 respectively, and normal phase input end links to each other with reference voltage (VREF).

The present invention satisfies the requirement of low-power consumption earlier, promptly gets bigger resistance, the rise time when adding auxiliary circuit shortening transmission high level again.As shown in Figure 3, give R2 PMOS pipe in parallel M3 (is example with resistance R 2), electric current is by in the process of R2 to the load capacitance charging, give grid end (i.e. 5 nodes) the low pulse of M3 in the suitable moment, allow the M3 conducting, thereby significantly strengthen electric current, so the rise time of 2 nodes has also shortened greatly to the electric capacity charging, again PMOS is managed M3 later on and turn-offs when 2 node voltages reach high level, make its to low level transmission without any influence.

The function of the one shot module of prior art is among the figure: when trailing edge appearred in input, output produced a low pulse, reverts to high level then again.Under the initial condition, the external open-drain in 1 node place drives open-minded, and 1,2,3 nodes all are pulled to ground, and the electric current by R2 is VCC2/R2.The inverting input voltage ratio positive input of comparator C OMP is low, so 4 nodes are high level, through one shot processing of circuit, 5 nodes also are high, and M3 turn-offs; In the time will transmitting high level, the external open-drain in 1 node place drives and turn-offs, at this moment the electric current by R2 begins to charge to 2 nodes, 2 node voltages slowly raise, when the voltage of 2 nodes meets and exceeds VREF, comparator C OMP upset, 4 node voltages are low by high saltus step, and one shot electric circuit inspection is exported low pulse behind this trailing edge, and promptly 5 nodes become low, the M3 conducting, electric current by M3 is given 2 node quick charges, makes 2 node voltages be elevated to VCC2 rapidly, and one shot circuit allows 5 node voltages automatically restore to high level afterwards, M3 turn-offs, and only remaining R2 keeps the high level of 2 nodes.So far whole transmission course has been finished.

Claims

1. the bidirectional transmission interface circuit between two different electrical power that change the rise time comprises: first resistance and second resistance that is connected second source voltage that connect first supply voltage; The other end of first resistance connects the source electrode of NMOS pipe, and the grid of NMOS pipe and first supply voltage link to each other with junior in the second source voltage, and the drain electrode of NMOS pipe links to each other with the second resistance other end; It is characterized in that also comprising: PMOS pipe and the 2nd PMOS pipe; Described PMOS pipe and the 2nd PMOS manage respectively with first resistance and second resistance and connect; The one PMOS pipe links to each other with second source voltage with first supply voltage respectively with the source electrode of the 2nd PMOS pipe, and PMOS pipe links to each other with the output of first " circuits for triggering " and second " circuits for triggering " respectively with the grid of the 2nd PMOS pipe; The input of first " circuits for triggering " and second " circuits for triggering " links to each other with the output of first comparator with second comparator respectively; The inverting input of first comparator and second comparator links to each other with the drain electrode of the 2nd PMOS pipe with PMOS pipe respectively, and normal phase input end links to each other with reference voltage.