CN103281069A - IO multiplexing port - Google Patents
IO multiplexing port Download PDFInfo
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- CN103281069A CN103281069A CN2013102334271A CN201310233427A CN103281069A CN 103281069 A CN103281069 A CN 103281069A CN 2013102334271 A CN2013102334271 A CN 2013102334271A CN 201310233427 A CN201310233427 A CN 201310233427A CN 103281069 A CN103281069 A CN 103281069A
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- port
- driving amplifier
- nmos pipe
- pipe
- led lamp
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- Circuit Arrangement For Electric Light Sources In General (AREA)
Abstract
The invention discloses an IO multiplexing port comprising a first drive amplifier U1 and a second drive amplifier U2, wherein the first drive amplifier U1 and the second drive amplifier U2 are in parallel connection between a port and an internal circuit. The IO multiplexing port further comprises an LED lamp control circuit comprising an NMOS tube Q3 and an NMOS tube Q4. The IO multiplexing port has the advantages that an electric appliance port is converted into an input and output port, the size of an electric appliance is reduced, and use is facilitated. A control circuit is additionally arranged on the IO port, an LED lamp can be connected with the IO port, and the control circuit can control the brightness of the LED lamp, so that the IO port can be multiplex. The IO multiplexing port can serve as an input port and an output port of electronic equipment, and the LED lamp can be connected with the IO port for convenient overhaul when the electronic equipment breaks down.
Description
Technical field
The present invention relates to a multiplexing port, particularly relate to a kind of IO multiplexing port.
Background technology
The input and output of existing a lot of devices all are divided into two ports, have increased the volume of device like this, and two-port need insert input and output respectively, and are also inconvenient during use.
Summary of the invention
The objective of the invention is to overcome the shortcoming and defect of above-mentioned prior art, a kind of IO multiplexing port is provided, solve excessive, the awkward defective of device volume of existing dual-port (i.e. input, output port).
Purpose of the present invention is achieved through the following technical solutions: a kind of IO multiplexing port, comprise the first driving amplifier U1 and the second driving amplifier U2, the described first driving amplifier U1 and the second driving amplifier U2 are connected in parallel between port and the internal circuit, the input of the first driving amplifier U1 is connected to port, output is connected to internal circuit, the input of the second driving amplifier U2 connects internal circuit, the output connectivity port, also comprise a LED lamp control circuit, the LED lamp control circuit comprises NMOS pipe Q3 and NMOS pipe Q4, the source electrode of described NMOS pipe Q3 and NMOS pipe Q4 is ground connection all, the drain electrode of NMOS pipe Q3 connects the IO port, the drain electrode of NMOS pipe Q4 connects the grid of NMOS pipe Q3, and the grid of NMOS pipe Q4 is connected to a relay J 2.In this circuit, relay J 2 is master switchs of control LED lamp control circuit, after relay J 2 control LED lamp control circuits disconnect, when the first driving amplifier U1 starts, when the second amplifier U2 closes, then connect from the port to the internal circuit, port is input port; When the first driving amplifier U2 closes, the second driving amplifier U2 starts, and then circuit is to the port connection internally, and port is output port.When closing the first driving amplifier U1 and the second driving amplifier U2, relay J 2 is opened the LED lamp control circuit, and makes the IO port insert a LED lamp, LED lamp one termination IO port, another termination power, and can be by the brightness of relay J 2 control LED lamps.
Further, be respectively arranged with PMOS pipe Q1 and PMOS pipe Q2 on the first above-mentioned driving amplifier U1 and the power circuit of the second driving amplifier U2, the i.e. power cathode ground connection of the first driving amplifier U1 and the second driving amplifier U2, the positive source of the first driving amplifier U1 is connected to power supply by PMOS pipe Q1, and the positive source of the second driving amplifier U2 is connected to power supply by PMOS pipe Q2.Q1 controls the first driving amplifier U1 by the PMOS pipe, and PMOS pipe Q2 controls the second driving amplifier U2, is convenient to the conversion of port input and output.
Further, the grid of above-mentioned PMOS pipe Q1 and PMOS pipe Q2 is connected to a controller, by controller control PMOS pipe Q1 and PMOS pipe Q2.
Further, be provided with a NMOS pipe Q3 between the power cathode of the above-mentioned first driving amplifier U1 and the ground connection, be provided with a NMOS pipe Q4 between the power cathode of the second driving amplifier U2 and the ground connection, the grid of NMOS pipe Q3 and NMOS pipe Q4 also is connected to controller, the ground connection place arranges a field effect transistor again, namely the power supply of the first driving amplifier U1 can be managed Q1 and NMOSQ3 control by PMOS, when PMOS pipe Q1 and NMOSQ3 damage one, do not influence the use of entire device, the power supply of the second driving amplifier U2 can be managed Q2 and NMOSQ4 control by PMOS simultaneously, Q2, during one of them damage of Q4, do not influence the use of entire device yet.
The invention has the beneficial effects as follows: this circuit is being input and output the two supports port with the electrical equipment port translation, the volume of the electrical equipment that not only reduces, also made things convenient for use, a control circuit is set in the IO port again, the IO port can insert the LED lamp, control circuit can be controlled the brightness of LED lamp, it is multiplexing to make that like this IO port is able to, not only as the input and output of electronic equipment, when electronic equipment breaks down, insert the LED lamp, convenient maintenance.
Description of drawings
Fig. 1 is the structural representation of embodiment 1;
Fig. 2 is the structural representation of embodiment 2;
Fig. 3 is the structural representation of embodiment 3.
Embodiment
The present invention is described in further detail below in conjunction with embodiment, but structure of the present invention is not limited only to following examples:
[embodiment 1]
As shown in Figure 1, a kind of IO multiplexing port, comprise the first driving amplifier U1 and the second driving amplifier U2, the described first driving amplifier U1 and the second driving amplifier U2 are connected in parallel between port and the internal circuit, the input of the first driving amplifier U1 is connected to port, output is connected to internal circuit, and the input of the second driving amplifier U2 connects internal circuit, output connectivity port.In this circuit, relay J 2 is master switchs of control LED lamp control circuit, after relay J 2 control LED lamp control circuits disconnect, when the first driving amplifier U1 starts, when the second amplifier U2 closes, then connect from the port to the internal circuit, port is input port; When the first driving amplifier U2 closes, the second driving amplifier U2 starts, and then circuit is to the port connection internally, and port is output port.When closing the first driving amplifier U1 and the second driving amplifier U2, relay J 2 is opened the LED lamp control circuit, and makes the IO port insert a LED lamp, LED lamp one termination IO port, another termination power, and can be by the brightness of relay J 2 control LED lamps.
[embodiment 2]
As shown in Figure 2, present embodiment is on the basis of embodiment 1, power circuit at the first driving amplifier U1 and the second driving amplifier U2 is respectively arranged with PMOS pipe Q1 and PMOS pipe Q2, the i.e. power cathode ground connection of the first driving amplifier U1 and the second driving amplifier U2, the positive source of the first driving amplifier U1 is connected to power supply by PMOS pipe Q1, and the positive source of the second driving amplifier U2 is connected to power supply by PMOS pipe Q2.Q1 controls the first driving amplifier U1 by the PMOS pipe, and PMOS pipe Q2 controls the second driving amplifier U2, is convenient to the conversion of port input and output.
The grid of above-mentioned PMOS pipe Q1 and PMOS pipe Q2 is connected to a controller, by controller control PMOS pipe Q1 and PMOS pipe Q2.
[embodiment 3]
As shown in Figure 3, present embodiment is on the basis of embodiment 2, between the power cathode of the first driving amplifier U1 and ground connection, be provided with a NMOS pipe Q3, be provided with a NMOS pipe Q4 between the power cathode of the second driving amplifier U2 and the ground connection, the grid of NMOS pipe Q3 and NMOS pipe Q4 also is connected to controller, the ground connection place arranges a field effect transistor again, namely the power supply of the first driving amplifier U1 can be managed Q1 and NMOSQ3 control by PMOS, when PMOS pipe Q1 and NMOSQ3 damage one, do not influence the use of entire device, the power supply of the second driving amplifier U2 can be managed Q2 and NMOSQ4 control by PMOS simultaneously, Q2, during one of them damage of Q4, do not influence the use of entire device yet.
Claims (4)
1. IO multiplexing port, comprise the first driving amplifier U1 and the second driving amplifier U2, the described first driving amplifier U1 and the second driving amplifier U2 are connected in parallel between port and the internal circuit, the input of the first driving amplifier U1 is connected to port, output is connected to internal circuit, the input of the second driving amplifier U2 connects internal circuit, the output connectivity port, it is characterized in that, also comprise a LED lamp control circuit, the LED lamp control circuit comprises NMOS pipe Q3 and NMOS pipe Q4, the source electrode of described NMOS pipe Q3 and NMOS pipe Q4 is ground connection all, the drain electrode of NMOS pipe Q3 connects the IO port, and the drain electrode of NMOS pipe Q4 connects the grid of NMOS pipe Q3, and the grid of NMOS pipe Q4 is connected to a relay J 2.
2. a kind of IO multiplexing port according to claim 1, it is characterized in that, be respectively arranged with PMOS pipe Q1 and PMOS pipe Q2 on the power circuit of the described first driving amplifier U1 and the second driving amplifier U2, the i.e. power cathode ground connection of the first driving amplifier U1 and the second driving amplifier U2, the positive source of the first driving amplifier U1 is connected to power supply by PMOS pipe Q1, and the positive source of the second driving amplifier U2 is connected to power supply by PMOS pipe Q2.
3. a kind of IO multiplexing port according to claim 2 is characterized in that, the grid of described PMOS pipe Q1 and PMOS pipe Q2 is connected to a controller J1.
4. a kind of IO multiplexing port according to claim 3, it is characterized in that, be provided with a NMOS pipe Q3 between the power cathode of the first driving amplifier U1 and the ground connection, be provided with a NMOS pipe Q4 between the power cathode of the second driving amplifier U2 and the ground connection, the grid of NMOS pipe Q3 and NMOS pipe Q4 also is connected to controller J1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310233427.1A CN103281069B (en) | 2013-06-14 | 2013-06-14 | A kind of IO multiplexing port |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310233427.1A CN103281069B (en) | 2013-06-14 | 2013-06-14 | A kind of IO multiplexing port |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103281069A true CN103281069A (en) | 2013-09-04 |
| CN103281069B CN103281069B (en) | 2016-05-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310233427.1A Expired - Fee Related CN103281069B (en) | 2013-06-14 | 2013-06-14 | A kind of IO multiplexing port |
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| Country | Link |
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| CN (1) | CN103281069B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201219256Y (en) * | 2008-06-05 | 2009-04-08 | 苏州市华芯微电子有限公司 | Input/output bidirectional port |
| CN101841321A (en) * | 2009-03-20 | 2010-09-22 | 广芯电子技术(上海)有限公司 | Two-way transmission interface circuit between two disconnected power supplies for changing rise time |
| US7859294B1 (en) * | 2009-01-22 | 2010-12-28 | Xilinx, Inc. | Method and arrangement for reducing power in bidirectional input/output ports |
| CN102809930A (en) * | 2012-07-27 | 2012-12-05 | 三一重工股份有限公司 | Input/output multiplexing port and controller |
-
2013
- 2013-06-14 CN CN201310233427.1A patent/CN103281069B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201219256Y (en) * | 2008-06-05 | 2009-04-08 | 苏州市华芯微电子有限公司 | Input/output bidirectional port |
| US7859294B1 (en) * | 2009-01-22 | 2010-12-28 | Xilinx, Inc. | Method and arrangement for reducing power in bidirectional input/output ports |
| CN101841321A (en) * | 2009-03-20 | 2010-09-22 | 广芯电子技术(上海)有限公司 | Two-way transmission interface circuit between two disconnected power supplies for changing rise time |
| CN102809930A (en) * | 2012-07-27 | 2012-12-05 | 三一重工股份有限公司 | Input/output multiplexing port and controller |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103281069B (en) | 2016-05-11 |
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Effective date of registration: 20200714 Address after: 233000 No.10, building 32, Zone 8, Guangcai market, bengshan District, Bengbu City, Anhui Province Patentee after: Bengbu Shangwei Intellectual Property Operations Co.,Ltd. Address before: 610000 Shiyang Industrial Park, hi tech Zone, Chengdu, Sichuan Patentee before: CHENGDU RUIYI INFORMATION TECHNOLOGY Co.,Ltd. |
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Granted publication date: 20160511 |
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