CN203289403U - A controllable input-output multiplex port - Google Patents
A controllable input-output multiplex port Download PDFInfo
- Publication number
- CN203289403U CN203289403U CN2013203380380U CN201320338038U CN203289403U CN 203289403 U CN203289403 U CN 203289403U CN 2013203380380 U CN2013203380380 U CN 2013203380380U CN 201320338038 U CN201320338038 U CN 201320338038U CN 203289403 U CN203289403 U CN 203289403U
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- Prior art keywords
- driving amplifier
- port
- output
- input
- pmos
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Abstract
The utility model discloses a controllable input-output multiplex port. The controllable input-output multiplex port comprises a first driving amplifier U1 and a second driving amplifier U2 which are connected in parallel between the port and an internal circuit. The input end of the first driving amplifier U1 is connected with the port, while the output end of the first driving amplifier U1 is connected with the internal circuit. The input end of the second driving amplifier U2 is connected with the internal circuit, while the output end of the second driving amplifier U2 is connected with the port. The controllable input-output multiplex port has a beneficial effect that a circuit converts a port of an electric appliance into an input-output double-support port so as to reduce the size of the electric appliance and facilitate use.
Description
Technical field
The utility model relates to a multiplexing port, particularly relates to a kind of controlled input and output multiplexing port.
Background technology
The input and output of existing a lot of devices all are divided into two ports, have increased like this volume of device, and two-port need to insert respectively input and output, and are also inconvenient during use.
The utility model content
The purpose of this utility model is to overcome the shortcoming and defect of above-mentioned prior art, and a kind of controlled input and output multiplexing port is provided, and solves excessive, the awkward defect of device volume of existing dual-port (i.e. input, output port).
The purpose of this utility model is achieved through the following technical solutions: controlled input and output multiplexing port, comprise the first driving amplifier U1 and the second driving amplifier U2, described the first driving amplifier U1 and the second driving amplifier U2 are connected in parallel between port and internal circuit, the input of the first driving amplifier U1 is connected to port, output is connected to internal circuit, the input of the second driving amplifier U2 connects internal circuit, output connectivity port.In this circuit,, when the first driving amplifier U1 starts, when the second amplifier U2 closes, connect from the port to the internal circuit, port is input port; When the first driving amplifier U2 closes, the second driving amplifier U2 starts, and circuit connects to port internally, and port is output port.
Further, be respectively arranged with PMOS pipe Q1 and PMOS pipe Q2 on the first above-mentioned driving amplifier U1 and the power circuit of the second driving amplifier U2, the i.e. power cathode ground connection of the first driving amplifier U1 and the second driving amplifier U2, the positive source of the first driving amplifier U1 is managed Q1 by PMOS and is connected to power supply, and the positive source of the second driving amplifier U2 is managed Q2 by PMOS and is connected to power supply.Manage Q1 by PMOS and control the first driving amplifier U1, PMOS pipe Q2 controls the second driving amplifier U2, is convenient to the conversion of port input and output.
Further, the grid of above-mentioned PMOS pipe Q1 and PMOS pipe Q2 is connected to a controller, by controller, controls PMOS pipe Q1 and PMOS pipe Q2.
further, be provided with a NMOS pipe Q3 between the power cathode of above-mentioned the first driving amplifier U1 and ground connection, be provided with a NMOS pipe Q4 between the power cathode of the second driving amplifier U2 and ground connection, the grid of NMOS pipe Q3 and NMOS pipe Q4 also is connected to controller, the ground connection place arranges a field effect transistor again, namely the power supply of the first driving amplifier U1 can be managed Q1 and NMOSQ3 control by PMOS, when PMOS pipe Q1 and NMOSQ3 damage one, do not affect the use of whole device, the power supply of the second driving amplifier U2 can be managed Q2 and NMOSQ4 control by PMOS simultaneously, Q2, during one of them damage of Q4, do not affect the use of whole device yet.
The beneficial effects of the utility model are: this circuit is being input and output the two supports port with the electrical equipment port translation, and the volume of the electrical equipment that not only reduces, also facilitated use.
Description of drawings
Fig. 1 is the structural representation of embodiment 1;
Fig. 2 is the structural representation of embodiment 2;
Fig. 3 is the structural representation of embodiment 3.
Embodiment
The utility model is described in further detail below in conjunction with embodiment, but structure of the present utility model is not limited only to following examples:
[embodiment 1]
As shown in Figure 1, controlled input and output multiplexing port, comprise the first driving amplifier U1 and the second driving amplifier U2, described the first driving amplifier U1 and the second driving amplifier U2 are connected in parallel between port and internal circuit, the input of the first driving amplifier U1 is connected to port, output is connected to internal circuit, and the input of the second driving amplifier U2 connects internal circuit, output connectivity port.In this circuit,, when the first driving amplifier U1 starts, when the second amplifier U2 closes, connect from the port to the internal circuit, port is input port; When the first driving amplifier U2 closes, the second driving amplifier U2 starts, and circuit connects to port internally, and port is output port.
[embodiment 2]
As shown in Figure 2, the present embodiment is on the basis of embodiment 1, be respectively arranged with PMOS pipe Q1 and PMOS pipe Q2 on the power circuit of the first driving amplifier U1 and the second driving amplifier U2, the i.e. power cathode ground connection of the first driving amplifier U1 and the second driving amplifier U2, the positive source of the first driving amplifier U1 is managed Q1 by PMOS and is connected to power supply, and the positive source of the second driving amplifier U2 is managed Q2 by PMOS and is connected to power supply.Manage Q1 by PMOS and control the first driving amplifier U1, PMOS pipe Q2 controls the second driving amplifier U2, is convenient to the conversion of port input and output.
The grid of above-mentioned PMOS pipe Q1 and PMOS pipe Q2 is connected to a controller, by controller, controls PMOS pipe Q1 and PMOS pipe Q2.
[embodiment 3]
as shown in Figure 3, the present embodiment is on the basis of embodiment 2, be provided with a NMOS pipe Q3 between the power cathode of the first driving amplifier U1 and ground connection, be provided with a NMOS pipe Q4 between the power cathode of the second driving amplifier U2 and ground connection, the grid of NMOS pipe Q3 and NMOS pipe Q4 also is connected to controller, the ground connection place arranges a field effect transistor again, namely the power supply of the first driving amplifier U1 can be managed Q1 and NMOSQ3 control by PMOS, when PMOS pipe Q1 and NMOSQ3 damage one, do not affect the use of whole device, the power supply of the second driving amplifier U2 can be managed Q2 and NMOSQ4 control by PMOS simultaneously, Q2, during one of them damage of Q4, do not affect the use of whole device yet.
Claims (4)
1. controlled input and output multiplexing port, it is characterized in that, comprise the first driving amplifier U1 and the second driving amplifier U2, described the first driving amplifier U1 and the second driving amplifier U2 are connected in parallel between port and internal circuit, the input of the first driving amplifier U1 is connected to port, output is connected to internal circuit, and the input of the second driving amplifier U2 connects internal circuit, output connectivity port.
2. controlled input and output multiplexing port according to claim 1, it is characterized in that, be respectively arranged with PMOS pipe Q1 and PMOS pipe Q2 on the power circuit of described the first driving amplifier U1 and the second driving amplifier U2, the i.e. power cathode ground connection of the first driving amplifier U1 and the second driving amplifier U2, the positive source of the first driving amplifier U1 is managed Q1 by PMOS and is connected to power supply, and the positive source of the second driving amplifier U2 is managed Q2 by PMOS and is connected to power supply.
3. controlled input and output multiplexing port according to claim 2, is characterized in that, the grid of described PMOS pipe Q1 and PMOS pipe Q2 is connected to a controller.
4. controlled input and output multiplexing port according to claim 3, it is characterized in that, be provided with a NMOS pipe Q3 between the power cathode of the first driving amplifier U1 and ground connection, be provided with a NMOS pipe Q4 between the power cathode of the second driving amplifier U2 and ground connection, the grid of NMOS pipe Q3 and NMOS pipe Q4 also is connected to controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203380380U CN203289403U (en) | 2013-06-14 | 2013-06-14 | A controllable input-output multiplex port |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203380380U CN203289403U (en) | 2013-06-14 | 2013-06-14 | A controllable input-output multiplex port |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203289403U true CN203289403U (en) | 2013-11-13 |
Family
ID=49545745
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013203380380U Expired - Fee Related CN203289403U (en) | 2013-06-14 | 2013-06-14 | A controllable input-output multiplex port |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203289403U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103281070A (en) * | 2013-06-14 | 2013-09-04 | 成都锐奕信息技术有限公司 | Input and output controllable type IO port |
| CN104318952A (en) * | 2014-09-30 | 2015-01-28 | 山东华芯半导体有限公司 | Circuit and method for reducing number of voltage ports in DRAM |
-
2013
- 2013-06-14 CN CN2013203380380U patent/CN203289403U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103281070A (en) * | 2013-06-14 | 2013-09-04 | 成都锐奕信息技术有限公司 | Input and output controllable type IO port |
| CN104318952A (en) * | 2014-09-30 | 2015-01-28 | 山东华芯半导体有限公司 | Circuit and method for reducing number of voltage ports in DRAM |
| CN104318952B (en) * | 2014-09-30 | 2017-11-10 | 西安紫光国芯半导体有限公司 | A kind of circuit and method for reducing voltage port in DRAM |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131113 Termination date: 20160614 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |