CN103257950A - Double-step initialization chip configuring method capable of achieving dynamic link usability conversion - Google Patents
Double-step initialization chip configuring method capable of achieving dynamic link usability conversion Download PDFInfo
- Publication number
- CN103257950A CN103257950A CN 201310142656 CN201310142656A CN103257950A CN 103257950 A CN103257950 A CN 103257950A CN 201310142656 CN201310142656 CN 201310142656 CN 201310142656 A CN201310142656 A CN 201310142656A CN 103257950 A CN103257950 A CN 103257950A
- Authority
- CN
- China
- Prior art keywords
- link
- initialization
- processor
- chip
- fpga chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 11
- 238000013461 design Methods 0.000 claims abstract description 22
- 238000004891 communication Methods 0.000 claims description 16
- 230000005540 biological transmission Effects 0.000 claims description 8
- 230000001131 transforming effect Effects 0.000 claims 4
- 238000012795 verification Methods 0.000 abstract description 14
- 230000008569 process Effects 0.000 abstract description 5
- 238000011161 development Methods 0.000 abstract description 3
- 238000012360 testing method Methods 0.000 description 7
- 238000012942 design verification Methods 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 101150005660 PHY1 gene Proteins 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Images
Abstract
The invention discloses a double-step initialization chip configuring method capable of achieving dynamic link usability conversion. The double-step initialization chip configuring method capable of achieving the dynamic link usability conversion includes a first step of enabling an initialization processor to be directly connected with a link, a second step of respectively initializing the processor and an FPGA link, a third step of conducting link initialization control logic design, and a fourth step of disconnecting the link with finished initialization. The double-step initialization chip configuring method capable of achieving the dynamic link usability conversion effectively reduces the complexity and shortens the development period of a verification platform hardware design and has high application value and technological value in the process of the design and verification of a high-level server key chip set.
Description
Technical field
The present invention relates to high-end server design field and large scale integrated circuit design technical field, be specifically related to a kind of two step initialization chip configuration methods that realize that the dynamic link availability transforms.
Background technology
Along with the develop rapidly of computer technology and integrated circuit technique, in order to satisfy the needs of socio-economic development, the high-end server system becomes one of bottleneck of restriction social development key area.Message areas such as the pattern analysis of huge data computation and data analysis, complexity and science budget are all very high to the performance requirement of server system.Therefore need to make up huge multipath server system, so that the better application demand that adapts to current each field.But, on the other hand, making up in the technical barrier that huge multipath server system also has been absorbed in interconnect verification between the multipath server system processor and the design of system core chipset verification platform, the complexity height of verification platform hardware design, construction cycle are long.
Therefore, at making up the technical barrier that huge multipath server system exists, be necessary to develop research in fact, to adopt rational verification system structural design, the implementation method that adopts configurable dynamic link availability to transform is with effective realization processor interconnection agreement interface logic and system core chipset FPGA checking.
Summary of the invention
For addressing the above problem, the object of the present invention is to provide a kind of two step initialization chip configuration methods that realize that the dynamic link availability transforms, when guaranteeing that the interconnecting link between processor exists constantly in the multipath server system, realize that the dynamic availability of physical link transforms between processor, significantly reduce the complexity of verification platform hardware design, and guarantee the completeness of fpga chip realization interconnect interface protocol logic and system core chipset logic verification platform.
For achieving the above object, technical scheme of the present invention is:
A kind of two step initialization chip configuration methods that realize that the dynamic link availability transforms comprise the steps:
A, initialization processor direct interconnection link;
B, difference initialization processor and FPGA link;
C, carry out link initialization steering logic design;
The link that D, disconnection initialization are finished.
Further, in steps A, by the system configuration interface, adopt the processor direct connected link to realize the initialization of two-way server interconnecting link, realize system interconnection.
Further, in step B, on the basis that the initialization of processor direct connected link is finished, realize the physical link initialization of multichannel processor and fpga chip logic respectively by the system configuration interface; Wherein, fpga chip is realized two interface logic designs, guarantees the connection communication of two processors.
Further, in step C, finish on the initialized basis of physical link with fpga chip respectively at the multichannel processor, the link initialization steering logic realizes that the multichannel processor is by the connection communication of fpga chip, realize the intraconnection of inner two interface logics of FPGA, realize that with this transmission link of fpga chip realization is to the transparent transmission of multichannel processor system.
Further, in step D, on the basis that the multichannel processor interconnecting link initialization that fpga chip is realized is finished, opening operation by system configuration interface configuration processor direct connected link, with this connection communication of realizing the physical link that the multichannel processor system is only realized by fpga chip, realize the dynamic conversion of physical link.
The present invention realizes two connection communications that go on foot initialization chip configuration methods assurance multipath server system that the dynamic link availability transforms, the dynamic availability that has realized multipath server system processor interconnecting link transforms, be test link by processor direct connected link dynamic conversion, verify the correctness of the interface logic design that fpga chip is realized with this, and provide platform for the design verification of system core chipset, the implementation method of this dynamic-configuration has effectively reduced complexity and the construction cycle of verification platform hardware design, has high using value and technological value in high-end server key chip group design verification process.
Description of drawings
Fig. 1 is method flow diagram of the present invention;
Fig. 2 a-2c is the inventive method layoutprocedure diagram.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the present invention, and be not used in restriction the present invention.
A kind of two step initialization chip configuration methods that realize that the dynamic link availability transforms of the present invention, it mainly considers in the multichannel processor system characteristics of interconnecting link project organization between processor, need guarantee the connection communication between the processor constantly, adopt two step collocation methods to realize the dynamic conversion of processor interconnecting link from direct-connected mode to the FPGA proofing chip.Wherein, on the basis that the initialization of processor direct connected link is finished, take into full account the interface logic design feature that fpga chip is realized, realize the link initialization of the interface logic that multichannel processor and fpga chip are realized respectively, and adopt steering logic to realize the interface logic intraconnection that fpga chip is realized, finish transparent transmission based on physical link between the processor of fpga chip with this.At last, the direct connected link of initially finishing configuration is disconnected, make the test link that connection communication is only realized by fpga chip between processor.This has just guaranteed that the interconnecting link between processor exists constantly in the multipath server system, realized that simultaneously the dynamic availability of physical link transforms between processor, significantly reduced the complexity of verification platform hardware design, and guaranteed that fpga chip realized the completeness of interconnect interface protocol logic and system core chipset logic verification platform.
Please refer to shown in Figure 1ly, the present invention realizes that two step initialization chip configuration methods that the dynamic link availability transforms mainly comprise the steps:
A, initialization processor direct interconnection link;
B, difference initialization processor and FPGA link;
C, carry out link initialization steering logic design;
The link that D, disconnection initialization are finished.
In steps A, by the system configuration interface, adopt the processor direct connected link to realize the initialization of two-way server interconnecting link, realize system interconnection.
In step B, on the basis that the initialization of processor direct connected link is finished, realize the physical link initialization of multichannel processor and fpga chip logic respectively by the system configuration interface; Wherein, fpga chip is realized two interface logic designs, guarantees the connection communication of two processors.
In step C, finish on the initialized basis of physical link with fpga chip respectively at the multichannel processor, the link initialization steering logic realizes that the multichannel processor is by the connection communication of fpga chip, realize the intraconnection of inner two interface logics of FPGA, realize that with this transmission link of fpga chip realization is to the transparent transmission of multichannel processor system.
In step D, on the basis that the multichannel processor interconnecting link initialization that fpga chip is realized is finished, opening operation by system configuration interface configuration processor direct connected link, with this connection communication of realizing the physical link that the multichannel processor system is only realized by fpga chip, realize the dynamic conversion of physical link.
Two step initialization chip configuration methods that dynamic link availability of the present invention transforms guarantee the connection communication of multipath server system, the dynamic availability that has realized multipath server system processor interconnecting link transforms, be test link by processor direct connected link dynamic conversion, verify the correctness of the interface logic design that fpga chip is realized with this, and provide platform for the design verification of system core chipset, the implementation method of this dynamic-configuration has also effectively reduced complexity and the construction cycle of verification platform hardware design, has high using value and technological value in high-end server key chip group design verification process.
Please refer to shown in Fig. 2 a-2c, system powers under the starting condition, by configuration interface configuration link 0, realizes that processor CPU0 and processor CPU1 are by link 0 connection communication, this moment, link 1 was not communicated with, and namely only communicated by letter by link 0 between processor CPU0 and the processor CPU1.
And when link 0 bottom link is finished initialization, by configuration interface configuration processor CPU0 and fpga chip, and processor CPU1 and fpga chip, it is configuration link 1, the fpga chip inner control logic is finished the interconnection of PHY0 and PHY1 simultaneously, thereby realizes that processor CPU0 and processor CPU1 pass through the connection communication of link 1, at this moment, link 0 and link 1 are communicated with simultaneously, namely communicate by letter with link 1 by link 0 simultaneously between processor CPU0 and the processor CPU1.
When link 0 and link 1 are all finished initialization, disconnect by configuration interface configuration processor CPU0 and processor CPU1 link, namely configuration link 0 disconnects, between this moment processor CPU0 and the processor CPU1 only by link 1 communication.So far, system realizes the connection of multilink by dynamic-configuration, availability transforms, and opening operation, layoutprocedure is finished at each interface link initialization procedure of system, and in this process, remain and have the intercommunication link between the processor, be that link 0 leads to or link 1 leads to, perhaps link 0 and link 1 are logical simultaneously, guarantee the stable operation of system with this, namely finally solve link 1 and can not guarantee the shortcoming that link is communicated with constantly between processor, make system finish power-up initializing by the fpga chip link, effectively realized the dynamic switching of system's multilink, play a great role in high-end server system verification and debug phase.
In the checking of high-end server chipset and system initialization link availability test process, consider the characteristics of link design structure, for improving the system architecture testing efficiency, reduce the testing complex degree, adopt two step initialization implementation methods of dynamic link availability conversion, reach the usability testing of many transmission links of high-end server system, realize fpga chip realization key chip group interface logic availability verification simultaneously.
The above only is preferred embodiment of the present invention, not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. the two step initialization chip configuration methods that realize that the dynamic link availability transforms is characterized in that, comprise the steps:
A, initialization processor direct interconnection link;
B, difference initialization processor and FPGA link;
C, carry out link initialization steering logic design;
The link that D, disconnection initialization are finished.
2. two step initialization chip configuration methods of transforming of realization dynamic link availability as claimed in claim 1, it is characterized in that: in steps A, by the system configuration interface, adopt the processor direct connected link to realize the initialization of two-way server interconnecting link, realize system interconnection.
3. two step initialization chip configuration methods of transforming of realization dynamic link availability as claimed in claim 2, it is characterized in that: in step B, on the basis that the initialization of processor direct connected link is finished, realize the physical link initialization of multichannel processor and fpga chip logic respectively by the system configuration interface; Wherein, fpga chip is realized two interface logic designs, guarantees the connection communication of two processors.
4. two step initialization chip configuration methods of transforming of realization dynamic link availability as claimed in claim 3, it is characterized in that: in step C, finish on the initialized basis of physical link with fpga chip respectively at the multichannel processor, the link initialization steering logic realizes that the multichannel processor is by the connection communication of fpga chip, realize the intraconnection of inner two interface logics of FPGA, realize that with this transmission link of fpga chip realization is to the transparent transmission of multichannel processor system.
5. two step initialization chip configuration methods of transforming of realization dynamic link availability as claimed in claim 4, it is characterized in that: in step D, on the basis that the multichannel processor interconnecting link initialization that fpga chip is realized is finished, opening operation by system configuration interface configuration processor direct connected link, with this connection communication of realizing the physical link that the multichannel processor system is only realized by fpga chip, realize the dynamic conversion of physical link.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201310142656 CN103257950A (en) | 2013-04-23 | 2013-04-23 | Double-step initialization chip configuring method capable of achieving dynamic link usability conversion |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201310142656 CN103257950A (en) | 2013-04-23 | 2013-04-23 | Double-step initialization chip configuring method capable of achieving dynamic link usability conversion |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103257950A true CN103257950A (en) | 2013-08-21 |
Family
ID=48961880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201310142656 Pending CN103257950A (en) | 2013-04-23 | 2013-04-23 | Double-step initialization chip configuring method capable of achieving dynamic link usability conversion |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103257950A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016095613A1 (en) * | 2014-12-16 | 2016-06-23 | 华为技术有限公司 | Multi-path server and signal processing method thereof |
-
2013
- 2013-04-23 CN CN 201310142656 patent/CN103257950A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016095613A1 (en) * | 2014-12-16 | 2016-06-23 | 华为技术有限公司 | Multi-path server and signal processing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105279133B (en) | VPX Parallel DSP Signal transacting board analysis based on SoC on-line reorganizations | |
| CN101710314B (en) | High-speed peripheral component interconnection switching controller and realizing method thereof | |
| WO2018040016A1 (en) | Protocol converter and protocol conversion method | |
| CN105450588A (en) | RDMA-based data transmission method and RDMA network cards | |
| CN108845897A (en) | Serial communication adjustment method, device and storage medium | |
| CN103793355A (en) | General signal processing board card based on multi-core DSP (digital signal processor) | |
| CN105051706A (en) | Device, method and system for operation of a low power PHY with a PCIe protocol stack | |
| CN101588285B (en) | Achievement method, non-transparent bridge and communication system for non-transparent transmission | |
| CN105244065B (en) | A kind of nuclear power station DCS control station frameworks based on FPGA technology | |
| US9354990B2 (en) | Coordination of spare lane usage between link partners | |
| CN211628241U (en) | PCIE bus structure switching topology through software | |
| CN201946003U (en) | Double-computer safety switching device | |
| CN102880583B (en) | Device and method for configuring dynamic link of multi-way server | |
| CN105553886A (en) | PCIE switch capable of flexibly extending port number | |
| CN103246623A (en) | Computing device extension system for system on chip (SOC) | |
| CN106027305A (en) | Method for hot standby of dual servers using same IP based on ARM | |
| CN206100049U (en) | Protocol converter | |
| CN103257950A (en) | Double-step initialization chip configuring method capable of achieving dynamic link usability conversion | |
| CN114548028A (en) | Method for low power design, electronic device and storage medium | |
| CN104598420A (en) | SoC chip architecture of 1394 bus | |
| CN110708185B (en) | Data interconnection method, system, chip and device for artificial intelligence processor | |
| CN104937575A (en) | USB controllers coupled to USB ports | |
| CN103150952A (en) | Reconfigurable electronic design automation (EDA) experimental platform | |
| CN203149572U (en) | EDA comprehensive experimental platform based on FPGA chip | |
| CN113626363A (en) | Multi-bus architecture device facing micro-nano satellite-borne computer and control method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130821 |
|
| WD01 | Invention patent application deemed withdrawn after publication |