WO2016095613A1

WO2016095613A1 - Multi-path server and signal processing method thereof

Info

Publication number: WO2016095613A1
Application number: PCT/CN2015/093586
Authority: WO
Inventors: 程龙飞
Original assignee: 华为技术有限公司
Priority date: 2014-12-16
Filing date: 2015-11-02
Publication date: 2016-06-23
Also published as: CN108345562B; CN108345562A; CN104503947A; CN104503947B

Abstract

Disclosed are a multi-path server and a signal processing method thereof. The multi-path server comprises a plurality of CPUs, a plurality of PBI boards and a key signal processing board. Each PBI board monitors at least two CPUs. The output end of each PBI board is connected with the input end of the key signal processing board respectively; the input end of each PBI board is connected with the output end of the key signal processing board respectively. The multi-path server receives key signals transmitted by the various PBI boards by means of the key signal processing board; and then transmits response signals corresponding to the key signals to the corresponding PBI boards synchronously; thus, the response signals received by the CPUs meet the demand of the multi-path server. From the above contents, it can be known that each PBI board is directly connected with the key signal processing board, serial connection by switches is not required, the amount of the switches is reduced, the structure is simple, and reliability is high. Furthermore, the amount of the switches passed by the signals is reduced, and signal quality is improved.

Description

Multi-path server and signal processing method thereof

This application claims priority to Chinese Patent Application No. 201410781480.X, filed on Dec. 16, 2014, entitled "Multiple Servers and Signal Processing Methods", the entire contents of which are incorporated by reference. In this application.

Technical field

The present invention relates to the field of server technologies, and in particular, to a multi-path server and a signal processing method thereof.

Background technique

Multi-path server refers to the number of physical CPUs in the server. The number of physical CPUs in the server determines the number of "multiple" servers in the server. For example, if the server contains 16 physical CPUs, it is a 16-way server. The more the number of physical CPUs in a multi-way server, the higher the ability to process data. Therefore, the 16-channel and 32-way servers become the development trend of multi-way servers.

If a 32-way server is implemented, 32 internal signals must be fully interconnected, and the timing requirements are extremely strict. For example, when the multi-way server is powered on, the time difference between all the CPUs receiving the Powergood signal indicating that the power is normal must be monitored within 10 ns, and the time is recorded as T0; when the CPU is hot plugged, online or offline, the new line is online. The time that the CPU (Intel Ivybridge processor) receives Powergood must be T0+864bclks (or T0+384bclks if Intel Haswell processor is used). Intel only gives the key signals (such as Caterr, PMSYNC, Powergood, TSC, etc.) in the 8-way and below servers, and does not give any recommendation for more than 8 servers.

Assume that the 8-way server is used to implement the key signal processing method of the 16-channel and above servers. The 8-way server uses different switches to switch different basic boards (each base board has multiple CPUs). The number of CPUs on the board is the unit of the smallest hard partition. In series, the number of switches needs to be connected. When the key signals are transmitted, the corresponding switch switch linkage needs to be controlled to achieve the implementation process. The implementation process is extremely complicated and the reliability is poor. After multi-stage switching switches with internal resistance, the signal quality becomes very poor.

Summary of the invention

In the embodiment of the present invention, a multi-path server and a signal processing method thereof are provided to solve the problem that the scheme in the prior art is complicated and the signal quality of the poor reliability set is poor.

In order to solve the above technical problem, the embodiment of the present invention discloses the following technical solutions:

In a first aspect, the present invention provides a multi-way server, including: multiple CPUs, and multiple south bridge management monitors Controller input and output PBI board, and key signal processing board, wherein one PBI board monitors at least two CPUs;

The PBI board is connected to a CPU that is monitored by itself;

An output end of each PBI board is connected to an input end of the key signal processing board, and an input end of each PBI board is connected to an output end of the key signal processing board, and the key signal processing board receives a key signal sent by the PBI board, And returning a response signal corresponding to the key signal to the PBI board;

The PBI board that receives the response signal sends the response signal to the CPU that it monitors.

In conjunction with the first aspect, in a first possible implementation manner of the first aspect, the key signal processing board receives a key signal sent by the PBI board, and returns a corresponding signal to the PBI board Response signals, including:

When the multi-way server is powered on as a server, the key signal processing board receives the first type power-on signal sent by all the PBI boards in the multi-path server, and simultaneously sends the PBI to all the PBIs. The board transmits a second type of power-on signal as a response signal corresponding to the first-type power-on signal, so that all CPUs in the multi-channel server receive the time difference of the second-type power-on signal Preset time requirement;

If all the CPUs in the multi-path server are divided into at least two sub-servers, when any one of the sub-servers is powered on, the key signal processing board receives the third of the PBI boards respectively sent by the sub-servers. After the power-on signal is sent to the power supply, the fourth type power-on signal corresponding to the third-type power-on signal is sent to all the PBI boards in the sub-server, so that the sub-server is in the sub-server. The time difference that all CPUs receive the power-on signal of the fourth type of power source meets a preset time requirement;

The first type of power-on signal and the third type of power-on signal are generated when the PBI board detects that the power of each CPU that is monitored by itself is powered on.

In conjunction with the first aspect, in a second possible implementation of the first aspect, the critical signal processing board receives a key signal transmitted by the PBI board and returns a corresponding signal to the PBI board Response signals, including:

When a new CPU is inserted in the multi-path server, the key signal processing board receives the fifth-type power-on signal sent by the PBI board corresponding to the new CPU, and then goes to the new one at a preset time. a PBI board corresponding to the CPU transmits a sixth type power-on signal as a response signal corresponding to the fifth-type power-on signal, so that the new CPU receives the sixth-type power-on signal Time meets the preset time requirement;

The fifth type of power-on signal is generated when the PBI board detects that the new CPU is powered on.

In conjunction with the first aspect, in a third possible implementation of the first aspect, the key signal processing board receives a key signal sent by the PBI board and returns a corresponding signal to the PBI board Response signals, including:

If the multi-path server is used as a server, the key signal processing board receives the first system error signal sent by any one of the PBI boards, and sends the system error signal PBI to the multi-path server respectively. The other respective PBI boards transmit a second system error signal as a response signal corresponding to the first system error signal;

If the multi-way server is divided into at least two sub-servers, and the key signal processing board receives the third system error signal sent by any one of the PBI boards, determining and transmitting the third system according to the obtained sub-server information The PBI boards of the error signals belong to other PBI boards of the same sub-server; respectively, to each of the PBI boards except the PBI board that transmits the third system error signal, as the third system error The fourth system error signal of the response signal corresponding to the signal.

In conjunction with the third possible implementation of the first aspect, in a fourth possible implementation manner of the first aspect, the key signal processing board receives a key signal sent by the PBI board, and returns to the PBI board The response signal corresponding to the key signal further includes:

The key signal processing board receives the next first system error signal or the third system error signal when it is detected that the first system error signal or the third system error transmitted by the current PBI board changes from the active state to the inactive state.

In a second aspect, the present invention provides a signal processing method for a multi-way server, which is applied to a multi-path server, which includes a plurality of CPUs, a plurality of south bridge substrate management monitor input and output PBI boards, and key signals. a processing board, wherein one PBI board monitors at least two CPUs; the method includes:

The key signal processing board receives a key signal sent by the PBI board;

The key signal processing board returns a response signal corresponding to the key signal to the PBI board according to the received key signal, so that the PBI board that receives the response signal sends the response signal The CPU that is monitored by the PBI board.

With reference to the second aspect, in a first possible implementation manner of the second aspect, the key signal processing board returns a response signal corresponding to the key signal to the PBI board according to the received key signal, including:

When the multi-way server is powered on as a server, the key signal processing board receives the first type power-on signal sent by all the PBI boards in the multi-way server, and simultaneously sends the power signals to all the PBI boards. a second type of power-on signal as a response signal corresponding to the power-on signal of the first type of power source, so that all CPUs in the multi-way server receive the time difference of the second-type power-on signal to meet the preset time requirement;

If all the CPUs in the multi-path server are divided into at least two sub-servers, when any one of the sub-servers is powered on, the key signal processing board receives the third of the PBI boards respectively sent by the sub-servers. After the power-on signal of the power-like type, a fourth type power-on signal as a response signal corresponding to the power-on signal of the third-type power source is simultaneously sent to all PBI boards in the sub-server, so that the sub-power All CPUs in the server Receiving the time difference of the fourth type power supply power-on signal to meet a preset time requirement;

With reference to the second aspect, in a second possible implementation manner of the second aspect, the key signal processing board returns a response signal corresponding to the key signal to the PBI board according to the received key signal, including:

In conjunction with the second possible implementation of the second aspect, in a third possible implementation of the second aspect, the key signal processing board returns the key signal to the PBI board according to the received critical signal Corresponding response signals include:

If the multi-path server is used as a server, the key signal processing board receives the first system error signal sent by any one of the PBI boards, and simultaneously sends the system error signal PBI to the multi-path server. The other respective PBI boards transmit a second system error signal as a response signal corresponding to the first system error signal;

If the multiplex server is divided into at least two sub-servers, the key signal processing board acquires sub-server information of the multiplex server, and when receiving a third system error signal sent by any one of the PBI boards, according to the sub-server The server information determines that each PBI board belonging to the same sub-server as the PBI board that transmits the third system error signal; and each PBI other than the PBI board that transmits the third system error signal to the sub-server The board transmits a fourth system error signal as a response signal corresponding to the third system error signal.

In conjunction with the third possible implementation of the second aspect, in a fourth possible implementation of the second aspect, the method further includes:

The multiplex server provided by the embodiment of the present invention includes: multiple CPUs, multiple PBI (PCH BMC IO, South Bridge Management Monitor Input and Output) boards, and a key signal processing board, wherein the BMC is Baseboard Management Controller, Baseboard Management Monitor. Each PBI board monitors at least two CPUs, and each PBI board is connected to the CPU it monitors. The output ends of the respective PBI boards are respectively connected to the input ends of the key signal processing boards, and the input ends of the respective PBI boards are respectively connected to the output ends of the key signal processing boards. It can be seen that each CPU is connected to a corresponding PBI board, and the PBI board is directly connected to the key signal processing board. The multi-way server receives the key signals sent by the respective PBI boards through the key signal processing boards, and then simultaneously sends corresponding response signals to the corresponding PBI boards. Each PBI board is directly connected to the key signal processing board, and does not require a switch to be connected in series, reducing the number of switchers, and having a simple structure and high reliability. Moreover, the number of switching switches through which the signal passes is reduced, and the signal quality is improved.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it will be apparent to those skilled in the art that In other words, other drawings can be obtained based on these drawings without paying for creative labor.

1 is a schematic structural diagram of a multi-path server according to an embodiment of the present invention;

2 is a schematic structural diagram of a PBI board according to an embodiment of the present invention;

FIG. 3 is a flowchart of a signal processing method of a multi-path server according to an embodiment of the present invention.

detailed description

In order to make those skilled in the art better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. The embodiments are only a part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of the present invention.

Referring to FIG. 1, a schematic structural diagram of a multi-path server according to an embodiment of the present invention is shown. This embodiment uses a 32-way server as an example for description. Of course, in other embodiments of the present invention, the multi-path server may be a 16-way, 8-way, 4-way server, and the number of PBI boards may be flexibly determined according to actual needs.

As shown in FIG. 1, the multi-way server includes: 32 CPUs, at least 8 PBI boards, and 1 key signal processing board.

In this embodiment, four CPUs are monitored by one PBI board as an example. For example, PBI1 monitors CPU1~CPU4, PBI2 monitors CPU5~CPU8, PBI3 monitors CPU9~CPU12, PBI4 monitors CPU13~CPU16, and so on, PBI8 monitors CPU29~ CPU32.

Each of the PBI boards is connected to a plurality of CPUs that are monitored by itself, CPUs 1 to 4 are connected to PBI 1, CPUs 5 to 8 are connected to PBI 2, and so on, and CPUs 29 to 32 are connected to PBI 8.

Due to the limited number of I/O interfaces on the PBI board, the PBI board connects to some of the CPUs that it monitors through its own I/O interface, and another part of the CPU that it monitors is connected to the PBI board through the backplane.

Of course, in other embodiments of the invention, one PBI board can monitor 2 or 8 CPUs. If one PBI board monitors two CPUs, the 32-way server needs to be configured with 16 PBI boards; if one PBI board monitors eight CPUs, the 32-way servers need to be configured with four PBI boards.

Each PBI board includes an input end and an output end. The input ends of the respective PBI boards are respectively connected to the output ends of the key signal processing boards 100, and the output ends of the respective PBI boards are respectively connected to the input ends of the key signal processing boards 100.

After receiving the key signal sent by the CPU or monitoring the state of the CPU and generating the corresponding key signal, the PBI board directly sends the key signal to the key signal processing board 100, and the key signal processing board 100 sends the corresponding signal to the corresponding PBI board. The response signal corresponding to the key signal. The PBI board that receives the response signal sends the response signal to the corresponding CPU, thereby ensuring that each CPU receives the response signal to meet the requirement.

The key signals include, but are not limited to, a Powergood signal, a Caterr signal, a PMSYNC signal, a TSC (Time Stamp Counte) signal, an S4 signal, a Thermtrip signal, a Powerbutton signal, an MSMI signal, and the like.

The response signals corresponding to different key signals are also different, and the functions of different response signals are also different. In general, the critical signals between the CPUs in the multi-way server satisfy the requirements of the multi-way server by responding to the signal. For example, the response signal of the Powergood signal is still the Powergood signal, and the CPU starts after receiving the Powergood signal.

In the multi-way server, the CPU is notified by the Powergood signal that the external power supplies have been powered on. Multi-channel servers have very strict timing requirements for Powergood signals. For example, when multiple servers are powered on, the time difference of Powergood signals received by all CPUs must be monitored within 10 ns, which can maximize the system performance of 32-way servers. The time at which the Powergood signal is transmitted to each CPU is recorded as the initial time T0.

For example, when the multi-way server is powered on as a server, the PBI board detects that the CPU monitored by itself is powered on, and sends the first Powergood signal to the critical signal processing board (ie, the first type of power-on signal). After the key signal processing board receives the first type of Powergood signals sent by all the PBI boards in the server, the second Powergood signal (ie, the second type power-on signal) is returned to all PBI boards in the multi-way server. After receiving the second Powergood signal sent by the key signal processing board, the PBI board sends it to the CPU of its own monitoring. In this way, the second Powergood signal is uniformly sent to each PBI board by the key signal processing board, and then sent by each PBI board to the CPU of its own monitoring, thereby ensuring that each CPU in the multi-path server receives the second Powergood signal. The time difference is within a preset time (for example, 10 ns).

When the CPU implements hot plugging, online (online) or offline (offline), the time that the new online CPU receives the Powergood signal must be the preset time. The preset time is T0 plus the preset period, where different The CPUs produced by the manufacturer, or different types of CPUs produced by the same manufacturer, may have different preset periods. For example, the preset period set by the Ivybridge processor can be N*864BCLKs; the preset period set by the Haswell processor can be N*384BCLKs. Where N is a positive integer and 1BCLK is 10 ns.

The Caterr signal indicates that the system has experienced a serious error.

The PMSYNC (Power Management Sync) signal is an energy saving control signal.

The S4 signal is a status signal of the multi-way server system. The signal is sent by the South Bridge (PCH). When the CPLD (Complex Programmable Logic Device) on the board where the CPU is located detects the PCH and sends the S4. Control the powering of the entire multi-way server system.

The Thermtrip signal is a signal that is sent when the CPU overheats.

The Powerbutton signal is a signal generated when the power-on button on the server is triggered. This signal is used to notify the PCH that there is a button triggering action. It needs to be powered on or powered off.

The MSMI signal is exactly the same as the Caterr signal and is a signal added by the latest Intel platform.

The multi-path server provided by the embodiment of the present invention includes a plurality of CPUs, a plurality of PBI boards, and a key signal processing board. Each PBI board monitors at least two CPUs, and each PBI board is connected to the CPU it monitors. The output ends of the respective PBI boards are respectively connected to the input ends of the key signal processing boards, and the input ends of the respective PBI boards are respectively connected to the output ends of the key signal processing boards. After receiving the key signal sent by the PBI board, the key signal processing board returns a response signal corresponding to the key signal to the corresponding PBI board. The PBI board that receives the response signal sends the response signal to the CPU that is monitored by itself, so that the response signal received by the CPU satisfies the requirements of the multi-path server. It can be seen from the above that the multi-channel server receives the key signals sent by the PBI boards through the key signal processing boards, and then sends corresponding response signals to the corresponding PBI boards, so that each CPU receives the response signal to meet the requirements of the multi-path server. . Moreover, each PBI board is directly connected to the key signal processing board, and does not require a switch to be connected in series, reducing the number of switchers, and having a simple structure and high reliability. Moreover, the number of switching switches through which the signal passes is reduced, and the signal quality is improved.

In addition, in the embodiment of the present invention, the PBI boards are not connected in series through the conversion switch, and any plurality of PBI combinations can be realized to form one hard partition, that is, the hard partition is flexibly configured. For example, the CPU corresponding to PBI1 and PBI3 is configured as a hard partition, that is, configured as an 8-way server; PBI2 and PBI5 are configured as one hard partition, that is, configured as an 8-way server. In the prior art, the multi-path server, because the PBI boards are connected in series through the switch, therefore, the adjacent PBI can only be configured as a hard partition when configuring the hard partition, and the hard partition cannot be flexibly configured.

FIG. 2 is a schematic diagram showing the internal structure of a PBI board according to an embodiment of the present invention, as shown in FIG. 2, each PBI The boards each include: a changeover switch 200, a level shifting chip 210, a first CPLD 220, and a south bridge chip 230. The number of the changeover switches 200 is the same as the number of CPUs monitored by the PBI board. In this embodiment, four switchers are disposed in each PBI board.

The I/O interface of each CPU is connected to the first I/O interface of the level conversion chip 210 through the changeover switch 200, and the second I/O interface of the level conversion chip 210 is connected to the first I/O interface of the first CPLD 220.

The first input of the first CPLD 220 is connected to the output of the key signal processing board 100 as an input of the PBI board. The first output of the first CPLD 220 is connected to the input of the critical signal processing board 100 as an output of the PBI board. The second output of the first CPLD 220 is connected to the south bridge chip 230.

The signal output by the CPU is supplied to the level conversion chip 210 to be converted into a high level signal that the CPLD can process, and is converted to a high level signal to be more suitable for long distance transmission.

The level conversion chip 210 transmits the converted signal to the first CPLD 220. The first CPLD 220 transmits the received signal to the key signal processing board 100.

The key signal processing board 100 returns a response signal corresponding to the received key signal to the first CPLD 220 in the corresponding PBI. Then, the corresponding changeover switch 200 is controlled by the first CPLD 220 to be closed, and the signal sent by the first CPLD 220 to the key signal processing board 100 is sent to the corresponding CPU.

The key signal processing process of the multi-path server provided by the embodiment of the present invention is described in the following with reference to FIG. 1 and FIG.

(1) When the 32-way server is powered on as a server, the transmission process of Powergood signals:

11) SMM (System Management Module) board notifies the key signal processing board that the multi-path server is a 32-way server. The SMM board is used to obtain partition information of the multi-path server system.

12) Each PBI board and each CPU it monitors are powered on separately; after each PBI board detects that the power of each CPU monitored by itself is powered on, the first Powergood signal is generated and sent to the key signal processing board, indicating that the PBI board is displayed. The CPU it monitors has been powered on.

In one embodiment, each PBI board can generate a first Powergood signal that is generated when power to all of the CPUs that it controls is detected to be powered up.

The power supply of each PBI board does not need to be powered on synchronously, and the key signal processing board avoids the unstable state caused by the power process of each PBI board by delay or debounce processing, so that the reliability of the system is higher. The delay means that the key signal processing board does not process the key signal after receiving the key signal, and the key signal such as the delay preset time period is completely stable before processing. The preset duration can be set according to the power-on stabilization time. Of course, it can also be set according to actual needs.

It should be noted that after each PBI board sends the first Powergood signal to the key signal processing board, The PBI board does nothing until it receives the second Powergood signal sent by the critical signal processing board.

13) After receiving the first Powergood signal sent by all the PBI boards, the key signal processing board sends the second Powergood signal to all PBI boards at the same time, and records the time at which the second Powergood signal is transmitted as the initial time T0.

In addition, since the signals transmitted between different boards are discrete, and the transmission lines of the signals have different delays, the lengths of the transmission lines between the key signal processing boards and the PBI boards are required to be equal, so that each PBI board can be guaranteed. The timing of receiving the second Powergood signal is consistent, thereby satisfying the timing requirement of the system for each CPU to receive the second Powergood signal.

It should be noted that when the CPU is hot swapped, the current BIOS (Basic Input Output System) can only achieve two CPUs simultaneously online (online) or offline (offline), so in multiple channels. In the server, you need to divide the two CPUs into one group. For example, there are 16 groups of 32-way servers.

In order to enable the multi-way server to be powered on and off with the CPU, the processing of the Powergood signal is compatible. When the multi-way server is powered on, each two CPUs are divided into one group. Each PBI board generates a first Powergood signal for each group of CPUs and sends them to the key signal processing boards. The key signal processing board needs to return a second Powergood signal to the PBI board for each group of CPUs, ensuring that the number of second Powergood signals is the same as the number of first Powergood signals. For example, each PBI board monitors 4 CPUs, and two CPUs are a group, and each PBI board generates two first Powergood signals. Moreover, the critical signal processing board needs to return two second Powergood signals to each PBI board simultaneously.

14) The first CPLD in the PBI board sends the second Powergood signal sent by the key signal processing board to each CPU monitored by itself.

The key signal processing board can simultaneously send the second Powergood signal to each PBI board, and then the second Powergood signal is sent to the corresponding CPU by each PBI board, thereby ensuring that each CPU receives the second Powergood signal. The timing requirements are met (ie, the time difference between each CPU receiving the second Powergood signal is within 10 ns).

(2) When the 32-way server is divided into multiple sub-servers, the process of powering up the sub-server is similar to the above process. Among them, one sub-server is a hard partition, and each sub-server can work alone. For example, a 32-way server can be divided into four 8-way sub-servers, or can be divided into one 16-way sub-server and two 8-way sub-servers.

The power-on process of the sub-server is as follows:

21) The SMM board notifies the critical signal processing board of the hard partition information of the multi-way server. The hard partition information may include information that the multi-way server contains several hard partitions, and which CPUs each hard partition contains.

22) Each hard partitioned PBI board and its monitored CPUs are respectively powered on; the PBI board detects that each of the CPUs monitored by the CPU is powered on, and generates a first Powergood signal (ie, a third type of power-on signal) And sent to the key signal processing board, indicating that the PBI board and its monitored CPU have been powered on.

23) After receiving the first Powergood signal sent by the PBI board in the hard partition, the critical signal processing board determines the hard partition where the PBI board is located.

Determining, according to hard partition information from the SMM board, information of a hard partition where the PBI board that sends the first Powergood signal is located, for example, determining which hard partition the PBI board that sends the first Powergood signal is located, and the hard partition includes Which PBI boards and other information.

24) After receiving the first Powergood signal sent by all PBI boards in the hard partition, the key signal processing board sends a second Powergood signal to each PBI board in the hard partition at the same time (ie, the fourth type power supply) The power-on signal is recorded, and the time at which the second Powergood signal is transmitted is recorded as the initial time T0.

25) The first CPLD in the PBI board sends the second Powergood signal sent by the key signal processing board to each CPU monitored by itself.

Through the above process, it can be realized that the time when each CPU in the hard partition receives the second Powergood signal satisfies the timing requirement. Moreover, each hard partition is separately powered and separately controlled, and there is no coupling relationship between them.

(3) When the CPU is online/offline, the transmission process of Powergood signal

When the CPU is online/offline, the transmission process of the 32-way server as a server or Powergood signal divided into multiple sub-servers is the same. The specific process is as follows:

31) The CPU that requires online is plugged into the multi-way server system.

32) After the PBI board detects that the CPU of the new online is powered on, it generates a first Powergood signal (ie, the fifth type of power-on signal) and sends the first Powergood signal to the key signal processing board.

33) After receiving the first Powergood signal sent by the PBI board, the key signal processing board sends a second Powergood signal (ie, a sixth type power supply power-on signal) to the PBI board at a preset time.

The preset time is the initial time T0 plus a preset period. Among them, the CPUs produced by different manufacturers, or different types of CPUs produced by the same manufacturer, may have different preset periods. For example, the preset period of the Ivybridge processor is N*864BCLKs, corresponding to the corresponding Ivybridge processor. The preset time is T0+N*864BCLKs; the preset around the Haswell processor is N*384BCLKs, and the corresponding preset time of the corresponding Haswell processor is T0+N*384BCLKs, where N is a positive integer.

34) transmitting, by the PBI board, the received second Powergood signal to the corresponding CPU.

When the CPU online is implemented through the above process, the second Powergood signal received by the online CPU meets the preset time requirement.

The following describes the working process of the multi-path server provided by the embodiment of the present invention by taking a system error signal (ie, a Caterr signal) as an example.

(4) If the 32-way server is used as a server, the transmission process of the Caterr signal is as follows:

41) When the PBI board receives the first Caterr signal sent by the CPU (ie, the first system error signal), the PBI board transmits the first Caterr signal to the key signal processing board.

42) After receiving the first Caterr signal from the key signal processing board, transmitting a second Caterr signal (ie, a second system error signal) to each of the PBI boards except the PBI board that transmits the first Caterr signal.

After receiving the first Caterr signal, the key signal processing board determines whether to respond to the first Caterr signal according to the flag bit corresponding to the Caterr signal. For example, when the flag corresponding to the Caterr signal is "0", the key signal processing board no longer responds to the Caterr signal sent by other CPUs; when the flag corresponding to the Caterr signal is "1", the key signal processing board can Respond to Caterr signals from other CPUs.

When the key signal processing board receives the first Caterr signal, it changes the flag corresponding to the Caterr signal to a binary number "0". If the first Caterr signal changes from low to high, it indicates that the fault is eliminated. At this time, the flag corresponding to the Caterr signal is modified to a binary number "1".

The key signal processing board responds to the Caterr signal sent by the CPU. After the key signal processing board receives the Caterr signal sent by the CPU, it forwards the Caterr signal to other CPUs that are in the same hard partition as the CPU, that is, the same as the CPU. The Caterr signal lines of other CPUs in the partition are pulled low by the high level to shield the Caterr signals sent by other CPUs. If the CPU that issued the Caterr signal can fix the error by itself, the Caterr signal will disappear and the system will return to normal. If the CPU cannot repair itself, the system will hang.

43) Each PBI board sends the received second Caterr signal to the corresponding CPU.

(5) If the 32-way server is divided into multiple sub-servers, each sub-server is a hard partition. The transmission process of the Caterr signal is as follows:

51) The SMM board notifies the hard partition information of the multi-path server of the key signal processing board.

52) When the PBI board receives the third Caterr signal (ie, the third system error signal) sent by the CPU, the PBI board transmits the third Caterr signal to the key signal processing board.

53) After receiving the third Caterr signal, the key signal processing board determines a hard partition corresponding to the PBI board according to the hard partition information.

That is, the key signal processing board determines the broadcast range of the response signal corresponding to the third Caterr signal, in other words, determines which PBI boards to send the response signal corresponding to the third Caterr signal.

54) The key signal processing board transmits a fourth Caterr signal (ie, a fourth system error signal) to the other PBI boards in the hard partition where the PBI board is located.

55) After receiving the fourth Caterr signal, the other PBI boards in the hard partition are sent to the CPU of their own monitoring.

With the multi-path server provided by the embodiment, after receiving the Caterr signal sent by the CPU, the key signal processing board can be sent to the corresponding CPU through the PBI, because the PBI boards are not connected in series through the switch, but directly deal with the key signals. The board is connected so that the control process is simple and the broadcast time of the Caterr signal is greatly reduced. In addition, the number of switches through which the signal passes is reduced, and the signal quality can be improved.

Corresponding to the multi-way server described above, the present invention also provides an embodiment of a signal synchronization method for a multi-way server.

3 is a schematic flowchart of a signal processing method of a multi-path server according to an embodiment of the present invention. The method is applied to a key signal processing board of a multi-path server. The multi-way server includes a plurality of CPUs, a plurality of PBI boards, and a key signal processing board, wherein one PBI board monitors at least two CPUs; each PBI board is connected to a plurality of CPUs monitored by itself; each PBI board includes an input At the end and the output end, the input ends of the respective PBI boards are respectively connected to the output ends of the key signal processing boards, and the output ends of the respective PBI boards are respectively connected to the input ends of the key signal processing boards.

As shown in FIG. 3, the method may include the following steps:

S110, the key signal processing board receives the key signal sent by the PBI board.

The key signal is sent by the CPU monitored by the PBI board to the PBI board, or is generated by the PBI board detecting the corresponding state of the CPU, for example, when the PBI board detects the power of each CPU that it monitors. After the power is completed, the first Powergood signal is generated; for example, when the CPU fails, the first Caterr signal is generated, and the first Caterr signal is sent to the PBI board, and sent by the PBI board to the key signal processing board.

The key signals include, but are not limited to, Powergood signals, Caterr signals, PMSYNC signals, TSC signals. No., S4 signal, Thermtrip signal, Powerbutton signal, MSMI signal.

The processing of the Powergood signal and the Caterr signal is as described in the above process, and will not be described here.

S120. The key signal processing board returns a response signal corresponding to the key signal to the PBI board according to the received key signal, so that the PBI board that receives the response signal sends the response signal to the PBI. Board monitors the CPU.

As can be seen from the above embodiments, the multi-way server can include 32 CPUs, 8 PBI boards, and a key signal processing board. Each PBI board monitors a plurality of CPUs; an output end of each PBI board is connected to an input end of the key signal processing board, an input end of each PBI board is connected to an output end of the key signal processing board; and a key signal processing board receives a PBI The key signal sent by the board generates a response signal corresponding to the key signal and returns the response signal to the corresponding PBI board. The PBI board that receives the response signal distributes the response signal to the corresponding CPU. It can be seen from the above that each PBI board is directly connected to the key signal processing board, does not need to switch the switch to be connected in series, reduces the number of switching switches, has a simple structure and high reliability, and reduces the switching quality of the signal passing through the switching switch.

If the key signal is a power-on signal (Powergood signal) when the multi-server is powered on, step S120 may include the following two situations:

First, the multi-way server is powered on as a server.

Receiving, by the key signal processing board, the first type of power-on signal sent by all the PBI boards in the multi-path server, and simultaneously transmitting to the entire PBI board as corresponding to the power-on signal of the first type of power source. And responding to the second type of power-on signal of the signal, so that all the CPUs in the multi-way server receive the time difference of the second-type power-on signal to meet the preset time requirement.

The first type of power-on signal is generated when the PBI board detects that the power of each CPU that is monitored by itself is powered on.

Second, the multi-way server is divided into at least two sub-servers, and the process of powering any one of the sub-servers is as follows:

After receiving the third type power-on signal sent by all the PBI boards in the sub-server, the key signal processing board simultaneously sends the third-type power-on signal to the PBI board in the sub-server as the third The fourth type of power-on signal corresponding to the response signal of the power-type power-on signal, so that all the CPUs in the sub-server receive the time difference of the power-on signal of the fourth-type power source to meet the preset time requirement.

The third type power-on power-on signal is generated when the PBI board detects that the power of each CPU that is monitored by itself is powered on.

If the key signal is the power-on signal (ie, Powergood signal) when the CPU is online/offline, the steps are S120 can include the following process:

When a new CPU is inserted in the multi-path server, the key signal processing board receives the fifth-type power-on signal sent by the PBI board corresponding to the new CPU, and sends the new signal to the new one at a preset time. The PBI board corresponding to the CPU transmits a sixth type power-on signal as a response signal corresponding to the fifth type power-on signal, so that the new CPU receives the sixth-type power-on signal The time meets the preset time requirement.

If the key signal is a system error signal (ie, a Caterr signal), step S120 may include the following two cases:

First, if the multi-way server is used as a server

After receiving the first system error signal sent by any one of the PBI boards, the key signal processing board simultaneously sends a second system error signal to each of the PBI boards except the system error signal PBI. The second system error signal is the response signal corresponding to the first system error signal

Second, the multi-way server is divided into at least two sub-servers.

The key signal processing board acquires the sub-server information of the multi-path server, and when receiving the third system error signal sent by any one of the PBI boards, determining, according to the sub-server information, the PBI board that sends the third system error signal Other PBI boards belonging to the same sub-server; simultaneously transmitting a fourth system error signal to each of the PBI boards except the PBI board transmitting the third system error signal; the fourth system error signal Is the response signal corresponding to the third system error signal.

Optionally, when the key signal is a Caterr signal, the method further includes:

Wherein, whether the state of the system error signal is valid can be obtained by detecting a flag bit corresponding to the system error signal. In a specific embodiment, if the flag bit corresponding to the system error signal is a binary number “0”, indicating a system error. The signal is valid; if the flag corresponding to the system error signal is binary number "1", it indicates that the system error is invalid. Of course, when the flag bit is "1", it indicates that the system error signal is valid; when the flag bit is "0", it indicates that the system error signal is invalid.

Through the description of the above method embodiments, those skilled in the art can clearly understand that the present invention can be implemented by means of software plus a necessary general hardware platform, and of course, can also be through hardware, but in many cases, the former is better. Implementation. Based on such understanding, the technical solution of the present invention, which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a storage medium, including a plurality of instructions for causing a A computer device (which may be a personal computer, server, or network device, etc.) performs all or part of the steps of the methods described in various embodiments of the present invention. And The foregoing storage medium includes various media that can store program codes, such as a read only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

The various embodiments in the specification are described in a progressive manner, and the same or similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for a device or system embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and the relevant portions can be referred to the description of the method embodiment. The apparatus and system embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, ie It can be located in one place or it can be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment. Those of ordinary skill in the art can understand and implement without any creative effort.

The invention may be described in the general context of computer-executable instructions executed by a computer, such as a program module. Generally, program modules include routines, programs, objects, components, data structures, and the like that perform particular tasks or implement particular abstract data types. The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are connected through a communication network. In a distributed computing environment, program modules can be located in both local and remote computer storage media including storage devices.

It should be noted that, in this context, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these There is any such actual relationship or order between entities or operations. Furthermore, the term "comprises" or "comprises" or "comprises" or any other variations thereof is intended to encompass a non-exclusive inclusion, such that a process, method, article, or device that comprises a plurality of elements includes not only those elements but also Other elements, or elements that are inherent to such a process, method, item, or device. An element that is defined by the phrase "comprising a ..." does not exclude the presence of additional equivalent elements in the process, method, item, or device that comprises the element.

The above is only a specific embodiment of the present invention, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present invention. It should be considered as the scope of protection of the present invention.

Claims

A multi-way server, comprising: a plurality of CPUs, a plurality of south bridge substrate management monitor input and output PBI boards, and a key signal processing board, wherein one PBI board monitors at least two CPUs;

The PBI board is connected to a CPU that is monitored by itself;

An output end of each PBI board is connected to an input end of the key signal processing board, and an input end of each PBI board is connected to an output end of the key signal processing board, and the key signal processing board receives a key signal sent by the PBI board, And returning a response signal corresponding to the key signal to the PBI board;

The PBI board that receives the response signal sends the response signal to the CPU that it monitors.
The multiplex server according to claim 1, wherein said key signal processing board receives a key signal transmitted by said PBI board and returns a response signal corresponding to said key signal to said PBI board, including :

When the multi-way server is powered on as a server, the key signal processing board receives the first type power-on signal sent by all the PBI boards in the multi-path server, and simultaneously sends the PBI to all the PBIs. The board transmits a second type of power-on signal as a response signal corresponding to the first-type power-on signal, so that all CPUs in the multi-channel server receive the time difference of the second-type power-on signal Preset time requirement;

If all the CPUs in the multi-path server are divided into at least two sub-servers, when any one of the sub-servers is powered on, the key signal processing board receives the third of the PBI boards respectively sent by the sub-servers. After the power-on signal is sent to the power supply, the fourth type power-on signal corresponding to the third-type power-on signal is sent to all the PBI boards in the sub-server, so that the sub-server is in the sub-server. The time difference that all CPUs receive the power-on signal of the fourth type of power source meets a preset time requirement;

The first type of power-on signal and the third type of power-on signal are generated when the PBI board detects that the power of each CPU that is monitored by itself is powered on.
The multiplex server according to claim 1, wherein said key signal processing board receives a key signal transmitted by said PBI board and returns a response signal corresponding to said key signal to said PBI board, including :

When a new CPU is inserted in the multi-path server, the key signal processing board receives the fifth-type power-on signal sent by the PBI board corresponding to the new CPU, and then goes to the new one at a preset time. a PBI board corresponding to the CPU transmits a sixth type power-on signal as a response signal corresponding to the fifth-type power-on signal, so that the new CPU receives the sixth-type power-on signal Time meets the preset time requirement;

The fifth type of power-on signal is generated when the PBI board detects that the new CPU is powered on.
The multiplex server according to claim 1, wherein said key signal processing board receives Deriving a key signal transmitted by the PBI board and returning a response signal corresponding to the key signal to the PBI board, including:

If the multi-path server is used as a server, the key signal processing board receives the first system error signal sent by any one of the PBI boards, and sends the system error signal PBI to the multi-path server respectively. The other respective PBI boards transmit a second system error signal as a response signal corresponding to the first system error signal;

If the multi-way server is divided into at least two sub-servers, and the key signal processing board receives the third system error signal sent by any one of the PBI boards, determining and transmitting the third system according to the obtained sub-server information The PBI boards of the error signals belong to other PBI boards of the same sub-server; respectively, to each of the PBI boards except the PBI board that transmits the third system error signal, as the third system error The fourth system error signal of the response signal corresponding to the signal.
The multiplex server according to claim 4, wherein said key signal processing board receives a key signal transmitted by said PBI board, and returns a response signal corresponding to said key signal to said PBI board, include:

The key signal processing board receives the next first system error signal or the third system error signal when it is detected that the first system error signal or the third system error transmitted by the current PBI board changes from the active state to the inactive state.
A signal processing method for a multi-path server, which is characterized in that it is applied to a multi-path server, which includes a plurality of CPUs, a plurality of south bridge substrate management monitor input and output PBI boards, and a key signal processing board. Wherein, one PBI board monitors at least two CPUs; the method includes:

The key signal processing board receives a key signal sent by the PBI board;

The key signal processing board returns a response signal corresponding to the key signal to the PBI board according to the received key signal, so that the PBI board that receives the response signal sends the response signal The CPU that is monitored by the PBI board.
The method according to claim 6, wherein the key signal processing board returns a response signal corresponding to the key signal to the PBI board according to the received key signal, including:

When the multi-way server is powered on as a server, the key signal processing board receives the first type power-on signal sent by all the PBI boards in the multi-way server, and simultaneously sends the power signals to all the PBI boards. a second type of power-on signal as a response signal corresponding to the power-on signal of the first type of power source, so that all CPUs in the multi-way server receive the time difference of the second-type power-on signal to meet the preset time requirement;

If all the CPUs in the multi-path server are divided into at least two sub-servers, when any one of the sub-servers is powered on, the key signal processing board receives the third of the PBI boards respectively sent by the sub-servers. After the power-on signal of the power-like type, a fourth type power-on signal as a response signal corresponding to the power-on signal of the third-type power source is simultaneously sent to all PBI boards in the sub-server, so that the sub-power The time difference between all the CPUs in the server receiving the power-on signal of the fourth type of power meets the preset time requirement;

The first type of power-on signal and the third type of power-on signal are generated when the PBI board detects that the power of each CPU that is monitored by itself is powered on.
The method according to claim 6, wherein the key signal processing board returns a response signal corresponding to the key signal to the PBI board according to the received key signal, including:

When a new CPU is inserted in the multi-path server, the key signal processing board receives the fifth-type power-on signal sent by the PBI board corresponding to the new CPU, and then goes to the new one at a preset time. a PBI board corresponding to the CPU transmits a sixth type power-on signal as a response signal corresponding to the fifth-type power-on signal, so that the new CPU receives the sixth-type power-on signal Time meets the preset time requirement;

The fifth type of power-on signal is generated when the PBI board detects that the new CPU is powered on.
The method according to claim 8, wherein the key signal processing board returns a response signal corresponding to the key signal to the PBI board according to the received key signal, including:

If the multi-path server is used as a server, the key signal processing board receives the first system error signal sent by any one of the PBI boards, and simultaneously sends the system error signal PBI to the multi-path server. The other respective PBI boards transmit a second system error signal as a response signal corresponding to the first system error signal;

If the multiplex server is divided into at least two sub-servers, the key signal processing board acquires sub-server information of the multiplex server, and when receiving a third system error signal sent by any one of the PBI boards, according to the sub-server The server information determines that each PBI board belonging to the same sub-server as the PBI board that transmits the third system error signal; and each PBI other than the PBI board that transmits the third system error signal to the sub-server The board transmits a fourth system error signal as a response signal corresponding to the third system error signal.
The method of claim 9 wherein the method further comprises:

The key signal processing board receives the next first system error signal or the third system error signal when it is detected that the first system error signal or the third system error transmitted by the current PBI board changes from the active state to the inactive state.