TWI790110B - High-reliability server and multi-party key signal control method - Google Patents

High-reliability server and multi-party key signal control method Download PDF

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TWI790110B
TWI790110B TW111103552A TW111103552A TWI790110B TW I790110 B TWI790110 B TW I790110B TW 111103552 A TW111103552 A TW 111103552A TW 111103552 A TW111103552 A TW 111103552A TW I790110 B TWI790110 B TW I790110B
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logic device
signal
chip
motherboard
control
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TW202331507A (en
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王俊傑
曾彥綸
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神雲科技股份有限公司
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Abstract

A high-reliability server includes a first motherboard and a second motherboard. The first motherboard includes a first chip device. The second motherboard includes a second logic device and a second chip device. After the second logic device receives an encoded signal from the first logic device, when the second logic device receives another encoded signal in a time interval of receiving, then the second logic device decodes the two encoded signals to obtain two decoded signals result. When the second logic device compares the two decoding results to be the same, the second logic device performs a table look-up with a database according to the decoding results to generate a key control signal corresponding to one of the multiple control command codes. The second logic device outputs the key control signal to the second chip device for control, so that the second chip device performs a control procedure.

Description

高可靠功能的伺服器以及多方關鍵信號控制方法 Highly reliable server and multi-party key signal control method

本發明是有關於一種伺服器，特別是指一種高可靠功能的伺服器以及其多方關鍵信號控制方法。 The present invention relates to a server, in particular to a highly reliable server and its multi-party key signal control method.

現有的雙主機板技術，各主機板上的控制器可以對主機板所運行的系統進行重置、重新開機等修復的程序，即使另一主機板的控制器出現問題也可以相互修復，以達到高可靠性要求。通常複雜可程式化邏輯裝置(Complex Programmable Logic Device，以下簡稱CPLD)可以承擔控制器的角色。複雜可程式化邏輯裝置通常在其所在的主機板上負責主機板上的上電/下電電源時序、運行系統的主晶片重置等。如果其中一主機板上的主晶片有任何問題而無法通信，另一主機板上的主晶片會通知同一主機板上的複雜可程式化邏輯裝置以使其對該其中一主機板進行修復。需說明的是，所述主晶片是具有控制能力的晶片，例如是可以運作主機板的作業系統的中央處理器(CPU)、單晶片系統(SOC)等。 In the existing dual mainboard technology, the controllers on each mainboard can carry out repair programs such as resetting and restarting the system running on the mainboard. Even if there is a problem with the controller on the other mainboard, they can also repair each other to achieve high reliability requirements. Usually, a Complex Programmable Logic Device (CPLD for short) can assume the role of the controller. The complex programmable logic device is usually responsible for the power-on/power-off power sequence on the motherboard, the main chip reset of the running system, etc. on the motherboard where it is located. If the main chip on one of the motherboards has any problem and cannot communicate, the main chip on the other motherboard will notify the CPLD on the same motherboard so that it can repair the one of the motherboards. It should be noted that the main chip is a chip with control capability, such as a central processing unit (CPU), a system on a chip (SOC), and the like that can operate the operating system of the motherboard.

舉例來說，當第二主機板的主晶片沒有反應時，第一主機板的主晶片會透過積體匯流排電路(Inter-Integrated Circuit，以下簡稱I2C)總線通知對應的第一複雜可程式化邏輯裝置，第一複雜可程式化邏輯裝置則會透過通用型輸入輸出(General Purpose Input/Output，以下簡稱GPIO)接腳來向第二主機板的第二複雜可程式化邏輯裝置發送高準位的系統重置信號(假設低準位是系統不重置)，第二複雜可程式化邏輯裝置接收到該系統重置信號後將重置第二主機板的主晶片。 For example, when the main chip of the second main board does not respond, the main chip of the first main board will notify the corresponding first complex possible Programmable logic device, the first complex programmable logic device will send the Micro Motion The system reset signal of bit (assuming that the low level means that the system does not reset), the second complex programmable logic device will reset the main chip of the second motherboard after receiving the system reset signal.

現有的雙主機板技術具有以下缺點：在對其中一主機板進行熱插拔時，因為電壓落差改變GPIO接腳的信號準位而造成誤判，進而導致誤觸發另一主機板產生系統誤動作，降低系統可靠度件。舉例來說，二個主機原本皆在開機運作狀態，卻因GPIO接腳的信號準位短暫發生錯誤，導致其中之一的主機板被另一主機板強制關機或是原本第一主機板的主晶片傳輸重置信號至第二主機板，因為GPIO接腳的信號電壓準位落差，使得第二複雜可程式化邏輯裝置判斷錯誤，而誤判第一複雜可程式化邏輯裝置傳輸了修復信號(例如，恢復信號)至第二主機板。 The existing dual mainboard technology has the following disadvantages: when one of the mainboards is hot-swappable, the signal level of the GPIO pin is changed due to a voltage drop, causing misjudgment, which in turn causes the other mainboard to be triggered by mistake to generate a system malfunction, reducing the System Reliability Parts. For example, two hosts were originally powered on, but due to a temporary error in the signal level of the GPIO pin, one of the main boards was forced to shut down by the other main board or the main board of the first main board was forced to shut down. The chip transmits the reset signal to the second motherboard, because the signal voltage level drop of the GPIO pin makes the second complex programmable logic device judge wrongly, and misjudges that the first complex programmable logic device transmits the repair signal (such as , recovery signal) to the second motherboard.

因此，本發明的第一目的，即在提供一種可消除因為接腳的信號電壓誤差所產生的系統誤動作，而達到降低誤動作的高可 靠功能的伺服器。 Therefore, the first object of the present invention is to provide a system that can eliminate system malfunctions caused by signal voltage errors of the pins, and achieve a high reliability of reducing malfunctions. Server by function.

於是，本發明高可靠功能的伺服器，包含一第一主機板及一第二主機板。 Therefore, the server with high reliability function of the present invention includes a first main board and a second main board.

該第一主機板包括一第一晶片裝置與一電連接該第一晶片裝置的第一邏輯裝置，該第一邏輯裝置具有一資料庫，該資料庫儲存多種控制命令碼。該第二主機板包括一電連接該第一主機板的第二邏輯裝置與一電連接該第二邏輯裝置的第二晶片裝置，該第二邏輯裝置具有另一資料庫，該資料庫儲存該等控制命令碼。 The first motherboard includes a first chip device and a first logic device electrically connected to the first chip device. The first logic device has a database, and the database stores various control command codes. The second motherboard includes a second logic device electrically connected to the first motherboard and a second chip device electrically connected to the second logic device, the second logic device has another database, the database stores the Wait for the control command code.

該第二邏輯裝置接收來自該第一主機板的該第一邏輯裝置的一編碼信號後，當該第二邏輯裝置於一接收時間區間接收到另一編碼信號時，則對該二編碼信號進行解碼，以得到二解碼結果。該第二邏輯裝置比對該二解碼結果是否相同，且具有一資料庫。該資料庫儲存多種控制命令碼。 After the second logic device receives a coded signal from the first logic device of the first mainboard, when the second logic device receives another coded signal within a receiving time interval, it performs the second coded signal Decode to get the second decoding result. The second logic device compares whether the two decoding results are the same, and has a database. The database stores various control command codes.

若該第二邏輯裝置比對該二解碼結果是相同，則該第二邏輯裝置根據該解碼結果與該資料庫進行查表以產生一對應該等控制命令碼之一的關鍵控制信號。該第二邏輯裝置輸出該關鍵控制信號到該第二晶片裝置以進行控制，使該第二晶片裝置進行一控制程序。該控制程序包括一重置程序、一重啟程序與一恢復程序的其中之一。 If the second logic device compares the two decoding results to be the same, the second logic device performs table lookup with the database according to the decoding result to generate a key control signal of one of the corresponding control command codes. The second logic device outputs the key control signal to the second chip device for control, so that the second chip device performs a control program. The control program includes one of a reset program, a restart program and a recovery program.

本發明的第二目的，即在提供一種高可靠功能的多方關 鍵信號控制方法，由一伺服器執行，該伺服器包含一第一主機板及一第二主機板，該第一主機板包括一第一晶片裝置與一電連接該第一晶片裝置的第一邏輯裝置，該第一邏輯裝置具有一資料庫，該資料庫儲存多種控制命令碼，該第二主機板包括一電連接該第一主機板的第二邏輯裝置與一電連接該第二邏輯裝置的第二晶片裝置，該第二邏輯裝置具有另一資料庫，該資料庫儲存該等控制命令碼，該方法包含以下步驟(a)~(e)。 The second purpose of the present invention is to provide a multi-party relationship with high reliability function The key signal control method is executed by a server, the server includes a first motherboard and a second motherboard, the first motherboard includes a first chip device and a first chip device electrically connected to the first chip device Logic device, the first logic device has a database, the database stores a variety of control command codes, the second motherboard includes a second logic device electrically connected to the first motherboard and a second logic device electrically connected to the second logic device The second chip device, the second logic device has another database, the database stores the control command codes, the method includes the following steps (a) to (e).

步驟(a)該第一主機板的該第一邏輯裝置產生二編碼信號。 Step (a) The first logic device of the first motherboard generates two coded signals.

步驟(b)該第二邏輯裝置接收來自該第一主機板的該第一邏輯裝置的一編碼信號後，當該第二邏輯裝置於一接收時間區間接收到另一編碼信號時，則對該二編碼信號進行解碼，以得到二解碼結果。 Step (b) After the second logic device receives a coded signal from the first logic device of the first mainboard, when the second logic device receives another coded signal within a receiving time interval, the The second encoded signal is decoded to obtain a second decoding result.

步驟(c)該第二邏輯裝置比對該二解碼結果是否相同。 Step (c) the second logic device compares whether the two decoding results are the same.

步驟(d)若該第二邏輯裝置比對該二解碼結果是相同，則該第二邏輯裝置根據該解碼結果與該資料庫進行查表以產生一對應該等控制命令碼之一的關鍵控制信號。 Step (d) If the second logic device compares the two decoding results to be the same, then the second logic device performs a table lookup with the database according to the decoding result to generate a pair of key controls corresponding to one of the control command codes Signal.

步驟(e)該第二邏輯裝置輸出該關鍵控制信號到該第二晶片裝置以進行控制，使該第二晶片裝置處於一控制程序。該控制程序包括一重置程序、一重啟程序與一恢復程序的其中之一。 Step (e) The second logic device outputs the key control signal to the second chip device for control, so that the second chip device is in a control program. The control program includes one of a reset program, a restart program and a recovery program.

本發明的功效在於：該第二邏輯裝置接收來自該第一主機板的該第一邏輯裝置的該二編碼信號，且對該二編碼信號進行解碼，以得到二解碼結果，該第二邏輯裝置比對該二解碼結果是否相同。若該第二邏輯裝置比對該二解碼結果是相同，則該第二邏輯裝置根據該解碼結果與該資料庫進行查表以產生該對應該等控制命令碼之一的關鍵控制信號，該第二邏輯裝置輸出該關鍵控制信號到該第二晶片裝置以進行控制，使該第二晶片裝置處於該控制程序，該控制程序包括一重置程序、一重啟程序與一恢復程序的其中之一。而不會因為電壓準位落差，使得該第二邏輯裝置判斷錯誤，而傳輸錯誤信號。因此，確實能達成本發明之目的。 The effect of the present invention is that: the second logic device receives the second coded signal from the first logic device of the first motherboard, and decodes the two coded signal to obtain a second decoding result, the second logic device Check whether the two decoding results are the same. If the second logic device compares the two decoding results to be the same, the second logic device performs a table lookup with the database according to the decoding result to generate the key control signal corresponding to one of the control command codes, the first logic device The two logic devices output the key control signal to the second chip device for control, so that the second chip device is in the control program, and the control program includes one of a reset process, a restart process and a recovery process. The second logic device does not make an error in judgment and transmits an error signal due to a difference in voltage level. Therefore, can really reach the purpose of the present invention.

1:第一主機板 1: First motherboard

11:第一晶片裝置 11: The first wafer device

12:第一邏輯裝置 12: The first logic device

121:第一收發器 121: first transceiver

13:第一電源電路 13: The first power supply circuit

2:第二主機板 2: Second motherboard

21:第二晶片裝置 21: Second Wafer Device

22:第二邏輯裝置 22: Second logic device

221:第二收發器 221: second transceiver

23:第二電源電路 23: Second power supply circuit

300~310:信號傳遞的步驟 300~310: Steps of signal transmission

600~610:信號傳遞的步驟 600~610: Steps of signal transmission

本發明的其他的特徵及功效，將於參照圖式的實施方式中清楚地呈現，其中：圖1是本發明高可靠功能的伺服器的一實施例的一方塊圖；圖2是該實施例的一流程圖；圖3是該實施例的一流程圖；圖4是該實施例的一信號傳遞示意圖；及圖5是該實施例的一信號傳遞示意圖。 Other features and effects of the present invention will be clearly presented in the implementation manner with reference to the drawings, wherein: Fig. 1 is a block diagram of an embodiment of the server with high reliability function of the present invention; Fig. 2 is the embodiment FIG. 3 is a flowchart of this embodiment; FIG. 4 is a schematic diagram of signal transmission of this embodiment; and FIG. 5 is a schematic diagram of signal transmission of this embodiment.

在本發明被詳細描述之前，應當注意在以下的說明內容中，類似的元件是以相同的編號來表示。 Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same numerals.

參閱圖1，本發明高可靠功能的伺服器的一實施例，包含一第一主機板1及一第二主機板2。該第一主機板1包括一第一晶片裝置11、一電連接該第一晶片裝置11與該第二主機板2的第一邏輯裝置12及一電連接該第一邏輯裝置12且用於控制提供給第一晶片裝置11電力的第一電源電路13。該第二主機板2包括一第二晶片裝置21、一電連接該第二晶片裝置21與該第一主機板1的第二邏輯裝置22及一電連接該第二邏輯裝置22且用於控制提供給第二晶片裝置21電力的第二電源電路23。該第一邏輯裝置12具有一第一收發器121及一資料庫，該資料庫儲存多種控制命令碼。該第二邏輯裝置222具有一電連接該第一收發器121的第二收發器221及另一資料庫。該資料庫儲存該等控制命令碼。需注意的是，該第一邏輯裝置12與該第二邏輯裝置22是一可編程裝置，例如為一複雜可程式化邏輯裝置(Complex Programmable Logic Device,CPLD)、微控制器單元(microcontroller unit,MCU)或現場可程式化邏輯閘陣列(Field Programmable Gate Array,FPGA)等可被編程的晶片。該第一收發器121與該第二收發器221都是遵循一通用異步收發器(Universal Asynchronous Receiver/Transmitter， 以下簡稱UART)介面規範的收發器。也就是說，該第一主機板1與該第二主機板2是相同的主機板。 Referring to FIG. 1 , an embodiment of the highly reliable server of the present invention includes a first motherboard 1 and a second motherboard 2 . The first motherboard 1 includes a first chip device 11, a first logic device 12 electrically connected to the first chip device 11 and the second motherboard 2, and a first logic device 12 electrically connected to the first logic device 12 for controlling A first power supply circuit 13 that supplies power to the first wafer device 11 . The second motherboard 2 includes a second chip device 21, a second logic device 22 electrically connected to the second chip device 21 and the first motherboard 1, and a second logic device 22 electrically connected to the second logic device 22 for controlling The second power supply circuit 23 that supplies power to the second wafer device 21 . The first logic device 12 has a first transceiver 121 and a database for storing various control command codes. The second logic device 222 has a second transceiver 221 electrically connected to the first transceiver 121 and another database. The database stores the control command codes. It should be noted that the first logic device 12 and the second logic device 22 are programmable devices, such as a complex programmable logic device (Complex Programmable Logic Device, CPLD), a microcontroller unit (microcontroller unit, MCU) or Field Programmable Gate Array (Field Programmable Gate Array, FPGA) and other chips that can be programmed. Both the first transceiver 121 and the second transceiver 221 comply with a Universal Asynchronous Receiver/Transmitter (Universal Asynchronous Receiver/Transmitter, Hereinafter referred to as UART) interface specification transceiver. That is to say, the first motherboard 1 and the second motherboard 2 are the same motherboard.

如圖2、3所示，本實施例的伺服器執行一多方關鍵信號控制方法，包括步驟300~步驟310。當該第一晶片裝置11對該第二晶片裝置21進行通信過程中未收到來自該第二晶片裝置21的回應時，或者，該第一晶片裝置11經由網路接收到一觸發信號時，由步驟300開始，在步驟301中，該第一晶片裝置11用以產生一詢問信號(如圖4)傳送至該第一邏輯裝置12。例如，該詢問信號(以十六進位碼為例)是C4。需注意的是，該第一晶片裝置11是透過積體匯流排電路總線(I2C)與該第一邏輯裝置12進行通信。 As shown in FIGS. 2 and 3 , the server of this embodiment executes a multi-party key signal control method, including steps 300 to 310 . When the first chip device 11 does not receive a response from the second chip device 21 during the communication process with the second chip device 21, or when the first chip device 11 receives a trigger signal via the network, Starting from step 300 , in step 301 , the first chip device 11 is used to generate an inquiry signal (as shown in FIG. 4 ) and send it to the first logic device 12 . For example, the query signal (take the hexadecimal code as an example) is C4. It should be noted that the first chip device 11 communicates with the first logic device 12 through an integrated bus (I 2 C).

在步驟302中，該第一邏輯裝置12接收該詢問信號並產生一用以回應該詢問信號的第一確認信號傳送至該第一晶片裝置11。該第一確認信號例如是一確定回應信息(Acknowledge Message，ACK)。 In step 302 , the first logic device 12 receives the inquiry signal and generates a first confirmation signal in response to the inquiry signal and sends it to the first chip device 11 . The first acknowledgment signal is, for example, an acknowledgment message (Acknowledge Message, ACK).

在步驟303中，該第一晶片裝置11接收該第一確認信號後產生二封包信號傳送至該第一邏輯裝置12。該二封包信號具有同一控制命令碼。 In step 303 , the first chip device 11 generates a two-packet signal and sends it to the first logic device 12 after receiving the first confirmation signal. The two packet signals have the same control command code.

參閱圖2與圖5。圖5是該實施例的一信號傳遞示意圖。在步驟304中，該第一邏輯裝置12接收該二封包信號後，產生一用以回應該二封包信號的第二確認信號傳送至該第一晶片裝置11，且 該第一收發器121將該二封包信號編碼產生二編碼信號傳輸至該第二邏輯裝置22的該第二收發器221，其中，該二編碼信號均指示出相同的控制命令碼，且該第一邏輯裝置12在接收到該二封包信號的其中一者後且在一監控時間內未收到該二封包信號的其中另一者，則不產生且不傳送用以回應該二封包信號的該第二確認信號至該第一晶片裝置11或是更進一步的傳送一錯誤信號。需注意的是，舉例來說，該編碼信號是具有一0xAA(重置命令)、一0x99(重啟命令)或一0x44(恢復命令)的信號。該第二確認信號可以是另一確定回應信息。 See Figure 2 and Figure 5. FIG. 5 is a schematic diagram of signal transmission in this embodiment. In step 304, after receiving the two-packet signal, the first logic device 12 generates a second confirmation signal in response to the two-packet signal and transmits it to the first chip device 11, and The first transceiver 121 encodes the two-packet signal to generate a second encoded signal and transmits it to the second transceiver 221 of the second logic device 22, wherein the two encoded signals both indicate the same control command code, and the second encoded signal After a logic device 12 receives one of the two packet signals and does not receive the other one of the two packet signals within a monitoring time, it does not generate and transmit the two packet signals in response to the The second confirmation signal is sent to the first chip device 11 or further sends an error signal. It should be noted that, for example, the encoded signal is a signal with a 0xAA (reset command), a 0x99 (restart command) or a 0x44 (resume command). The second confirmation signal may be another confirmation response information.

在步驟305中，該第二邏輯裝置22的該第二收發器221接收來自該第一收發器121的該編碼信號後，當該第二邏輯裝置22於一接收時間區間接收到該另一編碼信號時，則對該二編碼信號進行解碼，以得到二解碼結果。 In step 305, after the second transceiver 221 of the second logic device 22 receives the encoded signal from the first transceiver 121, when the second logic device 22 receives the another encoded signal within a receiving time interval signal, the second encoded signal is decoded to obtain a second decoding result.

在步驟306中，該第二邏輯裝置22比對該二解碼結果是否相同。 In step 306, the second logic device 22 compares whether the two decoding results are the same.

若該第二邏輯裝置22比對該二解碼結果是相同，則在步驟307~308中，該第二邏輯裝置22根據該解碼結果與該資料庫進行查表以產生一對應該等控制命令碼之一的關鍵控制信號。該第二邏輯裝置22輸出該關鍵控制信號到該第二晶片裝置21以進行控制，使該第二晶片裝置21進行一控制程序。該控制程序包括一重置 程序、一重啟程序與一恢復程序的其中之一。舉例來說，若該編碼信號是0xAA，則該第二邏輯裝置22將重置該第二晶片裝置21，也就是說，該第二邏輯裝置22傳送對應該編碼信號0xAA的該關鍵控制信號至該第二晶片裝置21，以觸發該第二晶片裝置21進行該重置程序。若該編碼信號是0x99，則該第二邏輯裝置22將進行重啟程序，詳細而言，在進行該重啟程序的過程，該第二邏輯裝置22將禁能該第二電源電路2323以關閉供該第二主機板2運作所使用的一主電源，進而使該第二晶片裝置21因沒有收到該主電源而進行關機程序，經一預設時間後，該第二邏輯裝置22致能該第二電源電路23以促使該第二晶片裝置21進行開機程序，進而完成關機後再開機的重啟程序。若該編碼信號是0x44，則該第二邏輯裝置22將強制該第二晶片裝置21進入恢復模式，也就是說，該第二邏輯裝置22觸發該第二晶片裝置21載入並執行預設韌體、載入並執行預設參數組及進行韌體更新其中任一者或任兩者之組合。 If the second logic device 22 compares the two decoding results to be the same, then in steps 307 to 308, the second logic device 22 performs table look-up with the database according to the decoding result to generate a pair of corresponding control command codes One of the key control signals. The second logic device 22 outputs the key control signal to the second chip device 21 for control, so that the second chip device 21 performs a control procedure. The control procedure includes a reset One of a program, a restart program and a recovery program. For example, if the encoding signal is 0xAA, the second logic device 22 will reset the second chip device 21, that is, the second logic device 22 transmits the key control signal corresponding to the encoding signal 0xAA to The second chip device 21 is used to trigger the second chip device 21 to perform the reset procedure. If the encoded signal is 0x99, then the second logic device 22 will perform a restart procedure. Specifically, during the restart procedure, the second logic device 22 will disable the second power supply circuit 2323 to shut down the power supply circuit 2323. A main power used for the operation of the second motherboard 2, and then make the second chip device 21 perform a shutdown process because it does not receive the main power, and after a preset time, the second logic device 22 enables the first chip device 21. The second power supply circuit 23 is used to prompt the second chip device 21 to perform a boot process, and then to complete a reboot process of shutting down and then booting up. If the encoding signal is 0x44, the second logic device 22 will force the second chip device 21 to enter recovery mode, that is, the second logic device 22 triggers the second chip device 21 to load and execute the default firmware. firmware, loading and executing a default parameter set, and performing firmware update, or a combination of both.

當該第二邏輯裝置22比對該二解碼結果是不相同時，則在步驟309中，該第二邏輯裝置22不輸出該關鍵控制信號。 When the second logic device 22 compares the two decoding results to be different, then in step 309 , the second logic device 22 does not output the key control signal.

在步驟310中，結束整個流程。 In step 310, the entire process ends.

另外要特別補充說明的是：在本實施例中是由該第一主機板1對該第二主機板2的該第二晶片裝置21進行該控制程序。類似地，在其他的實施例中，當該第二晶片裝置21對該第一晶片裝置 11進行通信過程中未收到來自該第一晶片裝置11的回應時，或者，該第二晶片裝置21經由網路接收到該觸發信號時，該第二主機板2也會對該第一主機板1的該第一晶片裝置11進行該控制程序。 In addition, it should be specially added that: in this embodiment, the first motherboard 1 performs the control program on the second chip device 21 of the second motherboard 2 . Similarly, in other embodiments, when the second wafer device 21 is connected to the first wafer device 11 When no response is received from the first chip device 11 during the communication process, or when the second chip device 21 receives the trigger signal via the network, the second main board 2 will also respond to the first host The first wafer device 11 of the panel 1 executes the control program.

綜上所述，上述實施例具有以下優點：優點一，該第二邏輯裝置22透過接收該二編碼信號並對該二編碼信號進行解碼，比對該二解碼結果是相同時才輸出該關鍵控制信號。可完全消除因為接腳的信號電壓誤差所產生的系統誤動作(產生錯誤的關鍵控制信號)，而達到降低誤動作且百分之百的可靠度。 In summary, the above-mentioned embodiment has the following advantages: Advantage 1, the second logic device 22 receives and decodes the two coded signals, and only outputs the key control when the two decoding results are the same Signal. It can completely eliminate the system malfunction (generating wrong key control signal) caused by the signal voltage error of the pin, so as to reduce the malfunction and achieve 100% reliability.

優點二，該第一邏輯裝置12與該第二邏輯裝置22分別透過該通用異步收發器(UART)取代通用型輸入輸出(GPIO)接腳作為彼此間傳輸信號。因此，只需要一組連接埠即可傳輸N種以上的控制命令(N≧3)，相較於現有GPIO接腳需要N組連接埠用來傳輸N種控制命令，大幅減少連接埠數量，藉此兩主機板其中之一者的晶片裝置透過其邏輯裝置的收發器並經由兩主機板其中另一者的邏輯裝置來控制其晶片裝置，也就是說，根據本發明的架構，本發明的兩主機板可以使用較少的連接埠即可達到兩主機板所分別對應的晶片裝置可進行較高可靠性的相互控制與溝通。故確實能達成本發明的目的。 The second advantage is that the first logic device 12 and the second logic device 22 use the universal asynchronous transceiver (UART) instead of the general purpose input output (GPIO) pin as the transmission signal between each other. Therefore, only one set of ports is needed to transmit more than N types of control commands (N≧3). Compared with the existing GPIO pins, N groups of ports are required to transmit N types of control commands, which greatly reduces the number of ports. The chip device of one of the two motherboards controls its chip device through the transceiver of its logic device and the logic device of the other of the two motherboards, that is, according to the framework of the present invention, the two motherboards of the present invention The main board can use fewer connection ports to achieve high reliability mutual control and communication between the respective chip devices corresponding to the two main boards. Therefore really can reach the purpose of the present invention.

惟以上所述者，僅為本發明的實施例而已，當不能以此限定本發明實施的範圍，凡是依本發明申請專利範圍及專利說明書 內容所作的簡單的等效變化與修飾，皆仍屬本發明專利涵蓋的範圍內。 But above-mentioned person, only embodiment of the present invention, when can not limit the scope of the present invention implementation with this, every according to the patent scope of the present invention application and patent description Simple equivalent changes and modifications made in the content still fall within the scope covered by the patent of the present invention.

1:第一主機板 1: First motherboard

11:第一晶片裝置 11: The first wafer device

12:第一邏輯裝置 12: The first logic device

121:第一收發器 121: first transceiver

13:第一電源電路 13: The first power supply circuit

2:第二主機板 2: Second motherboard

21:第二晶片裝置 21: Second Wafer Device

22:第二邏輯裝置 22: Second logic device

221:第二收發器 221: second transceiver

23:第二電源電路 23: Second power supply circuit

300~310:信號傳遞的步驟 300~310: Steps of signal transmission

Claims (10)

一種高可靠功能的伺服器，包含：一第一主機板，包括一第一晶片裝置與一電連接該第一晶片裝置的第一邏輯裝置，該第一邏輯裝置具有一資料庫，該資料庫儲存多種控制命令碼；及一第二主機板，包括一電連接該第一主機板的第二邏輯裝置與一電連接該第二邏輯裝置的第二晶片裝置，該第二邏輯裝置具有另一資料庫，該資料庫儲存該等控制命令碼，該第一晶片裝置接收來自該第一邏輯裝置的一第一確認信號後產生二封包信號傳送至該第一邏輯裝置，該第一邏輯裝置接收該二封包信號後，將該二封包信號編碼產生二編碼信號傳輸至該第二主機板的該第二邏輯裝置，其中，該二編碼信號均指示出相同的控制命令碼；該第二邏輯裝置接收來自該第一主機板的該第一邏輯裝置的該編碼信號後，當該第二邏輯裝置於一接收時間區間接收到該另一編碼信號時，則對該二編碼信號進行解碼，以得到二解碼結果，該第二邏輯裝置比對該二解碼結果是否相同，若該第二邏輯裝置比對該二解碼結果是相同，則該第二邏輯裝置根據該解碼結果與該資料庫進行查表以產生一對應該等控制命令碼之一的關鍵控制信號，該第二邏輯裝置輸出該關鍵控制信號到該第二晶片裝置以進行控制，使該第二晶片裝置進行一控制程序，該控制程序包括一重置程序、一重啟程序與一恢復程序的其 中之一。 A server with high reliability function, comprising: a first motherboard, including a first chip device and a first logic device electrically connected to the first chip device, the first logic device has a database, the database store a variety of control command codes; and a second motherboard, including a second logic device electrically connected to the first motherboard and a second chip device electrically connected to the second logic device, the second logic device has another A database, the database stores the control command codes, the first chip device receives a first confirmation signal from the first logic device and then generates a two-packet signal to send to the first logic device, and the first logic device receives After the two-packet signal, encode the two-packet signal to generate a two-coded signal and transmit it to the second logic device on the second motherboard, wherein the two coded signals all indicate the same control command code; the second logic device After receiving the coded signal from the first logic device of the first motherboard, when the second logic device receives the other coded signal within a receiving time interval, it decodes the second coded signal to obtain Two decoding results, the second logic device compares whether the two decoding results are the same, if the second logic device compares the two decoding results to be the same, then the second logic device performs table lookup with the database according to the decoding results To generate a key control signal of one of the control command codes, the second logic device outputs the key control signal to the second chip device for control, so that the second chip device performs a control program, the control program including a reset procedure, a restart procedure and a recovery procedure one of. 如請求項1所述的高可靠功能的伺服器，其中，當該二解碼結果不同時，則該第二邏輯裝置不輸出該關鍵控制信號。 The server with high reliability function as claimed in claim 1, wherein, when the two decoding results are different, the second logic device does not output the key control signal. 如請求項1所述的高可靠功能的伺服器，其中，該第一邏輯裝置電連接該第二主機板的該第二邏輯裝置，該第一晶片裝置用以產生一詢問信號傳送至該第一邏輯裝置，該第一邏輯裝置接收該詢問信號並產生該用以回應該詢問信號的第一確認信號傳送至該第一晶片裝置，該第一邏輯裝置接收該二封包信號後，產生一用以回應該二封包信號的第二確認信號傳送至該第一晶片裝置。 The server with high reliability function as claimed in item 1, wherein the first logic device is electrically connected to the second logic device of the second motherboard, and the first chip device is used to generate an inquiry signal and send it to the first chip device A logic device, the first logic device receives the inquiry signal and generates the first confirmation signal for responding to the inquiry signal and transmits it to the first chip device, after receiving the second packet signal, the first logic device generates a A second acknowledgment signal in response to the two-packet signal is sent to the first chip device. 如請求項3所述的高可靠功能的伺服器，其中，該第一邏輯裝置與該第二邏輯裝置是一複雜可程式化邏輯裝置。 The server with high reliability function as claimed in claim 3, wherein the first logic device and the second logic device are a complex programmable logic device. 如請求項3所述的高可靠功能的伺服器，其中，該第一邏輯裝置具有一第一收發器，該第二邏輯裝置具有一電連接該第一收發器的第二收發器，該第一收發器用以傳輸該二編碼信號至該第二收發器。 The server with high reliability function as described in claim 3, wherein, the first logic device has a first transceiver, the second logic device has a second transceiver electrically connected to the first transceiver, and the first logic device has a second transceiver electrically connected to the first transceiver. A transceiver is used for transmitting the second encoded signal to the second transceiver. 如請求項4所述的高可靠功能的伺服器，其中，該第一收發器與該第二收發器都是一通用異步收發器。 The server with high reliability function as claimed in claim 4, wherein both the first transceiver and the second transceiver are a Universal Asynchronous Transceiver. 一種高可靠功能的多方關鍵信號控制方法，由一伺服器執行，該伺服器包含一第一主機板及一第二主機板，該第一主機板包括一第一晶片裝置與一電連接該第一晶片裝置的第一邏輯裝置，該第一邏輯裝置具有一資料庫，該資料庫儲存多種控制命令碼，該第二主機板包括一電連接該第 一主機板的第二邏輯裝置與一電連接該第二邏輯裝置的第二晶片裝置，該第二邏輯裝置具有另一資料庫，該資料庫儲存該等控制命令碼，該方法包含以下步驟：(s3)該第一晶片裝置接收來自該第一邏輯裝置的一第一確認信號後產生二封包信號傳送至該第一邏輯裝置；(a)該第一邏輯裝置接收該二封包信號後，將該二封包信號編碼產生二編碼信號傳輸至該第二主機板的該第二邏輯裝置，其中，該二編碼信號均指示出相同的控制命令碼；(b)該第二邏輯裝置接收來自該第一主機板的該第一邏輯裝置的該編碼信號後，當該第二邏輯裝置於一接收時間區間接收到該另一編碼信號時，則對該二編碼信號進行解碼，以得到二解碼結果；(c)該第二邏輯裝置比對該二解碼結果是否相同；(d)若該第二邏輯裝置比對該二解碼結果是相同，則該第二邏輯裝置根據該解碼結果與該資料庫進行查表以產生一對應該等控制命令碼之一的關鍵控制信號；及(e)該第二邏輯裝置輸出該關鍵控制信號到該第二晶片裝置以進行控制，使該第二晶片裝置進行一控制程序，該控制程序包括一重置程序、一重啟程序與一恢復程序的其中之一。 A multi-party key signal control method with high reliability functions is executed by a server. The server includes a first main board and a second main board. The first main board includes a first chip device and an electrical connection to the first main board. A first logic device of a chip device, the first logic device has a database, the database stores a variety of control command codes, the second motherboard includes an electrical connection to the first A second logic device on a motherboard and a second chip device electrically connected to the second logic device, the second logic device has another database, the database stores the control command codes, the method includes the following steps: (s3) After the first chip device receives a first confirmation signal from the first logic device, it generates a two-packet signal and transmits it to the first logic device; (a) after the first logic device receives the two-packet signal, it sends The two-packet signal encoding generates two coded signals and transmits them to the second logic device on the second motherboard, wherein the two coded signals all indicate the same control command code; (b) the second logic device receives from the second logic device After receiving the coded signal from the first logic device of a motherboard, when the second logic device receives the other coded signal within a receiving time interval, it decodes the two coded signals to obtain two decoding results; (c) whether the second logic device compares the two decoding results to be the same; (d) if the second logic device compares the two decoding results to be the same, then the second logic device performs the same with the database according to the decoding result Look up the table to generate a key control signal of one of the control command codes; and (e) the second logic device outputs the key control signal to the second chip device for control, so that the second chip device performs a The control program includes one of a reset program, a restart program and a recovery program. 如請求項7所述的高可靠功能的多方關鍵信號控制方法，其中，該方法還包含以下步驟：(f)當該二解碼結果不同時，則該第二邏輯裝置不 輸出該關鍵控制信號。 The multi-party key signal control method with high reliability function as described in claim item 7, wherein the method also includes the following steps: (f) when the two decoding results are different, the second logic device does not Output the key control signal. 如請求項7所述的高可靠功能的多方關鍵信號控制方法，其中，該第一主機板包括一第一晶片裝置與一電連接該第一晶片裝置與該第二主機板的該第二邏輯裝置的第一邏輯裝置，該方法還包含以下步驟：(s1)在該步驟(a)之前，該第一晶片裝置用以產生一詢問信號傳送至該第一邏輯裝置；(s2)該第一邏輯裝置接收該詢問信號並產生一用以回應該詢問信號的第一確認信號傳送至該第一晶片裝置。 The multi-party key signal control method with high reliability function as described in claim 7, wherein the first motherboard includes a first chip device and the second logic electrically connecting the first chip device and the second motherboard The first logic device of the device, the method further includes the following steps: (s1) before the step (a), the first chip device is used to generate an inquiry signal and send it to the first logic device; (s2) the first The logic device receives the query signal and generates a first confirmation signal in response to the query signal and sends it to the first chip device. 如請求項9所述的高可靠功能的多方關鍵信號控制方法，其中，該方法還包含以下步驟：(s4)該第一邏輯裝置接收該二封包信號後，產生一用以回應該二封包信號的第二確認信號傳送至該第一晶片裝置。 The multi-party key signal control method with high reliability function as described in claim item 9, wherein, the method also includes the following steps: (s4) After receiving the two-packet signal, the first logic device generates a response to the two-packet signal The second acknowledgment signal is sent to the first wafer device.
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