CN110708185B - Data interconnection method, system, chip and device for artificial intelligence processor - Google Patents
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Abstract
The invention provides a data interconnection method, a system, a chip and a device for artificial intelligence processors, which comprise a PCIe interconnection topology tree formed by connecting a plurality of PCIe switches in series, wherein an upstream port of a first PCIe Switch in the PCIe interconnection topology tree is connected with a general processor, and each artificial intelligence processor is connected with a downstream port of one PCIe Switch in the PCIe interconnection topology tree; connecting the first sensor to a downstream port of any PCIe Switch in the PCIe interconnection topology tree through a PCIe bridge; establishing a PCIe-SRIO bridging module to realize the conversion between an SRIO protocol and a PCIe protocol, and connecting a PCIe port of the PCIe-SRIO bridging module to a downstream port of any PCIe Switch in a PCIe interconnection topology tree; an SRIO port of a PCIe-SRIO bridge module is connected to the SRIO switches to establish an interconnection path between the SRIO interconnection topology tree and the PCIe interconnection topology tree; and connecting the second sensor to an idle port of any SRIO switch in the SRIO interconnection topology tree through the SRIO bridge.
Description
Technical Field
The invention relates to the technical field of communication and computer system structures, in particular to an artificial intelligence processor data interconnection method and a related product.
Background
Data interconnection is a step and a stage which are needed to be passed by most electronic components, integrated circuits, computer products and communication equipment in the practical application process. With the rapid development of machine learning algorithms, artificial intelligence processors come along with the development of machine learning algorithms. The artificial intelligence processor is designed to provide an algorithmic guarantee for a machine learning algorithm.
The aforementioned artificial intelligence processor is a type of microprocessor that is intended to accelerate machine learning algorithms, such as deep learning algorithms, reinforcement learning algorithms, that are applied to data intensive or sensor driven tasks. Artificial intelligence processors are products derived in the large background of the artificial intelligence era. An artificial intelligence processor, namely the Carnival 1A, is successfully developed in 2016 of the research of the computing technology of the Chinese academy of sciences, the IP of the artificial intelligence processor is integrated into a kylin 970 processor, and the artificial intelligence processor is applied to various intelligent terminals. In order to enable the processing speed of a chip to be faster, a special storage structure is specially designed for 1A, an instruction set completely different from a general CPU is designed, the theoretical peak performance is 5120 billion times of half-precision floating point operation per second under 1GHz main frequency, and the equivalent theoretical peak of a sparse neural network reaches 2 trillion times of floating point operation per second. The cambrian era in 2018 publishes a second generation high-performance machine learning processor, namely cambrian MLU100, and comprehensively supports diversified machine learning applications, not only common deep learning. The MLU100 is based on a multi-core parallel architecture, the 8-bit fixed point computing power of the MLU reaches 128TOPS, the power consumption can be dynamically adjusted, and the MLU is widely applied to reasoning tasks of an object side, an edge and a cloud side.
The artificial intelligence processor needs to perform a large amount of data interaction with the outside of the artificial intelligence processor in the process of executing the machine learning algorithm. The existing artificial intelligence processor is mainly communicated with a sensor data source end through a PCIe interface. The application range of the artificial intelligence processor is restricted by a single communication mode, and particularly in an embedded system application scene, a PCIe communication interface is not adopted usually, so that the artificial intelligence processor cannot be directly applied.
The embedded system mainly refers to a special computer system designed for specific applications. An embedded system is a system for controlling or monitoring a large-scale device such as a machine, an apparatus, a factory, or the like. Unlike general-purpose computer systems such as personal computers and servers, embedded systems typically perform predefined tasks with specific requirements. Because embedded systems are designed for several special tasks, their functionality, reliability, cost, size, power consumption, environmental suitability are all critical requirements. From the aspect of appearance, the embedded system is usually a system on a chip, or a circuit board, or an electronic device formed by connecting a plurality of board cards, and the program thereof is stored in a computer readable storage medium. In fact, all electronic devices except general-purpose computer systems such as personal computers and servers belong to the category of embedded systems.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides 1. a data interconnection method for an artificial intelligence processor, which comprises the following steps:
step 1, a PCIe interconnection topology tree is formed by connecting a plurality of PCIeSlighs in series, an upstream port of a first PCIeSligh in the PCIe interconnection topology tree is connected with a general processor, and each artificial intelligent processor is connected with a downstream port of one PCIeSligh in the PCIe interconnection topology tree;
step 3, building a PCIe-SRIO bridging module to realize the conversion between an SRIO protocol and a PCIe protocol, and connecting a PCIe port of the PCIe-SRIO bridging module to a downstream port of any PCIeSlitch in the PCIe interconnection topological tree;
step 4, forming an SRIO interconnection topology tree by interconnecting a plurality of SRIO switches, and connecting an SRIO port of the PCIe-SRIO bridging module to the SRIO switches so as to establish an interconnection path between the SRIO interconnection topology tree and the PCIe interconnection topology tree;
step 5, acquiring a second sensor, and connecting the second sensor to an idle port of any SRIO switch in the SRIO interconnection topology tree through an SRIO bridge;
and 6, the first sensor realizes data interconnection with the artificial intelligence processor through the PCIe bridge and the PCIe interconnection topology tree, and the second sensor realizes data interconnection with the artificial intelligence processor through the SRIO bridge, the SRIO interconnection topology tree, the PCIe-SRIO bridge module and the PCIe interconnection topology tree.
The PCIe-SRIO bridging module built in the step 3 consists of an SRIO physical layer interface sub-module, an SRIO data packet processing sub-module, a PCIe physical layer interface sub-module, a PCIe data packet processing sub-module and a shared memory;
the SRIO physical layer interface sub-module comprises a plurality of physical layer communication channels, is connected with an idle port of the SRIO switch in the SRIO interconnection topological tree connection and is used for transmitting the SRIO data packet generated by the second sensor;
the SRIO data packet processing submodule is connected with the SRIO physical layer interface submodule and is used for preprocessing the SRIO data packet and storing the preprocessed SRIO data packet into the shared memory;
the PCIe data packet processing submodule is used for acquiring the SRIO data packet from the shared memory, converting the SRIO data packet into a PCIe protocol and recoding the PCIe protocol to obtain a conversion data packet meeting the PCIe protocol, and sending the conversion data packet to a downstream port of any PCIeSlick in the PCIe interconnection topology tree through the PCIe physical layer interface submodule.
The PCIe packet processing sub-module includes a PCIe transaction layer TLP processing function unit, a PCIe link layer TLP transceiving verification function unit, a PCIe physical layer byte distribution merging function unit, a PCIe physical layer data stream coding and decoding function unit, a PCIe physical layer data stream scrambling and descrambling function unit, and a PCIe physical layer data stream serial-parallel conversion function unit.
The data interconnection method for the artificial intelligence processor, wherein the SRIO data packet processing submodule comprises:
the SRIO data packet analysis functional unit is used for analyzing and processing the SRIO data message, communicating with the shared memory and temporarily storing the SRIO data message;
the SRIO data packet routing function unit is used for carrying out ID addressing and distribution path selection on the SRIO data message;
the SRIO data packet checking functional unit is used for checking the SRIO data message;
the data extraction functional unit is used for receiving the physical layer data stream from the SRIO physical layer interface sub-module and extracting effective data in the SRIO physical layer data stream;
the data packing functional unit is constructed and used for packing and packing the SRIO protocol data according to the SRIO physical layer requirement and sending the packed data to an SRIO physical layer interface sub-module;
the PCIe data packet processing submodule comprises:
a PCIe transaction layer TLP data packet processing functional unit, configured to generate a data packet used by a PCIe bus, communicate with the shared memory, and temporarily store the TLP;
a PCIe link layer TLP transceiving and checking functional unit, configured to perform transceiving processing on the TLP and perform checking processing on the TLP;
a PCIe physical layer byte distribution and merging functional unit, configured to perform byte distribution on a TLP, merge data from different channels, and perform a debounce operation;
the PCIe physical layer data stream encoding and decoding functional unit is used for encoding and decoding the PCIe physical layer data stream;
and the PCIe physical layer data stream scrambling and descrambling functional unit is used for scrambling and descrambling the PCIe physical layer data stream.
And the PCIe physical layer data stream serial-parallel conversion functional unit is used for converting the serial data stream into a parallel data stream and converting the parallel data stream into the serial data stream.
The invention also provides a data interconnection system for the artificial intelligence processor, which comprises:
the module 1 is connected with a plurality of PCIeSlighs in series to form a PCIe interconnection topological tree, an upstream port of a first PCIeSligh in the PCIe interconnection topological tree is connected with a general processor, and each artificial intelligent processor is connected with a downstream port of one PCIeSligh in the PCIe interconnection topological tree;
the module 2 acquires a first sensor, and connects the first sensor to a downstream port of any PCIeSchw in the PCIe interconnection topology tree through a PCIe bridge;
the module 3 is used for building a PCIe-SRIO bridge module to realize the conversion between an SRIO protocol and a PCIe protocol and connecting a PCIe port of the PCIe-SRIO bridge module to a downstream port of any PCIeSlitch in the PCIe interconnection topological tree;
the module 4 is used for forming an SRIO interconnection topology tree by interconnecting a plurality of SRIO switches, and connecting an SRIO port of the PCIe-SRIO bridging module to the SRIO switches so as to establish an interconnection path between the SRIO interconnection topology tree and the PCIe interconnection topology tree;
the module 5 acquires a second sensor, and connects the second sensor to an idle port of any SRIO switch in the SRIO interconnection topology tree through an SRIO bridge;
the module 6 and the first sensor realize data interconnection with the artificial intelligence processor through the PCIe bridge and the PCIe interconnection topology tree, and the second sensor realizes data interconnection with the artificial intelligence processor through the SRIO bridge, the SRIO interconnection topology tree, the PCIe-SRIO bridge module and the PCIe interconnection topology tree.
In the data interconnection system for the artificial intelligence processor, the PCIe-SRIO bridge module built in the module 3 consists of an SRIO physical layer interface sub-module, an SRIO data packet processing sub-module, a PCIe physical layer interface sub-module, a PCIe data packet processing sub-module and a shared memory;
the SRIO physical layer interface sub-module comprises a plurality of physical layer communication channels, is connected with an idle port of the SRIO switch in the SRIO interconnection topological tree connection and is used for transmitting the SRIO data packet generated by the second sensor;
the SRIO data packet processing submodule is connected with the SRIO physical layer interface submodule and is used for preprocessing the SRIO data packet and storing the preprocessed SRIO data packet into the shared memory;
the PCIe data packet processing submodule is used for acquiring the SRIO data packet from the shared memory, converting the SRIO data packet into a PCIe protocol and recoding the PCIe protocol to obtain a conversion data packet meeting the PCIe protocol, and sending the conversion data packet to a downstream port of any PCIeSlick in the PCIe interconnection topology tree through the PCIe physical layer interface submodule.
The PCIe packet processing sub-module includes a PCIe transaction layer TLP data packet processing function unit, a PCIe link layer TLP transceiving verification function unit, a PCIe physical layer byte distribution merging function unit, a PCIe physical layer data stream coding/decoding function unit, a PCIe physical layer data stream scrambling/descrambling function unit, and a PCIe physical layer data stream serial-parallel conversion function unit.
The data interconnection system for the artificial intelligence processor, wherein the SRIO data packet processing submodule comprises:
the SRIO data packet analysis functional unit is used for analyzing and processing the SRIO data message, communicating with the shared memory and temporarily storing the SRIO data message;
the SRIO data packet routing function unit is used for carrying out ID addressing and distribution path selection on the SRIO data message;
the SRIO data packet checking functional unit is used for checking the SRIO data message;
the data extraction functional unit is used for receiving the physical layer data stream from the SRIO physical layer interface sub-module and extracting effective data in the SRIO physical layer data stream;
the data packing functional unit is constructed and used for packing and packing the SRIO protocol data according to the SRIO physical layer requirement and sending the packed data to an SRIO physical layer interface sub-module;
the PCIe data packet processing submodule comprises:
a PCIe transaction layer TLP data packet processing functional unit, configured to generate a data packet used by a PCIe bus, communicate with the shared memory, and temporarily store the TLP;
a PCIe link layer TLP transceiving and checking functional unit, configured to perform transceiving processing on the TLP and perform checking processing on the TLP;
a PCIe physical layer byte distribution and merging functional unit, configured to perform byte distribution on a TLP, merge data from different channels, and perform a debounce operation;
the PCIe physical layer data stream encoding and decoding functional unit is used for encoding and decoding the PCIe physical layer data stream;
and the PCIe physical layer data stream scrambling and descrambling functional unit is used for scrambling and descrambling the PCIe physical layer data stream.
And the PCIe physical layer data stream serial-parallel conversion functional unit is used for converting the serial data stream into a parallel data stream and converting the parallel data stream into the serial data stream.
The invention also provides a data interconnection chip for the artificial intelligence processor, wherein the data interconnection chip is used for storing a program for executing any data interconnection method.
The invention also provides a data interconnection device for the artificial intelligence processor, which comprises:
the PCIe interconnection topology tree is composed of a plurality of PCIeSlighs connected in series, an upstream port of a first PCIeSligch in the PCIe interconnection topology tree is used for connecting a general processor, and each artificial intelligent processor is connected with a downstream port of one PCIeSligch in the PCIe interconnection topology tree;
the PCIe bridge is used for receiving the sensing data generated by the first sensor and is connected to a downstream port of any PCIeSchw in the PCIe interconnection topology tree;
the PCIe-SRIO bridging module is used for realizing the conversion between an SRIO protocol and a PCIe protocol and connecting a PCIe port of the PCIe-SRIO bridging module to a downstream port of any PCIe Switch in the PCIe interconnection topology tree;
the SRIO interconnection topology tree is composed of a plurality of SRIO switches which are interconnected, and an SRIO port of the PCIe-SRIO bridging module is connected to the SRIO switches so as to establish an interconnection path between the SRIO interconnection topology tree and the PCIe interconnection topology tree;
and the SRIO bridge is used for receiving the sensing data generated by the second sensor and is connected to the idle port of any SRIO switch in the SRIO interconnection topology tree.
According to the scheme, the invention has the advantages that:
the advantages of an artificial intelligence processor data interconnection method and related products include the following three aspects:
(1) the problem of interconnection and intercommunication between sensors with different types and different interfaces and an artificial intelligence processor is solved.
(2) The problem of data interconnection among a plurality of artificial intelligence processors in an embedded system is solved.
(3) The application scope of the artificial intelligence processor is expanded, the intelligent hardware product form for the artificial intelligence processor is enriched, and the application scene of the embedded system is expanded from a general computing scene, such as a personal computer and a server. At present, artificial intelligence processors are all used on general purpose computers because the PCIe interface resources of the general purpose computers are abundant. Products on the market are all board cards made based on an artificial intelligence processor, similar to display cards and standard PCIe interface board cards. The PCIe interface is not available in the embedded system, because the PCIe interface is not suitable for the embedded environments of miniaturization, vibration resistance and the like. In current embedded equipment, other communication interfaces than PCIe are generally used. By utilizing the interconnection device, the artificial intelligence processor can be interconnected with various embedded sensors. The bridge module has mature bridge chips on the market, and developers write bridge logic by using the FPGA. All mature chips or FPGA implementations have limitations, and are different in the number of interface channels (similar data bit width) and implementation details of protocol conversion. Since the bridge module is an essential link of the interconnection apparatus of the present invention, the present invention provides an implementation principle of the bridge module, and compared with the existing solutions, the present invention has technical advances in universality and expansibility, for example, the number of interface channels supported by the present invention is 1 to n, and the mature chip is generally 4 interface channels.
Drawings
FIG. 1 is a diagram of an artificial intelligence processor data interconnect architecture;
FIG. 2 is a PCIe interconnect topology diagram;
FIG. 3 is a SRIO interconnect topology diagram;
FIG. 4 is a diagram of a PCIe-SRIO bridging module;
FIG. 5 is a diagram of the internal connection relationship of the SRIO packet processing sub-module;
fig. 6 is a diagram of the internal connection relationship of the PCIe packet processing sub-module.
Detailed Description
The data interconnection method of the artificial intelligence processor can expand the communication mode of the artificial intelligence processor, so that the artificial intelligence processor can be interconnected with sensors of various types, various systems and various interfaces, and the data intelligent processing under various scenes is realized.
The related products comprise all chips, interconnection devices and electronic equipment adopting the artificial intelligence processor data interconnection method.
The data interconnection method of the artificial intelligence processor and the related product realize interconnection among different artificial intelligence processors and interconnection between the artificial intelligence processor and various sensors. An interconnection architecture of an artificial intelligence processor data method is shown in figure 1, and a core interconnection topological structure of the artificial intelligence processor data method is located inside a dot-dash rectangular frame and consists of five functional components: PCIe interconnection topology tree, PCIe bridge, PCIe-SRIO bridge module, SRIO interconnection topology tree and SRIO bridge.
The PCIe bridge refers to a PCIe-other interface switching module.
The SRIO bridge refers to an SRIO-other interface switching module.
Component 1 — PCIe interconnect topology tree:
the PCIe interconnect topology tree assumes three functional roles: the parallel access of a plurality of artificial intelligent processors, the access of a PCIe-SRIO bridge module and the access of a PCIe bridge are realized. As shown in fig. 2, PCIe interconnect mainly relies on the PCIe switch module to implement topology building. In the PCIe bus, the PCIe switch is composed of 1 upstream port and a plurality of downstream ports. The port that may be directly or indirectly connected to the CPU in one pci switch is an upstream port. All ports in the pci express except for the upstream port are downstream ports. The downstream port of the pci switch is connected to a PCIe end device (EP). Compared with the PCIe interconnection topology tree, the artificial intelligence processor, the PCIe bridge and the PCIe-SRIO bridge module all belong to PCIe terminal equipment and should be connected to a downstream port of the PCIeSlwitch. All devices connected to the PCIe interconnect topology tree can communicate with each other. Once the artificial intelligence processor has access to the PCIe topology tree, its intelligent computing resources may be shared with other port devices.
the sensor is various in types, and the communication interface of the sensor is also various. The sensors of each type may be connected to a PCIe bus via PCIe bridges, thereby indirectly interconnecting the artificial intelligence processor. The function of the PCIe bridge is to mount devices with different types of communication interfaces onto a PCIe bus, so as to realize conversion between different types of communication protocols and PCIe protocols. Common PCIe bridge modules include PCIe-PCI, PCIe-Ethernet, PCIe-SATA, PCIe-USB, PCIe-m.2, PCIe-UART, PCIe-RS232, PCIe-RS422, PCIe-RS485, PCIe-SPI, PCIe-HDMI, PCIe-VGA, PCIe-CameraLink, etc.
Component 3-PCIe-SRIO bridge Module:
in computing applications, a PCIe bus is often used. For example, an artificial neural network model trains a server to connect multiple artificial intelligence processor boards or GPU graphics cards into a clustered system using PCIe.
In embedded systems, SRIO buses are often used. For example, an aircraft control computer uses an SRIO bus to connect a plurality of sensor modules, a power supply module, a digital signal processing module, a main control module, an execution module, and a security module into a whole system.
Although SRIO and PCIe have similar functionality, the two interconnect technologies have different protocols and require a translation module to pass transactions between them. Therefore, the PCIe-SRIO bridge module is adopted by the invention to carry out necessary conversion on the two interconnection protocols. The PCIe-SRIO bridge module is composed of an SRIO physical layer interface sub-module, an SRIO data packet processing sub-module, a PCIe data packet processing sub-module, and a PCIe physical layer interface sub-module, as shown in fig. 4.
Component 4 — SRIO interconnect topology tree:
the SRIO interconnection topology tree assumes two functional roles: the access and the mutual communication of a plurality of SRIO interface functional modules are realized, and the access of a plurality of SRIO bridge modules (comprising PCIe-SRIO bridge modules and SRIO-other interface conversion modules) is realized. The 'SRIO interface functional module' refers to a functional module which is already provided with an SRIO interface, and has other module units with special functions, not only having a bridging function, but also being a functional module which is already prepared and needs to be interfaced with an artificial intelligence processor. The 'multiple SRIO bridging modules' refer to special modules which are specially used for bridging SRIO interfaces and other types of interfaces, and only have bridging function and no other functions.
As shown in fig. 3, the SRIO interconnection topology tree is mainly constructed by the SRIO switching module. The SRIO switching module consists of several ports. Unlike the pci switch, the ports of the SRIO switch module are equal in status, and do not distinguish between upstream and downstream. If sensor A in FIG. 3 needs to communicate with the artificial intelligence processor, sensor A may establish a communication link through SRIO bridge A, SRIO switch #1, SRIO-PCIe bridge module. If sensor B in FIG. 3 needs to communicate with the artificial intelligence processor, sensor B may establish a communication link through SRIO bridge B, SRIO switch # 2, SRIO switch #1, SRIO-PCIe bridge modules.
Component 5 — SRIO bridge:
the external communication interfaces for different types of sensors are also diverse. The sensors of various types can be connected to the SRIO bus through the SRIO bridge, and then are indirectly interconnected with the artificial intelligence processor through the PCIe-SRIO bridge module in the component 3. The SRIO bridge is used for mounting equipment of different types of communication interfaces to an SRIO bus so as to realize conversion between different types of communication protocols and the SRIO protocol. Common SRIO bridge modules comprise SRIO-PCI, SRIO-Ethernet, SRIO-SATA, SRIO-USB, SRIO-m.2, SRIO-UART, SRIO-RS232, SRIO-RS422, SRIO-RS485, SRIO-SPI, SRIO-HDMI, SRIO-VGA, SRIO-CameraLink, SRIO-optical fiber and the like.
The related products of the invention comprise all chips, circuit boards, interconnection devices and electronic equipment adopting the interconnection method.
In order to make the aforementioned features and effects of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
As shown in fig. 1, a method for interconnecting data of an artificial intelligence processor includes the following main implementation steps:
and (3) link 1: 1 to n artificial intelligence processor subsystems are prepared.
And (2) link: and building a PCIe interconnection topology tree.
Link 2-1: preparing 1 to n PCIeSchwitch submodules and CPU subsystem modules.
And (2) link 2-2: 1 to n pci switch submodules are connected in the manner shown in fig. 2. The upstream port of 2# PCIe Switch is interconnected with the downstream port of 1# PCIeSwitch, the upstream port of 3# PCIeSwitch is interconnected with the downstream port of 2# PCIeSwitch, and so on, the upstream port of n # PCIeSwitch is interconnected with the downstream port of n-1# PCIeSwitch.
And (2) link 2-3: the CPU subsystem is connected to the upstream port of the 1# pcie switch.
And (2) link 2-4: connecting the 1 to n artificial intelligence processor subsystems to the idle downstream ports of the 1 to n # PCIeSlwitch, wherein the numbers do not require one-to-one correspondence, for example, the 1# artificial intelligence processor subsystem can be connected to the idle downstream port of the 1# PCIeSlwitch, the 1# artificial intelligence processor subsystem can also be connected to the idle downstream port of the 2# PCIeSlwitch, and the 1# artificial intelligence processor subsystem can also be connected to the idle downstream port of the n # PCIeSlwitch.
And (3) link: and building a PCIe bridge.
Link 3-1: sensors are prepared that need to be interconnected with an artificial intelligence processor.
And (3) link 3-2: and preparing corresponding PCIe-other interface conversion modules according to different interfaces of the sensors. For example: meanwhile, 2 sensors need to be interconnected with an artificial intelligence processor, a sensor A is an RS232 interface, a sensor B is a hundred-mega Ethernet interface, and a PCIe-RS232 conversion module and a PCIe-hundred-mega Ethernet conversion module need to be prepared.
And (3) link 3-3: the sensors are connected to corresponding PCIe bridge modules, and the PCIe bridge modules are connected to the idle downstream port of any PCIeSlwitch in the PCIe interconnection topology tree. For example: assuming that sensor a is an RS232 interface, sensor a is connected to a PCIe-RS232 conversion module, and the PCIe-RS232 conversion module is connected to the idle downstream port of the 2# PCIe switch, or the PCIe-RS232 conversion module is connected to the idle downstream ports of other number PCIe switches.
And 4, link 4: and building a PCIe-SRIO bridge module. The most common implementation methods of the PCIe-SRIO bridge module include 2, one is to use a dedicated PCIe-SRIO bridge chip, and the other is to use a programmable logic device to implement programming. The use method of the PCIe-SRIO bridging chip and the programming method of the programmable logic device are not described, and the principle design steps of the PCIe-SRIO bridging module are emphasized.
Link 4-1: and establishing an SRIO physical layer interface sub-module. A plurality of physical layer communication channels CH1 through CHn are built up as needed. At present, the PCIe-SRIO bridge chip is supported to 4 x (4 channels) mostly, and the FPGA is supported to 8 x mostly. Theoretically, the SRIO standard can support up to 16 ×. Each lane is called 1 x and contains 1 transmit differential pair and 1 receive differential pair. The present invention supports multiple channels for the following reasons: 1. the performance of the sensor is continuously improved, the generated data volume is exponentially increased, and the number of channels needs to meet the access requirement of larger data in the future; 2. the external interface of the current cambrian artificial intelligence processor is pci ex16, and the bandwidth is about 2.5G 16G 40G. The single-channel bandwidth of the SRIO is usually 3.125G, and at least more than 12 channels are needed to ensure that the communication bandwidth of the SRIO does not become a data access bottleneck of the intelligent processor.
And 4-2: and (5) establishing an SRIO data packet processing sub-module, wherein the connection relation of each functional unit in the sub-module is shown in an attached figure 5.
Link 4-2-1: and establishing an SRIO data packet analysis functional unit. This unit has two functions: one is to analyze and process the SRIO data message; and the other function is to communicate with an external shared memory and temporarily store the SRIO data message.
Link 4-2-2: and establishing an SRIO data packet routing functional unit. The unit is used for ID addressing and distribution path selection of the SRIO data message.
Link 4-2-3: and establishing an SRIO data packet checking functional unit. The unit is used for checking the SRIO data message.
Link 4-2-4: and constructing a data extraction functional unit. The unit is used for receiving the physical layer data stream from the SRIO physical layer interface sub-module and extracting effective data in the SRIO physical layer data stream.
Link 4-2-5: and constructing a data packing functional unit. The unit is used for packaging and packaging SRIO protocol data according to the requirements of an SRIO physical layer and sending the SRIO protocol data to an SRIO physical layer interface sub-module.
And 4-3: and establishing a PCIe data packet processing sub-module. The connection relationship of each functional unit in the sub-module is shown in figure 6.
Link 4-3-1: and establishing a PCIe transaction layer TLP data message processing functional unit. The TLP represents a transaction layer packet (transactionalayerpacket). The function of this unit is two: one is to generate a data message used by the PCIe bus; and the other is communicated with an external shared memory for temporarily storing the TLP.
Link 4-3-2: and establishing a PCIe link layer TLP message receiving and checking functional unit. The function of this unit is two: one is to perform a TLP transceiving process; and the other is to check the TLP.
Link 4-3-3: and establishing a PCIe physical layer byte distribution and merging functional unit. The function of this unit is two: one is to perform byte distribution on the TLP, because the PCIe link may be composed of a plurality of channels, the byte distribution function may distribute the data packet to different channels, and also eliminate a data jitter (Skew) phenomenon that may exist when data is transmitted by different channels; another function is to combine data from different channels and perform a De-jitter (De-skew) operation.
Link 4-3-4: and establishing a PCIe physical layer data stream encoding and decoding functional unit. The function of this unit is to encode and decode the PCIe physical layer data stream.
Link 4-3-5: and establishing a functional unit for scrambling and descrambling the PCIe physical layer data stream. The function of this unit is to scramble and descramble the PCIe physical layer data stream. Scrambling is to send out the source data stream after exclusive-or operation with a random sequence, so as to reduce the electromagnetic interference noise in the sequence.
Link 4-3-6: and establishing a PCIe physical layer data stream serial-parallel conversion functional unit. The unit functions in two ways, one to convert a serial data stream into a parallel data stream and the other to convert a parallel data stream into a serial data stream.
And 4, link 4-4: and establishing a PCIe physical layer interface sub-module. A plurality of physical layer communication channels Lane1 through Lanen are built as needed. At present, the PCIe-SRIO bridge chip is supported to 4 x (4 channels) mostly, and the FPGA is supported to 16 x mostly. Theoretically, the PCIe standard can support up to 32 x. Each lane is called 1 x and contains 1 transmit differential pair and 1 receive differential pair.
And 4-5: a shared memory is constructed. The data temporary storage of the SRIO data packet processing sub-module and the data temporary storage of the PCIe data packet processing sub-module can be realized. The shared memory is used in ping-pong mode between the SRIO data packet processing sub-module and the PCIe data packet processing sub-module, and plays a role in data sharing.
Link 4-5-1: and constructing an on-chip RAM.
Link 4-5-2: an off-chip ddr sdram is constructed. Currently commonly used are DDR3 and DDR 4.
And (5) link: and building an SRIO interconnection topology tree.
Link 5-1: 1 to n SRIO switches are prepared.
And 5-2: connecting 1 to n SRIO switches according to the mode of fig. 3. Because the SRIO switches do not distinguish upstream and downstream ports, the SRIO switches can be arbitrarily interconnected, but cannot form a closed loop.
And 5-3: and connecting the SRIO port of the SRIO-PCIe bridge to a certain idle port of the SRIO switch, thereby establishing an interconnection path of the SRIO interconnection topology tree and the PCIe interconnection topology tree.
And 5-4: and connecting a plurality of functional modules with SRIO interfaces to the idle ports of the SRIO switch. If the function module A is connected to the 1# SRIO switch, the function module B is connected to the 2# SRIO switch.
And 6, link 6: and building an SRIO bridge.
Link 6-1: sensors are prepared that need to be interconnected with an artificial intelligence processor.
And 6-2: and preparing corresponding SRIO-other interface conversion modules according to different interfaces of each sensor. For example: meanwhile, 2 sensors need to be interconnected with an artificial intelligence processor, a sensor A is an RS485 interface, a sensor B is an optical fiber interface, an SRIO bridge A needs to prepare an ASRIO-RS485 conversion module, and an SRIO bridge B needs to prepare an SRIO-optical fiber conversion module.
And 6-3: and connecting the sensor to a corresponding SRIO bridge module, and connecting the SRIO bridge module to an idle port of any SRIO switch in the SRIO interconnection topology tree. For example: if the sensor A is an RS485 interface and the sensor B is an optical fiber interface, the sensor A is connected to the SRIO-RS485 conversion module, the sensor B is connected to the SRIO-optical fiber conversion module, the SRIO-RS485 conversion module is connected to an idle port of the 1# SRIO switch, and the SRIO-optical fiber conversion module is connected to an idle port of the 2# SRIO switch.
Therefore, the design of the artificial intelligence processor data interconnection method is completed, and the interconnection of the sensors with different interface types and the artificial intelligence processor can be realized.
The data interconnection method of the artificial intelligence processor can only comprise the link 1, the link 2 and the link 3, such as communication links a-b-c shown in fig. 1; link 1, link 2, link 4, link 5, link 6, such as the communication link a-d-e-f-g shown in fig. 1, may also be included; it may also include all links from link 1 to link 6, as shown in fig. 1 where communication links a-b-c and communication links a-d-e-f-g are present.
The artificial intelligence processor data interconnection method and the related product provide a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute part or all of the steps of any one of the artificial intelligence processor data interconnection methods as described in the above method embodiments.
The computer program product includes a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the artificial intelligence processor data interconnection methods described in the above method embodiments.
In some embodiments, a chip is disclosed that includes the above-described method for performing an artificial intelligence processor data interconnect.
In some embodiments, a chip package structure is disclosed, which comprises the above chip.
In some embodiments, a circuit board card is disclosed, which includes the above chip packaging structure.
In some embodiments, an electronic device is disclosed, which comprises the above board card. The electronic equipment comprises a data processing device, a robot, a computer, a printer, a scanner, a tablet personal computer, an intelligent terminal, a mobile phone, a vehicle data recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, wearable equipment, a vehicle, household appliances, medical equipment and special equipment.
The following are system examples corresponding to the above method examples, and this embodiment can be implemented in cooperation with the above embodiments. The related technical details mentioned in the above embodiments are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the above-described embodiments.
The invention also provides a data interconnection system for the artificial intelligence processor, which comprises:
the module 1 is connected with a plurality of PCIeSlighs in series to form a PCIe interconnection topological tree, an upstream port of a first PCIeSligh in the PCIe interconnection topological tree is connected with a general processor, and each artificial intelligent processor is connected with a downstream port of one PCIeSligh in the PCIe interconnection topological tree;
the module 2 acquires a first sensor, and connects the first sensor to a downstream port of any PCIeSchw in the PCIe interconnection topology tree through a PCIe bridge;
the module 3 is used for building a PCIe-SRIO bridge module to realize the conversion between an SRIO protocol and a PCIe protocol and connecting a PCIe port of the PCIe-SRIO bridge module to a downstream port of any PCIeSlitch in the PCIe interconnection topological tree;
the module 4 is used for forming an SRIO interconnection topology tree by interconnecting a plurality of SRIO switches, and connecting an SRIO port of the PCIe-SRIO bridging module to the SRIO switches so as to establish an interconnection path between the SRIO interconnection topology tree and the PCIe interconnection topology tree;
the module 5 acquires a second sensor, and connects the second sensor to an idle port of any SRIO switch in the SRIO interconnection topology tree through an SRIO bridge;
the module 6 and the first sensor realize data interconnection with the artificial intelligence processor through the PCIe bridge and the PCIe interconnection topology tree, and the second sensor realizes data interconnection with the artificial intelligence processor through the SRIO bridge, the SRIO interconnection topology tree, the PCIe-SRIO bridge module and the PCIe interconnection topology tree.
In the data interconnection system for the artificial intelligence processor, the PCIe-SRIO bridge module built in the module 3 consists of an SRIO physical layer interface sub-module, an SRIO data packet processing sub-module, a PCIe physical layer interface sub-module, a PCIe data packet processing sub-module and a shared memory;
the SRIO physical layer interface sub-module comprises a plurality of physical layer communication channels, is connected with an idle port of the SRIO switch in the SRIO interconnection topological tree connection and is used for transmitting the SRIO data packet generated by the second sensor;
the SRIO data packet processing submodule is connected with the SRIO physical layer interface submodule and is used for preprocessing the SRIO data packet and storing the preprocessed SRIO data packet into the shared memory;
the PCIe data packet processing submodule is used for acquiring the SRIO data packet from the shared memory, converting the SRIO data packet into a PCIe protocol and recoding the PCIe protocol to obtain a conversion data packet meeting the PCIe protocol, and sending the conversion data packet to a downstream port of any PCIeSlick in the PCIe interconnection topology tree through the PCIe physical layer interface submodule.
The PCIe packet processing sub-module includes a PCIe transaction layer TLP data packet processing function unit, a PCIe link layer TLP transceiving verification function unit, a PCIe physical layer byte distribution merging function unit, a PCIe physical layer data stream coding/decoding function unit, a PCIe physical layer data stream scrambling/descrambling function unit, and a PCIe physical layer data stream serial-parallel conversion function unit.
The data interconnection system for the artificial intelligence processor, wherein the SRIO data packet processing submodule comprises:
the SRIO data packet analysis functional unit is used for analyzing and processing the SRIO data message, communicating with the shared memory and temporarily storing the SRIO data message;
the SRIO data packet routing function unit is used for carrying out ID addressing and distribution path selection on the SRIO data message;
the SRIO data packet checking functional unit is used for checking the SRIO data message;
the data extraction functional unit is used for receiving the physical layer data stream from the SRIO physical layer interface sub-module and extracting effective data in the SRIO physical layer data stream;
the data packing functional unit is constructed and used for packing and packing the SRIO protocol data according to the SRIO physical layer requirement and sending the packed data to an SRIO physical layer interface sub-module;
the PCIe data packet processing submodule comprises:
a PCIe transaction layer TLP data packet processing functional unit, configured to generate a data packet used by a PCIe bus, communicate with the shared memory, and temporarily store the TLP;
a PCIe link layer TLP transceiving and checking functional unit, configured to perform transceiving processing on the TLP and perform checking processing on the TLP;
a PCIe physical layer byte distribution and merging functional unit, configured to perform byte distribution on a TLP, merge data from different channels, and perform a debounce operation;
the PCIe physical layer data stream encoding and decoding functional unit is used for encoding and decoding the PCIe physical layer data stream;
and the PCIe physical layer data stream scrambling and descrambling functional unit is used for scrambling and descrambling the PCIe physical layer data stream.
And the PCIe physical layer data stream serial-parallel conversion functional unit is used for converting the serial data stream into a parallel data stream and converting the parallel data stream into the serial data stream.
The invention also provides a data interconnection chip for the artificial intelligence processor, wherein the data interconnection chip is used for storing a program for executing any data interconnection method.
The invention also provides a data interconnection device for the artificial intelligence processor, which comprises:
the PCIe interconnection topology tree is composed of a plurality of PCIeSlighs connected in series, an upstream port of a first PCIeSligch in the PCIe interconnection topology tree is used for connecting a general processor, and each artificial intelligent processor is connected with a downstream port of one PCIeSligch in the PCIe interconnection topology tree;
the PCIe bridge is used for receiving the sensing data generated by the first sensor and is connected to a downstream port of any PCIeSchw in the PCIe interconnection topology tree;
the PCIe-SRIO bridging module is used for realizing the conversion between an SRIO protocol and a PCIe protocol and connecting a PCIe port of the PCIe-SRIO bridging module to a downstream port of any PCIe Switch in the PCIe interconnection topology tree;
the SRIO interconnection topology tree is composed of a plurality of SRIO switches which are interconnected, and an SRIO port of the PCIe-SRIO bridging module is connected to the SRIO switches so as to establish an interconnection path between the SRIO interconnection topology tree and the PCIe interconnection topology tree;
and the SRIO bridge is used for receiving the sensing data generated by the second sensor and is connected to the idle port of any SRIO switch in the SRIO interconnection topology tree.
Claims (9)
1. A method of data interconnection for an artificial intelligence processor, comprising:
step 1, a PCIe interconnection topology tree is formed by connecting a plurality of PCIe switches in series, an upstream port of a first PCIe Switch in the PCIe interconnection topology tree is connected with a general processor, and each artificial intelligence processor is connected with a downstream port of one PCIe Switch in the PCIe interconnection topology tree;
step 2, acquiring a first sensor, and connecting the first sensor to a downstream port of any PCIe Switch in the PCIe interconnection topology tree through a PCIe bridge;
step 3, building a PCIe-SRIO bridging module to realize the conversion between the SRIO protocol and the PCIe protocol, and connecting a PCIe port of the PCIe-SRIO bridging module to a downstream port of any PCIe Switch in the PCIe interconnection topology tree;
step 4, forming an SRIO interconnection topology tree by interconnecting a plurality of SRIO switches, and connecting an SRIO port of the PCIe-SRIO bridging module to the SRIO switches so as to establish an interconnection path between the SRIO interconnection topology tree and the PCIe interconnection topology tree;
step 5, acquiring a second sensor, and connecting the second sensor to an idle port of any SRIO switch in the SRIO interconnection topology tree through an SRIO bridge;
step 6, the first sensor realizes data interconnection with the artificial intelligence processor through the PCIe bridge and the PCIe interconnection topology tree, and the second sensor realizes data interconnection with the artificial intelligence processor through the SRIO bridge, the SRIO interconnection topology tree, the PCIe-SRIO bridge module and the PCIe interconnection topology tree;
wherein the SRIO interconnection topology tree comprises: the SRIO switches are connected in series through an SRIO bus, and each SRIO switch is connected with an SRIO bridge through the SRIO bus; the second sensor is connected through the SRIO bridge.
2. The data interconnection method for an artificial intelligence processor of claim 1, wherein the PCIe-SRIO bridge module built in step 3 is composed of an SRIO physical layer interface sub-module, an SRIO packet processing sub-module, a PCIe physical layer interface sub-module, a PCIe packet processing sub-module, and a shared memory;
the SRIO physical layer interface sub-module comprises a plurality of physical layer communication channels, is connected with an idle port of an SRIO switch in the SRIO interconnection topological tree and is used for transmitting an SRIO data packet generated by the second sensor;
the SRIO data packet processing submodule is connected with the SRIO physical layer interface submodule and is used for preprocessing the SRIO data packet and storing the preprocessed SRIO data packet into the shared memory;
the PCIe data packet processing submodule is used for acquiring the SRIO data packet from the shared memory, converting the SRIO data packet into a PCIe protocol for recoding to obtain a conversion data packet meeting the PCIe protocol, and sending the conversion data packet to a downstream port of any PCIe Switch in the PCIe interconnection topology tree through the PCIe physical layer interface submodule.
3. The data interconnection method for an artificial intelligence processor of claim 2, wherein the PCIe packet processing sub-module comprises a PCIe transaction layer TLP data packet processing functional unit, a PCIe link layer TLP transceiving check functional unit, a PCIe physical layer byte distribution merging functional unit, a PCIe physical layer data stream coding and decoding functional unit, a PCIe physical layer data stream scrambling and descrambling functional unit, and a PCIe physical layer data stream deserializing functional unit.
4. The data interconnection method for an artificial intelligence processor of claim 3, wherein the SRIO packet processing submodule comprises:
the SRIO data packet analyzing functional unit is used for analyzing and processing the SRIO data packet, communicating with the shared memory and temporarily storing the SRIO data packet;
the SRIO data packet routing function unit is used for carrying out ID addressing and distribution path selection on the SRIO data packet;
the SRIO data packet checking functional unit is used for checking the SRIO data packet;
the data extraction functional unit is used for receiving the physical layer data stream from the SRIO physical layer interface sub-module and extracting effective data in the SRIO physical layer data stream;
the data packing functional unit is constructed and used for packing and packing the SRIO protocol data according to the SRIO physical layer requirement and sending the packed data to an SRIO physical layer interface sub-module;
the PCIe data packet processing submodule comprises:
a PCIe transaction layer TLP data packet processing functional unit, configured to generate a data packet used by a PCIe bus, communicate with the shared memory, and temporarily store the TLP;
a PCIe link layer TLP transceiving and checking functional unit, configured to perform transceiving processing on the TLP and perform checking processing on the TLP;
a PCIe physical layer byte distribution and merging functional unit, configured to perform byte distribution on a TLP, merge data from different channels, and perform a debounce operation;
the PCIe physical layer data stream coding and decoding function unit is used for coding and decoding the PCIe physical layer data stream;
the PCIe physical layer data stream scrambling and descrambling functional unit is used for scrambling and descrambling the PCIe physical layer data stream;
and the PCIe physical layer data stream serial-parallel conversion functional unit is used for converting the serial data stream into a parallel data stream and converting the parallel data stream into the serial data stream.
5. A data interconnection system for an artificial intelligence processor, comprising:
the module 1 is used for forming a PCIe interconnection topology tree by connecting a plurality of PCIe switches in series, wherein an upstream port of a first PCIe Switch in the PCIe interconnection topology tree is connected with a general processor, and each artificial intelligence processor is connected with a downstream port of one PCIe Switch in the PCIe interconnection topology tree;
the module 2 is used for acquiring a first sensor and connecting the first sensor to a downstream port of any PCIe Switch in the PCIe interconnection topology tree through a PCIe bridge;
the module 3 is used for constructing a PCIe-SRIO bridge module so as to realize the conversion between an SRIO protocol and a PCIe protocol, and connecting a PCIe port of the PCIe-SRIO bridge module to a downstream port of any PCIe Switch in the PCIe interconnection topology tree;
the module 4 is used for forming an SRIO interconnection topology tree by interconnecting a plurality of SRIO switches, and connecting an SRIO port of the PCIe-SRIO bridging module to the SRIO switches so as to establish an interconnection path between the SRIO interconnection topology tree and the PCIe interconnection topology tree;
the module 5 is used for acquiring a second sensor and connecting the second sensor to an idle port of any SRIO switch in the SRIO interconnection topology tree through an SRIO bridge;
the second sensor realizes data interconnection with the artificial intelligent processor through the SRIO bridge, the SRIO interconnection topology tree, the PCIe-SRIO bridge module and the PCIe interconnection topology tree;
and the SRIO interconnection topology tree includes: the SRIO switches are connected in series through an SRIO bus, and each SRIO switch is connected with an SRIO bridge through the SRIO bus; the second sensor is connected through the SRIO bridge.
6. The data interconnection system for artificial intelligence processor of claim 5, wherein the PCIe-SRIO bridge module built in module 3 is composed of SRIO physical layer interface sub-module, SRIO packet processing sub-module, PCIe physical layer interface sub-module, PCIe packet processing sub-module and shared memory;
the SRIO physical layer interface sub-module comprises a plurality of physical layer communication channels, is connected with an idle port of an SRIO switch in the SRIO interconnection topological tree and is used for transmitting an SRIO data packet generated by the second sensor;
the SRIO data packet processing submodule is connected with the SRIO physical layer interface submodule and is used for preprocessing the SRIO data packet and storing the preprocessed SRIO data packet into the shared memory;
the PCIe data packet processing submodule is used for acquiring the SRIO data packet from the shared memory, converting the SRIO data packet into a PCIe protocol for recoding to obtain a conversion data packet meeting the PCIe protocol, and sending the conversion data packet to a downstream port of any PCIe Switch in the PCIe interconnection topology tree through the PCIe physical layer interface submodule.
7. The data interconnect system for the artificial intelligence processor of claim 6, wherein the PCIe packet processing sub-module comprises a PCIe transaction layer TLP data packet processing functional unit, a PCIe link layer TLP transceiving check functional unit, a PCIe physical layer byte distribution merging functional unit, a PCIe physical layer data stream coding and decoding functional unit, a PCIe physical layer data stream scrambling and descrambling functional unit, and a PCIe physical layer data stream deserializing functional unit.
8. The data interconnect system for an artificial intelligence processor of claim 7, wherein the SRIO packet processing submodule includes:
the SRIO data packet analyzing functional unit is used for analyzing and processing the SRIO data packet, communicating with the shared memory and temporarily storing the SRIO data packet;
the SRIO data packet routing function unit is used for carrying out ID addressing and distribution path selection on the SRIO data packet;
the SRIO data packet checking functional unit is used for checking the SRIO data packet;
the data extraction functional unit is used for receiving the physical layer data stream from the SRIO physical layer interface sub-module and extracting effective data in the SRIO physical layer data stream;
the data packing functional unit is constructed and used for packing and packing the SRIO protocol data according to the SRIO physical layer requirement and sending the packed data to an SRIO physical layer interface sub-module;
the PCIe data packet processing submodule comprises:
a PCIe transaction layer TLP data packet processing functional unit, configured to generate a data packet used by a PCIe bus, communicate with the shared memory, and temporarily store the TLP;
a PCIe link layer TLP transceiving and checking functional unit, configured to perform transceiving processing on the TLP and perform checking processing on the TLP;
a PCIe physical layer byte distribution and merging functional unit, configured to perform byte distribution on a TLP, merge data from different channels, and perform a debounce operation;
the PCIe physical layer data stream coding and decoding function unit is used for coding and decoding the PCIe physical layer data stream;
the PCIe physical layer data stream scrambling and descrambling functional unit is used for scrambling and descrambling the PCIe physical layer data stream;
and the PCIe physical layer data stream serial-parallel conversion functional unit is used for converting the serial data stream into a parallel data stream and converting the parallel data stream into the serial data stream.
9. A data interconnection apparatus for an artificial intelligence processor, comprising:
the system comprises a PCIe interconnection topology tree and a plurality of PCIe switches, wherein the PCIe interconnection topology tree is composed of a plurality of PCIe switches connected in series, an upstream port of the first PCIe Switch in the PCIe interconnection topology tree is used for connecting a general processor, and each artificial intelligence processor is connected with a downstream port of one PCIe Switch in the PCIe interconnection topology tree;
the PCIe bridge is used for receiving the sensing data generated by the first sensor and is connected to a downstream port of any PCIe Switch in the PCIe interconnection topology tree;
the PCIe-SRIO bridging module is used for realizing the conversion between an SRIO protocol and a PCIe protocol and connecting a PCIe port of the PCIe-SRIO bridging module to a downstream port of any PCIe Switch in the PCIe interconnection topology tree;
the SRIO interconnection topology tree is composed of a plurality of SRIO switches which are interconnected, and an SRIO port of the PCIe-SRIO bridging module is connected to the SRIO switches so as to establish an interconnection path between the SRIO interconnection topology tree and the PCIe interconnection topology tree;
and the SRIO bridge is used for receiving the sensing data generated by the second sensor and is connected to the idle port of any SRIO switch in the SRIO interconnection topology tree.
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