CN103247570A - Manufacturing method for silicon through holes and silicon through hole interconnection - Google Patents
Manufacturing method for silicon through holes and silicon through hole interconnection Download PDFInfo
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- CN103247570A CN103247570A CN2013101748195A CN201310174819A CN103247570A CN 103247570 A CN103247570 A CN 103247570A CN 2013101748195 A CN2013101748195 A CN 2013101748195A CN 201310174819 A CN201310174819 A CN 201310174819A CN 103247570 A CN103247570 A CN 103247570A
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Abstract
The invention discloses a manufacturing method for silicon through holes and a silicon through hole interconnection. The method comprises the following steps: first, bonding a plurality of silicon substrates in a laminating manner as a whole through a hot-press method, manufacturing a graph needed in forming through holes in one side surface of the laminated silicon substrates, machine-forming through holes, carrying out metallization filling in the through holes, carrying out debonding process on the silicon substrates after the metallization filling is finished, and finishing the split of the silicon substrates. Through the adoption of the structure that the silicon substrates are laminated and meanwhile the through holes are processed in the silicon substrates, the method has the advantages that the through holes are formed in the silicon substrates in one time, so that the working efficiency is higher; the aim of carrying out metallization filling simultaneously on the silicon substrates is realized through carrying out metallization filling in the through holes of the laminated silicon substrates; the manufacture time of the silicon through holes and the silicon through hole interconnection is greatly reduced; and meanwhile the processing and the manufacturing cost are reduced to a large extent.
Description
Technical field
The invention belongs to the microelectronic packaging technology field, be specifically related to a kind of method of silicon through hole and manufacture method of interconnecting silicon through holes of making.
Background technology
Along with people to the requirement of the electronic product development to directions such as miniaturization, multi-functional, environment-friendly types, people make great efforts to seek to do electronic system more little, integrated level is more and more higher, function does more and more, more and more stronger.
Three-dimensional packaging technology refers under the prerequisite that does not change package body sizes, stacks the encapsulation technology of two above chips in same packaging body in vertical direction.And silicon perforation (Through Silicon Via is called for short TSV, the silicon through hole) is to realize one of key technology in the three-dimension packaging.This can realize the total silicon encapsulation owing to the silicon through hole with respect to traditional interconnection mode, and is compatible mutually with semiconductor CMOS technology, but and equal proportion increase density of components, reduce the interconnect delay problem, realize high-speed interconnect.
The advantage that the silicon chip through hole is compared to common substrate is: 1) the silicon chip through-hole aperture is much smaller than the printed circuit board through-hole aperture; 2) depth-to-width ratio of silicon chip through hole is much larger than the depth-to-width ratio of printed circuit board through-hole; 3) density of silicon chip through hole is much larger than the density of printed circuit board through-hole.Based on above characteristics, so its development of studying MEMS and semiconductor technology plays an important role.
The manufacture craft of conventional one-piece silicon chip TSV pore-forming comprises: 1) ultrasonic drilling; 2) sand-blast; 3) wet etching; 4) dry etching; 5) laser ablation; 6) machine drilling.
But, because the technology that adopts all is based on the single piece of silicon substrate, also there is influence in the price of final products, even still there are problems in a lot of technology, wherein to make be a crucial difficult problem to the through hole of high, dark, wide ratio.Reliability consideration to through hole is still continuing.Make through hole for the single piece of silicon substrate, its cost of manufacture height, efficient are low.
Because there is multiple unfavorable factor in the method for these single piece of silicon substrate traditional manufacturing technique, to rate of finished products and the reliability of product and finally go out commodity price and all cause great influence.Various new processes also progressively are suggested and discuss, but these methods all carry out on monolithic manufacture craft basis, have shortcomings such as make efficiency is low, cost height.
Therefore, in view of above problem, be necessary to propose a kind ofly can satisfy the requirement of silicon through hole height, dark, wide ratio by the multilayer silicon chip being carried out simultaneously forming through hole and carrying out through-hole interconnection, improve processing efficient, reduce cost of manufacture.
Summary of the invention
In view of this, the invention provides and a kind ofly can satisfy the requirement of silicon through hole height, dark, wide ratio by the multilayer silicon chip being carried out simultaneously forming through hole and carrying out through-hole interconnection, improve processing efficient, reduce cost of manufacture.
According to a kind of method of making the silicon through hole that purpose of the present invention proposes, concrete steps are as follows:
(1), by hot-press method a plurality of silicon chip laminations are bonded together, the lamination bonding structure that forms the multilayer silicon chip is the lamination silicon chip;
(2), make the required figure of forming through hole on the surface of lamination silicon chip one side;
(3), vertical described lamination silicon chip surface forming through-hole structure on the basis of figure;
(4), the lamination silicon chip torn open bonding handle, make each silicon chip of lamination separate;
(5), the silicon chip that respectively machines is carried out clean, remove the bonding material on silicon chip surface, finally had the silicon chip of through hole.
Preferably, described multilayer silicon chip is realized by polymer poly acid imide, SU8 photoresist, benzocyclobutene or bonding glue bonding.
Preferably, the molding mode of described through hole adopts a kind of in machining, laser processing, sandblast boring or the etching.
Preferably, the mode that the lamination silicon chip is torn bonding open in the step 4 adopts the chemical solution dissolve polymer, or adopts electric spark, line cutting, blade cuts mode to split.
A kind of manufacture method of interconnecting silicon through holes, concrete steps are as follows:
(1), by hot-press method a plurality of silicon chip laminations are bonded together, the lamination bonding structure that forms the multilayer silicon chip is the lamination silicon chip;
(2), make the required figure of forming through hole on the surface of lamination silicon chip one side;
(3), vertical described lamination silicon chip surface forming through-hole structure on the basis of figure;
(4), dielectric layer deposited on the madial wall of through hole;
(5), adopt the mode of physical sedimentation or chemical precipitation to make adhesion layer on the basis of dielectric layer;
(6), the filling of metallizing in the through hole to the lamination silicon chip;
(7), the lamination silicon chip torn open bonding handle, make each silicon chip of lamination separate;
(8), the silicon chip that respectively machines is cleaned, remove the bonding material on silicon chip surface, and adopt the mode of surfacing polishing that silicon chip is thinned to desired thickness, obtain final silicon chip.
Preferably, described adhesive layer material is one or more among Ni, Ta, Ti, Pt, Pd, AlN, the TiN.
Preferably, the metallization of described lamination silicon chip through hole filling realizes by the mode of plating, chemical plating, physical deposition or liquid metal filling.
Preferably, before step 4, also comprise the step that the surface of lamination silicon chip with through-hole structure is cleaned, remove the impurity on lamination silicon chip surface.
Preferably, metallization is filled and is adopted plating mode to carry out in the described step 6, also is included in the step of the surface deposition Seed Layer of adhesion layer before step 6, prepares for plating mode metallizes to fill.
Preferably, before step 7, also comprise the step that adopts mode chemical, mechanical polishing to remove metallization filling back lamination silicon chip surface metal.
Compared with prior art, the advantage of the method for making silicon through hole disclosed by the invention and the manufacture method of interconnecting silicon through holes is: by will simultaneously it being carried out through hole processing behind the multilayer silicon chip lamination, once can be to multilayer silicon chip forming through hole, by the filling of in the through hole of lamination silicon chip, metallizing, realize carrying out simultaneously the metal filled purpose of a plurality of silicon chips, shortened the Production Time of silicon through hole and interconnecting silicon through holes greatly, increase work efficiency, reduced the processing cost simultaneously significantly.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the bonding step in the manufacture method of the method for making silicon through hole disclosed by the invention and interconnecting silicon through holes.
Fig. 2 is the forming through hole step in the manufacture method of the method for making silicon through hole disclosed by the invention and interconnecting silicon through holes.
Fig. 3 is for tearing the bonding step open in the method for making silicon through hole disclosed by the invention.
Fig. 4 is the silicon chip finished product that is manufactured with the silicon through hole disclosed by the invention.
Fig. 5 is the step of making adhesion layer in the manufacture method of interconnecting silicon through holes disclosed by the invention.
Fig. 6 is the step that metallizes and fill in the manufacture method of interconnecting silicon through holes disclosed by the invention.
The step of Fig. 7 for tearing bonding open in the manufacture method of interconnecting silicon through holes disclosed by the invention.
Fig. 8 is the open silicon chip interconnection of the present invention finished product.
The title of the numeral among the figure or the corresponding component of alphabetical representative:
1, silicon chip 2, bonded layer 3, through hole 4, Cutting Road 5, adhesion layer 6, filling metal
Embodiment
The processing technology that traditional silicon chip through hole adopts all is based on the single piece of silicon substrate, and its cost of manufacture height, efficient are low; And because there is multiple unfavorable factor in the method for these single piece of silicon substrate traditional manufacturing technique, to rate of finished products and the reliability of product and finally go out commodity price and all cause great influence.
The present invention is directed to deficiency of the prior art, providing a kind of can satisfy the requirement of silicon through hole height, dark, wide ratio by simultaneously the multilayer silicon chip being carried out forming through hole, improves processing efficient, reduces cost of manufacture.
To be clearly and completely described technical scheme of the present invention by embodiment below.Obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Please in the lump referring to Fig. 1-Fig. 4, Fig. 1 is the bonding step in the manufacture method of the method for making silicon through hole disclosed by the invention and interconnecting silicon through holes.Fig. 2 is the forming through hole step in the manufacture method of the method for making silicon through hole disclosed by the invention and interconnecting silicon through holes.Fig. 3 is for tearing the bonding step open in the method for making silicon through hole disclosed by the invention.Fig. 4 is the silicon chip finished product that is manufactured with the silicon through hole disclosed by the invention.As shown in the figure,
A kind of method of making the silicon through hole, concrete steps are as follows:
(1), by hot-press method a plurality of silicon chip 1 laminations are bonded together, the lamination bonding structure that forms the multilayer silicon chip is the lamination silicon chip; The multilayer silicon chip is realized by bonded layer 2 bondings that the polymer poly acid imide forms.Wherein silicon chip is the silicon of 200um.
(2), make the required figure of forming through hole on the surface of lamination silicon chip one side, specifically adopt mode such as photoetching to realize.
(3), vertical stack silicon chip surface forming through hole 3 structures on the basis of figure; The molding mode of through hole 3 adopts a kind of in machining, laser processing, sandblast boring or the etching.
(4), the lamination silicon chip torn open bonding handle, make each silicon chip of lamination separate; The mode of tearing bonding open adopts chemical solution dissolving polyimides, or adopts electric spark, line cutting, blade cuts mode etc. to split, and forms Cutting Road 4, splits each silicon chip along Cutting Road 4.
(5), the silicon chip that respectively machines is carried out clean, remove the bonding material on silicon chip surface, finally had the silicon chip of through hole, so that the technology of follow-up making interconnection.
The pore diameter range of through hole 3 is 5um-500um, and the aperture is less.
A kind of manufacture method of interconnecting silicon through holes, concrete steps are as follows:
(1), by hot-press method a plurality of silicon chip laminations are bonded together, the lamination bonding structure that forms the multilayer silicon chip is the lamination silicon chip; The multilayer silicon chip is realized by bonded layer 2 bondings that the polymer poly acid imide forms.Wherein silicon chip is the silicon of 200um.
(2), make the required figure of forming through hole on the surface of lamination silicon chip one side, specifically adopt mode such as photoetching to realize.
(3), vertical stack silicon chip surface forming through-hole structure on the basis of figure; The molding mode of through hole 3 adopts a kind of in machining, laser processing, sandblast boring or the etching.
Afterwards, also comprise the step that the surface of lamination silicon chip with through-hole structure is cleaned, use SC1(NH
4+ H
2O
2+ H
2O) impurity on removal lamination silicon chip surface makes through hole 3 surface cleanliness be more suitable for the metal deposit.
(4), dielectric layer deposited (not shown) on the madial wall of through hole; Dielectric layer is mainly SiO
2
(5), adopt the mode of physical sedimentation or chemical precipitation to make adhesion layer on the basis of dielectric layer; Adhesive layer material is one or more among Ni, Ta, Ti, Pt, Pd, AlN, the TiN.As adopt the Ti of 200nm.In addition can be at the Cu of surface deposition one deck 1um of adhesion layer as Seed Layer.The purpose of deposit Seed Layer is to prepare for the following adopted plating mode metallizes to fill.
(6), the filling of metallizing in the through hole to the lamination silicon chip; The packing material that metallization is filled is Cu, Sn, W, Ti, Pt, Pd, Ni or Au.The metallization of lamination silicon chip through hole is filled the mode of filling by plating, chemical plating, physical deposition or liquid metal and is realized.
After metal that lamination silicon chip upper surface is unnecessary adopt chemistry or mechanical polishing mode to remove.
(7), the lamination silicon chip torn open bonding handle, make each silicon chip of lamination separate; The mode of tearing bonding open adopts chemical solution dissolving polyimides, or adopts electric spark, line cutting, blade cuts mode etc. to split, and forms Cutting Road 4, splits along Cutting Road 4.
(8), the silicon chip that respectively machines is cleaned, remove the bonding material on silicon chip surface, and adopt the mode of surfacing polishing that silicon chip is thinned to desired thickness.
The multilayer silicon chip also can pass through SU8 photoresist, benzocyclobutene, and ephemeral key rubber alloy or similarly polymer-bound realization specifically do not limit.
In addition, the lamination silicon chip can be 10 layers at most.
The invention discloses a kind of method of silicon through hole and manufacture method of interconnecting silicon through holes of making, by will behind the multilayer silicon chip lamination it being carried out through hole processing, moulding multilayer silicon chip simultaneously once, by the filling of in the through hole of lamination silicon chip, metallizing, realize carrying out simultaneously the metal filled purpose of a plurality of silicon chips, shorten the Production Time of silicon through hole and interconnecting silicon through holes greatly, increased work efficiency, reduced the processing cost simultaneously significantly.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments herein.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the wideest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. method of making the silicon through hole is characterized in that concrete steps are as follows:
(1), by hot-press method a plurality of silicon chip laminations are bonded together, the lamination bonding structure that forms the multilayer silicon chip is the lamination silicon chip;
(2), make the required figure of forming through hole on the surface of lamination silicon chip one side;
(3), vertical described lamination silicon chip surface forming through-hole structure on the basis of figure;
(4), the lamination silicon chip torn open bonding handle, make each silicon chip of lamination separate;
(5), the silicon chip that respectively machines is carried out clean, remove the bonding material on silicon chip surface, finally had the silicon chip of through hole.
2. the method for making silicon through hole as claimed in claim 1 is characterized in that, described multilayer silicon chip is realized by polymer poly acid imide, SU8 photoresist, benzocyclobutene or bonding glue bonding.
3. the method for making silicon through hole as claimed in claim 1 is characterized in that, the molding mode of described through hole adopts a kind of in machining, laser processing, sandblast boring or the etching.
4. the method for making silicon through hole as claimed in claim 1 is characterized in that, the mode that the lamination silicon chip is torn bonding open in the step 4 adopts the chemical solution dissolve polymer, or adopts electric spark, line cutting, blade cuts mode to split.
5. the manufacture method of an interconnecting silicon through holes is characterized in that, concrete steps are as follows:
(1), by hot-press method a plurality of silicon chip laminations are bonded together, the lamination bonding structure that forms the multilayer silicon chip is the lamination silicon chip;
(2), make the required figure of forming through hole on the surface of lamination silicon chip one side;
(3), vertical described lamination silicon chip surface forming through-hole structure on the basis of figure;
(4), dielectric layer deposited on the madial wall of through hole;
(5), adopt the mode of physical sedimentation or chemical precipitation to make adhesion layer on the basis of dielectric layer;
(6), the filling of metallizing in the through hole to the lamination silicon chip;
(7), the lamination silicon chip torn open bonding handle, make each silicon chip of lamination separate;
(8), the silicon chip that respectively machines is cleaned, remove the bonding material on silicon chip surface, and adopt the mode of surfacing polishing that silicon chip is thinned to desired thickness, obtain final silicon chip.
6. the manufacture method of interconnecting silicon through holes as claimed in claim 5 is characterized in that, described adhesive layer material is one or more among Ni, Ta, Ti, Pt, Pd, AlN, the TiN.
7. the manufacture method of interconnecting silicon through holes as claimed in claim 5 is characterized in that, the metallization of described lamination silicon chip through hole is filled the mode of filling by plating, chemical plating, physical deposition or liquid metal and realized.
8. the manufacture method of interconnecting silicon through holes as claimed in claim 5 is characterized in that, also comprises the step that the surface of lamination silicon chip with through-hole structure is cleaned before step 4, removes the impurity on lamination silicon chip surface.
9. the manufacture method of interconnecting silicon through holes as claimed in claim 5, it is characterized in that, metallization is filled and is adopted plating mode to carry out in the described step 6, also is included in the step of the surface deposition Seed Layer of adhesion layer before step 6, prepares for plating mode metallizes to fill.
10. the manufacture method of interconnecting silicon through holes as claimed in claim 5 is characterized in that, also comprises adopting mode chemical, mechanical polishing to remove the step that back lamination silicon chip surface metal is filled in metallization before step 7.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108896104A (en) * | 2018-05-23 | 2018-11-27 | 浙江大学 | Pressure and temperature sensor based on wafer bonding and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010057339A1 (en) * | 2008-11-19 | 2010-05-27 | Hong Kong Applied Science and Technology Research Institute Co. Ltd | Semiconductor chip with through-silicon-via and sidewall pad |
| CN102820262A (en) * | 2012-09-05 | 2012-12-12 | 江苏物联网研究发展中心 | Glass through hole manufacturing and interconnecting method |
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- 2013-05-10 CN CN2013101748195A patent/CN103247570A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010057339A1 (en) * | 2008-11-19 | 2010-05-27 | Hong Kong Applied Science and Technology Research Institute Co. Ltd | Semiconductor chip with through-silicon-via and sidewall pad |
| CN102820262A (en) * | 2012-09-05 | 2012-12-12 | 江苏物联网研究发展中心 | Glass through hole manufacturing and interconnecting method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108896104A (en) * | 2018-05-23 | 2018-11-27 | 浙江大学 | Pressure and temperature sensor based on wafer bonding and preparation method thereof |
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Application publication date: 20130814 |