CN103236437A - High-reliability N-type transverse insulated gate bipolar device and preparation process thereof - Google Patents

High-reliability N-type transverse insulated gate bipolar device and preparation process thereof Download PDF

Info

Publication number
CN103236437A
CN103236437A CN2013101489595A CN201310148959A CN103236437A CN 103236437 A CN103236437 A CN 103236437A CN 2013101489595 A CN2013101489595 A CN 2013101489595A CN 201310148959 A CN201310148959 A CN 201310148959A CN 103236437 A CN103236437 A CN 103236437A
Authority
CN
China
Prior art keywords
type
trap
layer
field oxide
tagma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2013101489595A
Other languages
Chinese (zh)
Other versions
CN103236437B (en
Inventor
刘斯扬
于朝辉
于冰
张春伟
孙伟锋
陆生礼
时龙兴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Southeast University
Original Assignee
Southeast University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Southeast University filed Critical Southeast University
Priority to CN201310148959.5A priority Critical patent/CN103236437B/en
Publication of CN103236437A publication Critical patent/CN103236437A/en
Application granted granted Critical
Publication of CN103236437B publication Critical patent/CN103236437B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

The invention relates to a high-reliability N-type transverse insulated gate bipolar device and a preparation process thereof. The high-reliability N-type transverse insulated gate bipolar device comprises a P-type substrate. Buried oxides are arranged on the P-type substrate. An N-type well is arranged on the buried oxides. An N-type buffer well and a P-type body region are arranged in the N-type well. A P-type anode region is arranged in the N-type buffer well. An N-type cathode region and a P-type body contact region are arranged in the P-type body region. A field oxidation layer is arranged on the surface of the N-type well. A polycrystalline silicon gate is arranged on the surface of the P-type body region. Passivation layers are respectively arranged on the surfaces of the field oxidation layer, the P-type body contact region, the N-type cathode region, the polycrystalline silicon gate and the P-type anode region. The high-reliability N-type transverse insulated gate bipolar device is characterized in that the thickness of the field oxidation layer which is embedded in the N-type well accounts for 60-80 percent of total thickness and the ratio of the thickness of the part exposed out of the N-type well of the field oxidation layer to the thickness of the part embedded in the N-type well of the field oxidation layer is enabled to be 2:3 to 1:4. Therefore, the electric field intensity and the impact ionization rate at the bird's beak of the device are obviously weakened and the reliability of the device is greatly improved.

Description

A kind of N-type lateral insulated gate bipolar device and preparation technology thereof of high reliability
Technical field
The present invention relates generally to field of high voltage power semiconductor devices, specifically, be a kind of N-type lateral insulated gate bipolar device and preparation technology thereof with high reliability, be applicable to that plasma flat-plate display device, half-bridge drive circuit and automobile production field etc. drive chip.
Background technology
Along with the development of high voltage integrated circuit is more and more rapider, technology is also improving constantly, landscape insulation bar double-pole-type transistor (Lateral Insulated Gate Bipolar Transistor under these circumstances, LIGBT) come out, the working mechanism that it is unique, be the working mechanism that the MOS device combines with bipolar device, reduced conducting resistance to a great extent, improved the performance of device and circuit greatly.Because the LIGBT device is operated under the environment of high voltage, big electric current, thereby is faced with very severe integrity problem.The channel region of LIGBT device is terminal near the risk that produces high field intensity is also arranged near the drift region, and then causes hot carrier's effect and the degeneration of device produced and have a strong impact on, and in addition puncture voltage is also had serious restriction.Therefore, probe into its operating characteristic and improve device reliability as far as possible the application of LIGBT is had very important meaning.
With the CMOS process compatible and do not increase on the basis of technology cost and improve device reliability more significantly, be the key problem that high-performance LIGBT preparation technology will solve how.Because oxygen is at SiO 2In diffusion coefficient limited, oxidation rate can be reduced to zero gradually along with the increase of oxidated layer thickness, thereby finish the growth of oxide layer, there is an extreme value in the consumption of silicon when making the growth oxide layer, and the consumption of general silicon approximately is 44% of final oxidated layer thickness.In common LIGBT preparation technology, device only needs the primary field oxide layer growth, makes that like this thickness proportion of the field oxide part of exposing the N-type trap and the part that embeds the N-type trap is about 5:4.The electric field line of device beak below in this case is intensive, and electric field strength is big, and impact ionization rate is remarkable, and device reliability is unsatisfactory.The common process basic step of preparation LIGBT device is as follows:
Step 1 is with P type substrate and P type silicon layer bonding; Annealing strengthens the bonding dynamics of two disks; By grinding, polish attenuate P type silicon layer to designed thickness;
Step 2 is injected phosphorus impurities at P type silicon layer, advances by high temperature to form the N-type trap; Inject boron and form P type tagma, inject phosphorus then and form N-type buffering trap;
Step 3, the sacrificial oxide layer of growth 45 ~ 55 nanometers, and the silicon nitride of deposit 140 ~ 160 nanometers, the silicon nitride of photoetching, development and top, etching field oxide zone; At 950 ℃, O 2And H 2The ratio of volume content is growth field oxide 70 minutes in the atmosphere of 7:13, and then at 950 ℃, O 2With the ratio of HCL volume content be growth field oxide 20 minutes in the atmosphere of 16:0.32, then finish the growth of field oxide;
Step 4, growth gate oxide and deposit polysilicon gate;
Step 5 is injected phosphorus and arsenic and is formed the N-type cathodic region; Inject boron fluoride and boron and form p type anode district and P type body contact zone; Annealing activator impurity ion;
Step 6, passivation, etching oxidation layer form contact hole; Metal level deposit, photoetching, etching form the first metal layer and second metal level.
Summary of the invention
The invention provides a kind of N-type lateral insulated gate bipolar device and preparation technology thereof of high reliability, the present invention can improve the reliability of electrology characteristic and the device of N-type lateral insulated gate bipolar device.
The present invention adopts following technical scheme: a kind of N-type landscape insulation bar double-pole-type transistor of high reliability, comprise: P type substrate, be provided with at P type substrate and bury oxygen, be provided with the N-type trap burying oxygen, be provided with N-type buffering trap and P type tagma in the inside of N-type trap, in N-type buffering trap, be provided with the p type anode district, in P type tagma, be provided with N-type cathodic region and P type body contact zone, an end that is provided with field oxide and field oxide on the surface of N-type trap extends to the p type anode district and terminates in the p type anode district, the other end is to the extension of P type tagma and terminate in P type tagma front end, be provided with the part upper surface that polysilicon gate and polysilicon gate extend to field oxide on the surface in P type tagma, at field oxide, P type body contact zone, the N-type cathodic region, the surface in polysilicon gate and p type anode district is provided with passivation layer, be connected with the first metal layer on surface, p type anode district, be connected with second metal level in P type body contact zone and surface, N-type cathodic region.
The preparation method of the N-type lateral insulated gate bipolar device of described high reliability:
Step 1, getting two resistivity is that 25 Ω cm thickness are 500 ~ 600 microns P type silicon layer, every P type silicon layer difference oxidation growth oxide layer; With two P type silicon layer bondings, form oxygen buried layer under 15 ℃ ~ 35 ℃, annealing strengthens the bonding dynamics of two disks; By grind, polishing and corrosion come skiving one side P type silicon layer to 6 ~ 7 microns, be to form the N-type trap to do the basis, opposite side P type silicon layer is directly made P type substrate;
Step 2 is 2.5e12 cm at 6 ~ 7 microns P type silicon layer implantation dosages -2, energy is the phosphorus impurities of 120Kev, advance down at 1150 ℃ to form the N-type traps; Photoetching is developed and is determined doped region, and implantation dosage is 5e13 cm -2, energy is that the boron of 120Kev forms P type tagma, implantation dosage is 1.8e13 cm then -2, energy is that the phosphorus of 140Kev forms N-type buffering trap;
Step 3, first sacrificial oxide layer of 45 ~ 55 nanometers of above N-type buffering trap, N-type trap and P type tagma, growing, and first silicon nitride of deposit 140 ~ 160 nanometers, first silicon nitride is carried out photoetching, develops and etching, one end of etch areas is positioned at N-type buffering trap, and the other end of etch areas and P type tagma offset; At 950 ℃, O 2And H 2The ratio of volume content is growth field oxide 70 minutes in the atmosphere of 7:13, and then at 950 ℃, O 2With the ratio of HCL volume content be growth field oxide 20 minutes in the atmosphere of 16:0.32, form the transition field oxide in etch areas; With first silicon nitride and the remaining whole etchings of first sacrificial oxide layer of transition field oxide, remnants, form grooves 6 ~ 7 microns P type silicon surface again;
Step 4, second sacrificial oxide layer of 45 ~ 55 nanometers of above N-type buffering trap, N-type trap and P type tagma, growing, and second silicon nitride of deposit 140 ~ 160 nanometers, photoetching, also second silicon nitride of etched recesses top that develops expose the groove that etches in the previous step; At 950 ℃, O 2And H 2The ratio of volume content is growth field oxide 70 minutes in the atmosphere of 7:13, and then at 950 ℃, O 2With the ratio of HCL volume content be growth field oxide 20 minutes in the atmosphere of 16:0.32, in groove, form field oxide; Second silicon nitride and the remaining whole etchings of second sacrificial oxide layer with remnants;
Step 5, the gate oxide of growth 23 ~ 27 nanometers, under 950 ℃ of environment, deposition thickness is that 400 ~ 440 nanometers, resistivity are the polysilicon gate of 6.4e-4 Ω cm then;
Step 6 is selected the ion implanted region territory by mask blank, and implantation dosage is 6e13 cm in P type tagma -2, energy is that phosphorus and the dosage of 50Kev is 5e15 cm -2, energy is the arsenic of 80Kev, forms the N-type cathodic region; Implantation dosage is 5e15 cm in N-type buffering trap -2, energy is that boron fluoride and the dosage of 80Kev is 5e15 cm -2, energy is the boron of 140Kev, forms the p type anode district, implantation dosage is 5e15 cm in P type tagma simultaneously -2, energy is that boron fluoride and the dosage of 80Kev is 5e15 cm -2, energy is the boron of 140Kev, forms P type body contact zone; Annealing activator impurity ion;
Step 7, passivation forms passivation layer, and the etching oxidation layer forms contact hole; Carry out metal deposit, photoetching, etching again, form the first metal layer and second metal level.
Compared with prior art, the present invention has following advantage:
(1), device technology of the present invention, overcome the limit of field oxide 8 embedding N-type traps 3 degree of depth among the general preparation technology (under the general preparation technology, the thickness that field oxide 8 embeds N-type traps 3 account for field oxide 8 gross thickness 44%), the thickness that field oxide 8 embeds N-type trap 3 reaches 60% ~ 80% of field oxide 8 gross thickness, and accompanying drawing 30 can obviously be found out the effect of this technology.
(2), in the device of the present invention, it is darker that field oxide 8 embeds N-type trap 3, insert depth accounts for 60% ~ 80% of whole field oxide thickness, make that the thickness proportion of field oxide 8 part of exposing N-type trap 3 and the part that embeds N-type trap 3 is 2:3 to 1:4, the inversion layer width of positive voltage induction is bigger on the grid, slow down the speed that electric field strength raises with grid voltage, reduced in identical grid voltage lower channel longitudinal electric field intensity simultaneously, improved device ON state, OFF state puncture voltage.From accompanying drawing 33 as can be seen the OFF state puncture voltage of device obviously improve; Accompanying drawing 34 we can say that funerary objects spare ON state puncture voltage also obviously improves.
(3), in the device of the present invention, it is darker that field oxide 8 embeds N-type trap 3, insert depth accounts for 60% ~ 80% of whole field oxide thickness, make that the thickness proportion of field oxide 8 part of exposing N-type trap 3 and the part that embeds N-type trap 3 is 2:3 to 1:4, face south polar region extruding of power line, make that sparse before power line density under the ON state (accompanying drawing 31 is for adopting device electric power line chart behind the present invention, accompanying drawing 32 is for adopting the preceding device electric power line chart of the present invention), thereby electric field strength reduces, reduced the impact ionization rate at beak place simultaneously, hot carrier's effect is eased, has improved the reliability of device.From accompanying drawing 35 as can be seen, beak place (x=13 ~ 15 micron) impact ionization rate obviously reduces, and device reliability is improved.
(4), device of the present invention adopts and to generate field oxide technology twice, this technology easily realizes, and can not increase extra cost.In addition, device making technics of the present invention can with existing CMOS process compatible, be easy to the preparation.
(5), device of the present invention can not only improve reliability effectively, do not become because the device channel region carrier concentration, the length of raceway groove and width and do not become; And gate oxide thickness and growth of gate oxide layer environment do not have change, do not change so the threshold voltage of device almost, and as shown in Figure 36, threshold voltage is all between 0.75 ~ 0.85 volt before and after the device improvements.
Description of drawings
Fig. 1 is the cross-section structure for the N-type lateral insulated gate bipolar device after the present invention's improvement.
Below be the technological process after the device improvements:
Fig. 2 is step 1 (1), namely passes through two P type silicon layers after the thermal oxidation.
Fig. 3 is step 1 (2), i.e. two P type silicon layer bondings.
Fig. 4 is step 1 (3), and namely skiving one side P type silicon layer to 6 ~ 7 microns keeps opposite side P type silicon layer thickness and makes P type substrate.
Fig. 5 is step 2 (1), is about to 6 ~ 7 microns P type silicon layers and injects phosphorus impurities formation N-type trap.
Fig. 6 is step 2 (2), namely injects corresponding impurity and forms P type tagma and N-type buffering trap.
Fig. 7 is step 3 (1), i.e. growth first sacrificial oxide layer above N-type buffering trap, N-type trap and P type tagma, and deposit first silicon nitride.
Fig. 8 is step 3 (2), namely first silicon nitride is carried out photoetching, develops and etching, and an end of etch areas is positioned at N-type buffering trap, and the other end of etch areas and P type tagma offset.
Fig. 9 is step 3 (3), namely at etch areas growth transition field oxide.
Figure 10 is step 3 (4), is about to transition field oxide, remaining first silicon nitride and the whole etchings of remaining first sacrificial oxide layer, obtains groove.
Figure 11 is step 4 (1), i.e. growth second sacrificial oxide layer above N-type buffering trap, groove and P type tagma, and deposit second silicon nitride.
Figure 12 is step 4 (2), i.e. photoetching, also second silicon nitride of etching field groove top that develops expose the groove that etches in the previous step.
Figure 13 is step 4 (3), namely forms field oxide in groove.
Figure 14 is step 4 (4), is about to remaining second silicon nitride and the whole etchings of remaining second sacrificial oxide layer.
Figure 15 is the device complete graph after step 4 is finished.
Figure 16 is step 5 (1), the gate oxide of namely growing.
Figure 17 is step 5 (2), namely clicks polysilicon gate.
Figure 18 is the device complete graph after step 5 is finished.
Figure 19 is step 6, namely forms N-type cathodic region, p type anode district and P type body contact zone.
Figure 20 is step 7, namely forms passivation layer, the first metal layer and second metal level.
Below general preparation technology's flow chart:
Figure 21 is step 1, and namely two P type silicon layers are through thermal oxidation, bonding, again with a P type silicon layer skiving to 6 ~ 7 microns.
Figure 22 is step 2, namely forms N-type trap, P type tagma and N-type buffering trap.
Figure 23 is step 3 (1), namely grow above N-type buffering trap, N-type trap and P type tagma sacrificial oxide layer and deposit silicon nitride.
Figure 24 is step 3 (2), namely silicon nitride is carried out photoetching, develops and etching, and an end of etch areas is positioned at N-type buffering trap, and the other end of etch areas and P type tagma offset.
Figure 25 is step 3 (3), namely at etch areas growth field oxide.
Figure 26 is the device complete graph after step 3 is finished.
Figure 27 is step 4, namely grow gate oxide and deposit polysilicon gate.
Figure 28 is step 5, namely forms N-type cathodic region, p type anode district and P type body contact zone.
Figure 29 is step 6, namely forms passivation layer, the first metal layer and second metal level.
Figure 30 is technology of the present invention and general technology effect contrast figure.
Figure 31 is device electric power line chart after the process modification, is power line density contrast district in the black circles.
Figure 32 is device electric power line chart before the process modification, is power line density contrast district in the black circles, and through comparing Figure 31 and Figure 32, beak below power line density is more sparse than general technology device beak below power line density afterwards can obviously to find out process modification.
Figure 33 is the OFF state anode voltage current curve comparison diagram of device of the present invention and general device, can find out obviously that from figure the puncture voltage of the device after the improvement obviously promotes.
Figure 34 is the ON state anode voltage current curve comparison diagram of device of the present invention and general device, can find out obviously that from figure the puncture voltage of the device after the improvement obviously promotes.
Figure 35 is the comparison diagram of the hot carrier impact ionization rate in device of the present invention and general device surface zone, as can be seen from the figure the impact ionization rate of beak place (x=13 ~ 15 micron) obviously reduces, be that the hot carrier problem improves, the reliability of device is improved.
Figure 36 is the transfer characteristic curve comparison diagram of device of the present invention and general device, can obviously find out from figure, almost not variation of the threshold voltage of device before and after improving.
Embodiment
Below in conjunction with accompanying drawing 2, the present invention is elaborated, a kind of N-type lateral insulated gate bipolar device of high reliability, comprise: P type substrate 1, be provided with at P type substrate 1 and bury oxygen 2, be provided with N-type trap 3 burying oxygen 2, be provided with N-type buffering trap 4 and P type tagma 13 in the inside of N-type trap 3, in N-type buffering trap 4, be provided with p type anode district 5, in P type tagma 13, be provided with N-type cathodic region 12 and P type body contact zone 11, an end that is provided with field oxide 8 and field oxide 8 on the surface of N-type trap 35 extends and terminates in p type anode district 5 to the p type anode district, the other end 13 extends and terminates in P type tagma 13 front ends to P type tagma, be provided with the part upper surface that polysilicon gate 9 and polysilicon gate 9 extend to field oxide 8 on the surface in P type tagma 13, at field oxide 8, P type body contact zone 11, N-type cathodic region 12, the surface in polysilicon gate 9 and p type anode district 5 is provided with passivation layer 7, be connected with the first metal layer 6 on 5 surfaces, p type anode district, be connected with second metal level 10 in P type body contact zone 11 and 12 surfaces, N-type cathodic region.
Make the N-type lateral insulated gate bipolar device of aforesaid high reliability, concrete steps are as follows:
Step 1, getting two resistivity is that 25 Ω cm thickness are 500 ~ 600 microns P type silicon layer, every P type silicon layer difference thermal oxide growth oxide layer; With two P type silicon layer bondings, form oxygen buried layer 2 under 15 ℃ ~ 35 ℃, annealing strengthens the bonding dynamics of two disks; By grind, polishing comes skiving one side P type silicon layer to 6 ~ 7 microns, be to form N-type trap 3 to do the basis, opposite side P type silicon layer is directly made P type substrate 1;
Step 2 is 2.5e12 cm at 6 ~ 7 microns P type silicon layer implantation dosages -2, energy is the 120Kev phosphorus impurities, advance down at 1150 ℃ to form N-type traps 3; Photoetching is developed and is determined doped region, and implantation dosage is 5e13 cm -2, energy is that the boron of 120Kev forms P type tagma 13, implantation dosage is 1.8e13 cm then -2, energy is that 140Kev phosphorus forms N-type buffering trap 4;
Step 3, first sacrificial oxide layer of 45 ~ 55 nanometers of above N-type buffering trap 4, N-type trap 3 and P type tagma 13, growing, and first silicon nitride of deposit 140 ~ 160 nanometers, first silicon nitride is carried out photoetching, develops and etching, one end of etch areas is positioned at N-type buffering trap 4, and the other end of etch areas and P type tagma 13 offset; At 950 ℃, O 2And H 2The ratio of volume content is growth field oxide 70 minutes in the atmosphere of 7:13, and then at 950 ℃, O 2With the ratio of HCL volume content be growth field oxide 20 minutes in the atmosphere of 16:0.32, form the transition field oxide in etch areas; Again transition field oxide, remaining first silicon nitride and remaining first are sacrificed the whole etchings of field oxide, form groove 6 ~ 7 microns P type silicon surface;
Step 4, second sacrificial oxide layer of 45 ~ 55 nanometers of above N-type buffering trap 4, groove and P type tagma 13, growing, and second silicon nitride of deposit 140 ~ 160 nanometers, photoetching, also second silicon nitride of etched recesses top that develops expose the groove that etches in the previous step; At 950 ℃, O 2And H 2The ratio of volume content is growth gate oxide 70 minutes in the atmosphere of 7:13, and then at 950 ℃, O 2With the ratio of HCL volume content be growth gate oxide 20 minutes in the atmosphere of 16:0.32, in groove, form field oxide 8; Second silicon nitride and the remaining whole etchings of second sacrificial oxide layer with remnants;
Step 5, the gate oxide of growth 23 ~ 27 nanometers, under 950 ℃ of environment, deposition thickness is that 400 ~ 440 nanometers, resistivity are the polysilicon gate 9 of 6.4e-4 Ω cm then;
Step 6 is selected the ion implanted region territory by mask blank, and implantation dosage is 6e13 cm in P type tagma 13 -2, energy is that phosphorus and the dosage of 50Kev is 5e15 cm -2, energy is the arsenic of 80Kev, forms N-type cathodic region 12; Implantation dosage is 5e15 cm in N-type buffering trap 4 -2, energy is that boron fluoride and the dosage of 80Kev is 5e15 cm -2, energy is the boron of 140Kev, forms p type anode district 5, implantation dosage is 5e15 cm in p-type tagma 13 simultaneously -2, energy is that boron fluoride and the dosage of 80Kev is 5e15 cm -2, energy is the boron of 140Kev, forms P type body contact zone 11; Annealing activator impurity ion;
Step 7, passivation forms passivation layer 7, and the etching oxidation layer forms contact hole; Carry out metal level deposit, photoetching, etching again, form the first metal layer 6 and second metal level 10.

Claims (2)

1. the N-type lateral insulated gate bipolar device of a high reliability, comprise: P type substrate (1), be provided with at P type substrate (1) and bury oxygen (2), be provided with N-type trap (3) burying oxygen (2), be provided with N-type buffering trap (4) and P type tagma (13) in the inside of N-type trap (3), in N-type buffering trap (4), be provided with p type anode district (5), in P type tagma (13), be provided with N-type cathodic region (12) and P type body contact zone (11), an end that is provided with field oxide (8) and field oxide (8) on the surface of N-type trap (3) extends and terminates in p type anode district (5) to p type anode district (5), the other end extends to P type tagma (13) and terminates in P type tagma (13) front end, be provided with the part upper surface that polysilicon gate (9) and polysilicon gate (9) extend to field oxide (8) on the surface in P type tagma (13), in field oxide (8), P type body contact zone (11), N-type cathodic region (12), the surface of polysilicon gate (9) and p type anode district (5) is provided with passivation layer (7), be connected with the first metal layer (6) on surface, p type anode district (5), be connected with second metal level (10) in P type body contact zone (11) and surface, N-type cathodic region (12), it is characterized in that, the degree of depth that described field oxide (8) embeds N-type trap (3) is 60% ~ 80% of oxide layer (8) gross thickness, makes that the thickness proportion of field oxide (8) part of exposing N-type trap (3) and the part that embeds N-type trap (3) is 2:3 to 1:4.
2. the preparation technology of the N-type lateral insulated gate bipolar device of a high reliability is characterized in that:
Step 1, getting two resistivity is that 25 Ω cm thickness are 500 ~ 600 microns P type silicon layer, every P type silicon layer difference thermal oxide growth oxide layer; With two P type silicon layer bondings, form oxygen buried layer (2) under 15 ℃ ~ 35 ℃, annealing strengthens the bonding dynamics of two disks; By grind, polishing comes skiving one side P type silicon layer to 6 ~ 7 microns, be to form N-type trap (3) to do the basis, opposite side P type silicon layer is directly made P type substrate (1);
Step 2 is 2.5e12 cm at 6 ~ 7 microns P type silicon layer implantation dosages -2, energy is the phosphorus impurities of 120Kev, advance down at 1150 ℃ to form N-type traps (3); Photoetching is developed and is determined doped region, and implantation dosage is 5e13 cm -2, energy is that the boron of 120Kev forms P type tagma (13), implantation dosage is 1.8e13 cm then -2, energy is that the phosphorus of 140Kev forms N-type buffering trap (4);
Step 3, first sacrificial oxide layer of 45 ~ 55 nanometers of growing in the top in N-type buffering trap (4), N-type trap (3) and P type tagma (13), and first silicon nitride of deposit 140 ~ 160 nanometers, first silicon nitride is carried out photoetching, develops and etching, one end of etch areas is positioned at N-type buffering trap (4), and the other end of etch areas and P type tagma (13) offset; At 950 ℃, O 2And H 2The ratio of volume content is growth field oxide 70 minutes in the atmosphere of 7:13, and then at 950 ℃, O 2With the ratio of HCL volume content be growth field oxide 20 minutes in the atmosphere of 16:0.32, form the transition field oxide in etch areas; With first silicon nitride of transition field oxide, remnants and the remaining whole etchings of the first sacrifice field oxide, form grooves 6 ~ 7 microns P type silicon surface again;
Step 4, second sacrificial oxide layer of 45 ~ 55 nanometers of growing in the top in N-type buffering trap (4), groove and P type tagma (13), and second silicon nitride of deposit 140 ~ 160 nanometers, photoetching, also second silicon nitride of etched recesses top that develops expose the groove that etches in the previous step; At 950 ℃, O 2And H 2The ratio of volume content is growth gate oxide 70 minutes in the atmosphere of 7:13, and then at 950 ℃, O 2With the ratio of HCL volume content be growth gate oxide 20 minutes in the atmosphere of 16:0.32, in groove, form field oxide (8); Second silicon nitride and the remaining whole etchings of second sacrificial oxide layer with remnants;
Step 5, the gate oxide of growth 23 ~ 27 nanometers, under 950 ℃ of environment, deposition thickness is that 400 ~ 440 nanometers, resistivity are the polysilicon gate (9) of 6.4e-4 Ω cm then;
Step 6 is selected the ion implanted region territory by mask blank, and implantation dosage is 6e13 cm in P type tagma (13) -2, energy is that phosphorus and the dosage of 50Kev is 5e15 cm -2, energy is the arsenic of 80Kev, forms N-type cathodic region (12); Implantation dosage is 5e15 cm in N-type buffering trap (4) -2, energy is that boron fluoride and the dosage of 80Kev is 5e15 cm -2, energy is the boron of 140Kev, forms p type anode district (5), implantation dosage is 5e15 cm in P type tagma (13) simultaneously -2, energy is that boron fluoride and the dosage of 80Kev is 5e15 cm -2, energy is the boron of 140Kev, forms P type body contact zone (11); Annealing activator impurity ion;
Step 7, passivation forms passivation layer (7), and the etching oxidation layer forms contact hole; Carry out metal level deposit, photoetching, etching again, form the first metal layer (6) and second metal level (10).
CN201310148959.5A 2013-04-25 2013-04-25 High-reliability N-type transverse insulated gate bipolar device and preparation process thereof Active CN103236437B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310148959.5A CN103236437B (en) 2013-04-25 2013-04-25 High-reliability N-type transverse insulated gate bipolar device and preparation process thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310148959.5A CN103236437B (en) 2013-04-25 2013-04-25 High-reliability N-type transverse insulated gate bipolar device and preparation process thereof

Publications (2)

Publication Number Publication Date
CN103236437A true CN103236437A (en) 2013-08-07
CN103236437B CN103236437B (en) 2015-07-01

Family

ID=48884467

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310148959.5A Active CN103236437B (en) 2013-04-25 2013-04-25 High-reliability N-type transverse insulated gate bipolar device and preparation process thereof

Country Status (1)

Country Link
CN (1) CN103236437B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103762230A (en) * 2014-01-24 2014-04-30 东南大学 N-channel injection efficiency reinforced insulated gate bipolar transistor
CN104916674A (en) * 2015-04-17 2015-09-16 东南大学 Current enhanced type lateral insulated gate bipolar transistor
CN112053953A (en) * 2020-09-29 2020-12-08 上海华虹宏力半导体制造有限公司 Insulated gate bipolar transistor and manufacturing method thereof
CN112825301A (en) * 2019-11-21 2021-05-21 东南大学 Insulated gate bipolar transistor device and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670396A (en) * 1995-11-21 1997-09-23 Lucent Technologies Inc. Method of forming a DMOS-controlled lateral bipolar transistor
CN102437181A (en) * 2011-12-08 2012-05-02 东南大学 N type silicon on insulator transverse insulated gate bipolar device
US20130069712A1 (en) * 2011-09-15 2013-03-21 Tanya Trajkovic Power semiconductor devices and fabrication methods

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670396A (en) * 1995-11-21 1997-09-23 Lucent Technologies Inc. Method of forming a DMOS-controlled lateral bipolar transistor
US20130069712A1 (en) * 2011-09-15 2013-03-21 Tanya Trajkovic Power semiconductor devices and fabrication methods
CN102437181A (en) * 2011-12-08 2012-05-02 东南大学 N type silicon on insulator transverse insulated gate bipolar device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103762230A (en) * 2014-01-24 2014-04-30 东南大学 N-channel injection efficiency reinforced insulated gate bipolar transistor
CN103762230B (en) * 2014-01-24 2016-06-29 东南大学 N-channel injection efficiency reinforced insulation grid bipolar transistor
CN104916674A (en) * 2015-04-17 2015-09-16 东南大学 Current enhanced type lateral insulated gate bipolar transistor
CN104916674B (en) * 2015-04-17 2017-10-31 东南大学 A kind of intensifying current type landscape insulation bar double-pole-type transistor
CN112825301A (en) * 2019-11-21 2021-05-21 东南大学 Insulated gate bipolar transistor device and manufacturing method thereof
CN112825301B (en) * 2019-11-21 2022-08-12 东南大学 Insulated gate bipolar transistor device and manufacturing method thereof
CN112053953A (en) * 2020-09-29 2020-12-08 上海华虹宏力半导体制造有限公司 Insulated gate bipolar transistor and manufacturing method thereof
CN112053953B (en) * 2020-09-29 2024-03-22 上海华虹宏力半导体制造有限公司 Insulated gate bipolar transistor and manufacturing method thereof

Also Published As

Publication number Publication date
CN103236437B (en) 2015-07-01

Similar Documents

Publication Publication Date Title
EP1292990B1 (en) Trench mosfet with double-diffused body profile
TWI441336B (en) Mosfet device with reduced breakdown voltage
US7598143B2 (en) Method for producing an integrated circuit with a trench transistor structure
CN103928344B (en) One kind improves N-type DiMOSFET channel mobility method based on N-type nano thin-layer
CN103441148B (en) A kind of groove grid VDMOS device of integrated schottky diode
CN102751195A (en) Lateral transistor and manufacturing method thereof
CN103178093B (en) The structure of high-voltage junction field-effect transistor and preparation method
CN103236437B (en) High-reliability N-type transverse insulated gate bipolar device and preparation process thereof
CN102412162B (en) Method for improving breakdown voltage of N-groove laterally diffused metal oxide semiconductor (LDMOS)
CN106129117A (en) A kind of lateral double-diffused metallic oxide semiconductor tube of high reliability
CN105489500A (en) Preparation method for super-junction VDMOS and super-junction VDMOS device
CN103985746A (en) Groove type IGBT (Insulated Gate Bipolar Transistor) device and manufacturing method thereof
CN104347475B (en) Edge termination structure with trench isolation regions
CN104253050B (en) A kind of manufacture method of grooved lateral MOSFET device
CN102157377B (en) Super-junction VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) device and manufacturing method thereof
KR100902585B1 (en) Trench gate mosfet and method for fabricating of the same
CN102646712B (en) Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof
CN116705859A (en) Silicon carbide metal oxide semiconductor field effect transistor structure and preparation method thereof
US8349698B2 (en) Integrated semiconductor device and method of manufacturing the same
CN102437192B (en) N-type silicon-on-insulator transverse double-diffusion field effect transistor
CN103295910B (en) Semiconductor device and method of manufacturing the same
CN103811402B (en) A kind of isolation structure process for making of ultrahigh voltage BCD technology
CN102290344A (en) Trench type MOS (metal oxide semiconductor) tube manufacturing process
CN102103997B (en) Structure of groove type power MOS (Metal Oxide Semiconductor) device and preparation method thereof
CN104916686A (en) VDMOS device and manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant