CN103199863B - The electric charge supplementary circuitry with reference to settling time is shortened in pipeline a/d converter - Google Patents

Abstract

The present invention relates in a kind of pipeline a/d converter the electric charge supplementary circuitry shortened with reference to settling time, it comprises 1 comparator Q ₁, 2 PMOS PM ₁, PM ₂, 1 metal capacitance C _b.The scheme of circuit of the present invention is, when input range is less than full amplitude half time, the electric charge of supplementary sampling capacitance demand is carried out with the large charge be stored in advance on metal capacitance, make reference voltage less depart from operating voltage, the time of voltage thus shortening reference voltage is resumed work, reach the effect shortening reference voltage settling time, and then improve the conversion speed of pipeline a/d converter.Use shorten more than 49% than the settling time of routine reference circuit the settling time of reference circuit of the present invention.It is mainly used in low-power consumption high-speed high-precision flow line A/D converter field.

Description

The electric charge supplementary circuitry with reference to settling time is shortened in pipeline a/d converter

Technical field

The present invention relates to a kind of electric charge supplementary circuitry for shortening in pipeline a/d converter with reference to settling time, its direct application is low-power consumption high-speed high-precision flow line A/D converter field.

Background technology

In current low-power consumption high-speed high-precision flow line A/D converter field, reference circuit needs provide within the scope of full bandwidth to export with the Low ESR of load matched, and object makes reference voltage set up fast in load exactly.Fig. 1 is conventional pipeline a/d converter structured flowchart.In Fig. 1, the A/D converter of pipeline organization comprises k level circuit, and wherein, the circuit structure before k-1 level is identical, as shown in the dotted line frame inner structure of Fig. 1.Operation principle is:

Sampling/the retainer of the 1st grade of circuit is at V _cLKNrising edge, to input signal sampling, at V _cLKNtrailing edge, by the thick A/D converter (m of a m bit resolution ₁position ADC), by input reference voltage V _refinput signal is quantized, after quantized result, exports m digit numeric code (m ₁position); M digit numeric code sends into the Type Multiplicative digital to analog converter (m of a m position equally ₁position MDAC), Type Multiplicative digital to analog converter utilizes reference voltage V _ref, convert the analog voltage of corresponding m digit numeric code to and ask poor with input signal, then difference is accurately amplified 2 ^k-mdoubly, deliver to next stage processing of circuit.

After multistage process like this, be finally the thin A/D converter (N in N position by a precision _kposition ADC) residue signal is changed, the above-mentioned 1st grade of digital code to kth level circuit is exported through digital correction circuit, according to the 1st k-1 clock cycle of progression character code output delay, 2nd stages of digital output code postpones k-2 clock cycle, the rest may be inferred, postpones 1 clock cycle to kth-1 stages of digital output code, and kth progression character code exports and do not postpone, again the 1st grade of digital output code to kth level is folded position to be added, the final digital code exporting n position.

Pipeline a/d converter will reach the quantification of n position precision, and the 1st class precision of streamline must reach the requirement of n position precision.The load capacitance defining the 1st level production line is C _s, reference capacitance is C _r.Work as C _ssampled input signal V _inafter, start moment, electric capacity C in maintenance phase place _rand C _selectric charge distributive operation formula:

$V_s=\frac{V_{\mathrm{ref}}\×C_r+V_{\mathrm{in}}\×C_s}{C_r+C_s}---\left(1\right)$

(1) in formula, V _sfor electric charge distributes the voltage of finish time.

After this, reference current is to load C _sbe charged to V _ref:

$t_{\mathrm{set}}=\frac{(V_{\mathrm{ref}}-V_s)\×(C_r+C_s)}{I_{\mathrm{ref}}}---\left(2\right)$

(2) in formula, I _reffor reference output current.

(1) and in (2) formula, do not consider higher, settling time t _setbe defined as V _srise to V _reftime, t _setwith input signal V _inrelevant.

Because settling time t _setwith input signal V _insize be correlated with, so in the pipeline a/d converter of routine, its reference voltage V _refall there is input signal V _inwhen amplitude is less than 1/2nd full amplitudes, its settling time t _setthan input signal V _inwhen amplitude is greater than 1/2nd full amplitudes, settling time is larger, when being input as zero settling time t _setreach maximum.The settling time of general reference voltage is be less than time pipeline a/d converter change-over period 25%, the reference voltage long switching rate just limiting pipeline a/d converter settling time.

Summary of the invention

For overcoming the problem of reference voltage length settling time of conventional pipeline a/d converter, the present invention proposes in a kind of pipeline a/d converter the electric charge supplementary circuitry shortened with reference to settling time, it is characterized in that:

Shorten the electric charge supplementary circuitry with reference to settling time in pipeline a/d converter, it comprises:

Comparator Q ₁, PMOS PM ₁, PMOS PM ₂with electric capacity C _b, wherein, Q ₁input positive termination reference input voltage end V _rEF1, Q ₁input negative terminal meet analog input voltage end V _in, Q ₁input end of clock CLK meet clock input anode V _cLKP, Q ₁output V _q1with PM ₁grid connect, PM ₁source electrode meet reference output voltage end V _rEFO, PM ₁drain electrode meet C _banode, and and PM ₂drain electrode be connected, PM ₂grid meet clock input negative terminal V _cLKN, PM ₂source electrode meet high potential Input voltage terminal V _cP, PM ₁and PM ₂the equal ground connection of substrate, C _bnegativing ending grounding.

Described comparator Q ₁when the trailing edge of input end of clock CLK, compare Q ₁anode input voltage and Q ₁the size of negative terminal input voltage, works as Q ₁anode input voltage is greater than Q ₁during negative terminal input voltage, V _q1output low level, otherwise V _q1export high level; Q ₁when input end of clock CLK rising edge, reset; After reset, V _q1export high level.

Described clock input anode V _cLKPnegative terminal V is inputted with clock _cLKNit is the complementary clock of non-overlapping.

Described electric capacity C _bfor metal capacitance, when reference voltage 1V, load capacitance 4pF, its capacitance is 2.5pF.

Beneficial effect:

Shortening the electric charge supplementary circuitry with reference to settling time in pipeline a/d converter of the present invention, is by comparator Q ₁judge input signal V _insize, as input signal V _inbe less than with reference to V _rEF1time, introduce electric charge and supplement metal capacitance C _b, thus reduce analog input voltage to the impact of load, reach the object of the settling time shortening reference.When input range is less than full amplitude half time, with being stored in advance in metal capacitance C _bon large charge carry out the electric charge of supplementary sampling capacitance demand, make reference voltage less depart from operating voltage, thus shortening reference voltage is resumed work, the time of voltage, reaches the effect shortening reference voltage settling time, and then can improve the conversion speed of pipeline a/d converter.

Fig. 4 is sequential chart and the reference voltage oscillogram of the pipeline a/d converter applying circuit of the present invention, reference voltage V wherein _refas shown by the solid line, settling time is t to waveform ₁, do not use the output waveform figure of generalized reference circuit of the present invention as V in Fig. 4 _refshown in dotted line, settling time is t ₂, t ₁compare t ₂reduce 49.9%.Therefore, the reference circuit applied after circuit of the present invention improves 49.9% than the settling time of routine reference circuit, namely applies the pipeline a/d converter after circuit of the present invention, and its switching rate promotes 50% than the switching rate of conventional pipeline a/d converter.

Accompanying drawing explanation

Fig. 1 is conventional pipeline a/d converter system architecture diagram.

Fig. 2 is the electrical schematic diagram that the present invention shortens the electric charge supplementary circuitry with reference to settling time.

Fig. 3 is the structured flowchart of circuit application of the present invention on conventional pipeline a/d converter.

Fig. 4 is sequential chart and the reference voltage oscillogram of the pipeline a/d converter applying circuit of the present invention.

Embodiment

The specific embodiment of the present invention is not limited only to description below, now further illustrates by reference to the accompanying drawings.

Fig. 2 is the electrical schematic diagram that the present invention shortens the electric charge supplementary circuitry with reference to settling time, and concrete connection is identical with the summary of the invention part of this specification, and the operation principle of the present invention self is as follows:

The voltage V of clock input negative terminal _cLKNduring for low level, PM ₂conducting, high potential Input voltage terminal V _cPvoltage deliver to C _banode, now, clock input anode voltage V _cLKPfor high level, the first comparator Q ₁export as high level, the first PMOS PM ₁disconnect; V _cLKNduring for high level, the second PMOS PM ₂disconnect, the voltage V of clock input anode _cLKPat the voltage V of clock input negative terminal _cLKNafter uprising, drop to low level, Q ₁the relatively voltage V of 1/2 reference input voltage end _rEF1with the voltage V of analog input voltage end _insize: work as V _inbe less than V _rEF1time, Q ₁output low level, PM ₁conducting, the first electric capacity C _bpositive terminal voltage deliver to reference output voltage end V _rEFO.If V _inbe greater than V _rEF1, Q ₁export high level, PM ₁disconnect, reference output voltage end V _rEFOhigh-impedance state; V _cLKPduring for high level, Q ₁reset and export high level.

Fig. 3 is the structured flowchart of circuit application of the present invention on conventional pipeline a/d converter, in Fig. 3, and V _cPtermination power V _cC, V _rEF1termination reference voltage V _ref1/2 output, V _rEFOconnect with reference to output V _ref, V _inthe analog input end V of termination A/D converter system _in, V _cLKNthe V of terminating systems _cLKNend, V _cLKPthe V of terminating systems _cLKPend; V _cLKPand V _cLKNfor the complementary clock of non-overlapping.

Fig. 4 is sequential chart and the reference voltage oscillogram of the pipeline a/d converter applying circuit of the present invention.In Fig. 4, V _infor analog input waveform, V _cLKNfor clock negative terminal signal waveform, V _cLKNlow level is sampling phase, V _cLKNhigh level is for keeping phase place, V _cLKPfor clock signal anode waveform, itself and V _cLKNfor non-overlapping complementary clock, V _q1for comparator Q ₁output waveform, V _reffor reference output waveform.

The operation principle of circuit application of the present invention in pipeline a/d converter is as follows:

Work as V _cLKNduring for low level, PM ₂conducting, supply voltage delivers to C _banode, C _bupper storage C _bv _cCelectric charge.Work as V _cLKNduring rising edge, PM ₂disconnect, now V _cLKPtrailing edge make comparator Q ₁relatively negative terminal input V _inwhether voltage is less than anode input voltage V _rEF1if: be less than V _rEF1, then Q ₁output voltage V _q1for low level, PM ₁conducting, C _bpositive terminal voltage delivers to V _rEFOport; If be greater than V _rEF1, then Q ₁output voltage V _q1for high level, PM ₁cut-off.Output V _rEFOhigh-impedance state.V _cLKPrising edge compare V _cLKNtrailing edge arrive in advance, V _cLKPhigh level reset Q ₁, make Q ₁output voltage V _q1export high level.

Due to V _rEFOwith A/D converter with reference to output V _refbe connected.Work as V _rEFOon have voltage to output to V _reftime, the 1st grade of load capacitance C _son the electric charge that now stores be V _inc _s, reference capacitance C _ron the electric charge that now stores be V _refc _r, the electric charge that circuit of the present invention now stores is C _bv _cC.Now obtained by charge conservation:

V _ref×C _r+V _CC×C _b+V _in×C _s=V _S(C _r+C _b+C _s)（3）

After this reference circuit output current I _refload capacitance (C _r+ C _b+ C _s) on voltage from V _sadjust to normal operating reference voltage V _ref, the time required for adjustment is t settling time _set:

$t_{\mathrm{set}}=\frac{(V_{\mathrm{ref}}-V_s)\×(C_r+C_s+C_b)}{I_{\mathrm{ref}}}---\left(4\right)$

First metal capacitance C of the present invention _bcapacitance be defined as analog input V _inwhen equaling 1/2 reference voltage, C _bthe excess charge C of upper storage _b(V _cC-V _ref) equal the 1st grade of load C _sthe electric charge of upper storage.

In the embodiment of the present invention: reference voltage V _reffor 1V, with reference to output capacitance C _rfor 1nF, the 1st grade of load capacitance C _sfor 4pF.Calculate electric capacity C _b:

$C_b=\frac{C_s\×V_{\mathrm{ref}}/2}{V_{\mathrm{CC}}-V_{\mathrm{ref}}}---\left(5\right)$

Draw C _b=2.5pF.

By (3) formula, work as V _induring=0V, draw V _s=998.013mV.

By (3) formula, when not using of the present invention, C _b=0pF, works as V _induring=0V, draw V _s=996.016mV.

By (4) formula, obtain:

t ₁/t ₂=(1-0.996016)/(1-0.998013)=49.9%。

In Fig. 4, the reference of circuit of the present invention is denoted as t settling time ₁, do not use the reference of circuit of the present invention to be denoted as t settling time ₂.As shown in Figure 4, after namely applying circuit of the present invention, the reference of pipeline a/d converter can shorten 49.9% settling time.

Described first comparator Q ₁, compare Q at the trailing edge of input end of clock CLK ₁anode input voltage and Q ₁the size of negative terminal input voltage, wherein, Q ₁anode input voltage is greater than Q ₁during negative terminal input voltage, V _q1output low level, otherwise V _q1export high level; Q ₁reset when clock CLK rising edge, after reset, V _q1export high level.

Described input end of clock mouth V _cLKPand V _cLKNfor non-overlapping complementary clock.

Described comparator Q ₁for conventional comparator, its Specifeca tion speeification is: clock CLK is 250MHz, and minimum resolution is 10mV, and offset voltage is less than 30mV.

Described PM ₁, PM ₂for PMOS, breadth length ratio is W/L=20000nm/180nm.

Described first electric capacity is metal capacitance C _b, be 1V at reference voltage, when load capacitance is 4pF, capacitance is 2.5pF.

The present invention adopts standard 0.18 μm of CMOS technology.

Claims (2)

1. shorten the electric charge supplementary circuitry with reference to settling time in pipeline a/d converter, it is characterized in that it comprises:

Comparator Q ₁, PMOS PM ₁, PMOS PM ₂with electric capacity C _b, wherein, Q ₁input positive termination reference input voltage end V _rEF1, Q ₁input negative terminal meet analog input voltage end V _in, Q ₁input end of clock CLK meet clock input anode V _cLKP, comparator Q ₁when the trailing edge of input end of clock CLK, work as Q ₁anode input voltage is greater than Q ₁during negative terminal input voltage, V _q1for low level, otherwise V _q1for high level, Q ₁reset when input end of clock CLK rising edge, V after resetting _q1for high level, Q ₁output V _q1with PM ₁grid connect, PM ₁source electrode meet reference output voltage end V _rEFO, PM ₁drain electrode meet C _banode, and and PM ₂drain electrode be connected, PM ₂grid meet clock input negative terminal V _cLKN, PM ₂source electrode meet high potential Input voltage terminal V _cP, clock input anode V _cLKPnegative terminal V is inputted with clock _cLKNthe complementary clock of non-overlapping, PM ₁and PM ₂the equal ground connection of substrate, C _bnegativing ending grounding.

2. shorten the electric charge supplementary circuitry with reference to settling time in pipeline a/d converter according to claim 1, it is characterized in that described electric capacity C _bfor metal capacitance, when reference voltage 1V, load capacitance 4pF, its capacitance is 2.5pF.