CN101645710A - Low supply voltage pipelined folded interpolating analog-to-digital converter - Google Patents
Low supply voltage pipelined folded interpolating analog-to-digital converter Download PDFInfo
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Abstract
The invention belongs to the technical field of integrated circuit, in particular to a low supply voltage pipelined folded interpolating analog-to-digital converter. The invention comprises a track and hold circuit, a reference voltage resistance string, a coarse pre-amplifier circuit, a fine pre-amplifier circuit, a first sampling switch, a folded circuit, a second sampling circuit, an interpolating circuit, a comparator and a coding circuit, wherein, the sampling circuit adopts grid voltage bootstrapped switch. The structure of the invention is able to decrease the time delay of analog-to-digital converter key route, effectively raising the conversion rate of the low supply voltage pipelined folded interpolating analog-to-digital converter.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of folded interpolating A/D converter that is applicable to low supply voltage, ultra high-speed adc.
Background technology
Folded interpolating A/D converter is the analog to digital converter of a kind of medium accuracy, high conversion rate.In the application of or portable system or equipment embedded, require analog to digital converter to be operated under the low supply voltage at some.Yet along with the reduction of supply voltage, the gain of circuit is restricted, and in order to realize enough gains, the method that adopts is the more gain stage of cascade usually.As everyone knows, cascade the more unfavorable result of multiple gain stages increased the time delay on the signal path.Shown in Figure 1 is usually the structure chart of the folded interpolating A/D converter of employing, mainly is made of track and hold circuit 10, reference voltage resistance string 11, the pre-amplifying circuit 12 of thick son, thin sub pre-amplifying circuit 13, folding electric circuit 14, interpolating circuit 15, comparator 16 and coding circuit 17.Generally speaking, the maximum time of folded interpolating A/D converter signal postpones the time delay sum decision by the pre-amplifying circuit of thin sub-transducer, folding electric circuit, interpolating circuit, in other words, the time delay sum of the pre-amplifying circuit of thin sub-transducer, folding electric circuit, interpolating circuit has determined the high conversion rate that folded interpolating A/D converter can be worked.Along with reducing of supply voltage, folding electric circuit and interpolating circuit all not only are made of single-level circuit, usually can adopt the structure of cascade, and the switching rate of folded interpolating A/D converter will be subjected to certain restriction like this.
Summary of the invention
The objective of the invention is to propose a kind of time delay that can reduce the analog to digital converter critical path, effectively improve the low supply voltage pipelined folded interpolating analog-to-digital converter structure of the switching rate of low-voltage folded interpolating A/D converter.
The low-voltage pipelined folded interpolating analog-to-digital converter that the present invention proposes, its structure is similar to folded interpolating A/D converter shown in Figure 1, only between pre-amplifying circuit of thin son and folding electric circuit, be provided with first sampling switch, be arranged at second sampling switch again between folding electric circuit and the interpolating circuit.Promptly this folded interpolating A/D converter comprises: track and hold circuit, reference voltage resistance string, thick sub-prime amplifier, thin sub-prime amplifier, folding electric circuit, interpolating circuit, comparator, coding circuit, first sampling switch and second sampling switch; Analog input signal is through the track and hold circuit signal that is maintained; The reference level that inhibit signal and reference voltage resistance string produce is output as the difference amplifying signal between inhibit signal and the reference level as the input signal of pre-amplifying circuit of thick son and the pre-amplifying circuit of thin son; The output signal of the pre-amplifying circuit of thick son becomes the input signal of part comparator, exports through the thermometer code that relatively obtains of comparator; The output of the pre-amplifying circuit of thin son links first sampling switch, and the signal after the maintenance becomes the input signal of folding electric circuit; The output of folding electric circuit links second sampling switch, and the signal after the maintenance becomes the input signal of interpolating circuit; The output signal of interpolating circuit becomes the input signal of comparator, exports through the circulating temperature sign indicating number that relatively obtains of comparator; Coding circuit obtains the binary system output code according to the thermometer code of thick sub-comparator output and the circulating temperature sign indicating number coding of thin sub-comparator output.
It no longer is the time delay sum of pre-amplifying circuit, folding electric circuit and interpolating circuit that the adding of first sampling switch and second sampling switch makes the peak signal in the signal path postpone, but the time delay sum of the longest that of time delay and sampling switch in this three partial circuit.Adopt rational construction of switch to compare with the time delay of pre-amplifying circuit, folding electric circuit or interpolating circuit, can ignore so that the time delay of sampling switch is very little.Therefore, the time delay of the critical path of analog to digital converter has reduced, and switching rate has improved.
The folding electric circuit and the interpolating circuit that are operated in the folded interpolating A/D converter under the low-voltage also can adopt the multistage structure of cascade, the pipeline-type structure that the present invention proposes i.e. first and second sampling switchs can be applied in the cascade circuit of each grade, this architectural feature is: the output of first order folding electric circuit connects first order sampling switch, signal after the maintenance becomes the input signal of second level folding electric circuit, the output of second level folding electric circuit connects second level sampling switch, signal after the maintenance becomes the input signal of third level folding electric circuit, the rest may be inferred, the inhibit signal that N-1 level sampling switch obtains becomes the input signal of N level folding electric circuit, its output connects N level sampling switch, and the signal after the maintenance is the output signal of folding electric circuit; The output signal of folding electric circuit becomes the input signal of first order interpolating circuit, its output connects N+1 level sampling switch, signal after the maintenance becomes the input signal of second level interpolating circuit, the output of second level interpolating circuit connects N+2 level sampling switch, signal after the maintenance becomes the input signal of third level interpolating circuit, and the like, the inhibit signal that N+M-1 level sampling switch obtains becomes the input signal of M level interpolating circuit, and it is output as the output signal of interpolating circuit.Here the first order belongs to first sampling switch to the sampling switch of N+1 level, and the N+1 level belongs to second sampling switch to N+M level sampling switch.
Maximum delay in the said structure only is the time delay of one-level folding electric circuit or one-level interpolating circuit and the time delay sum of sampling switch, adopt this structure analog to digital converter operating rate in addition can reach several GHzs.
Sampling switch in the said structure (comprising first and second sampling switchs) can adopt the grid voltage bootstrapped switch, the conducting resistance of general cmos switch and gate source voltage difference are inversely proportional to, along with reducing of supply voltage, the gate source voltage difference of cmos switch constantly reduces, cause the conducting resistance of cmos switch to improve, the load capacitance of switch conduction resistance and late-class circuit can increase the extra time-delay of signal.Therefore, the conducting resistance of switch is the smaller the better.In addition, what sampling switch in the said structure was handled is analog signal, to switch have the requirement of certain linearity, the gate source voltage difference when improving switch conduction help to reduce relevant with input signal non-linear, the performance of raising sampling switch.
Fig. 4 has shown the grid voltage bootstrapped switch that the present invention adopts.This grid voltage bootstrapped switch is made of five metal-oxide-semiconductors and an electric capacity.The one PMOS manages M1, and its source end and substrate are received power supply Vdd, and grid end and drain terminal are connected to bootstrap voltage mode Vg.The 2nd PMOS manages M2, and its source terminates to power supply Vdd, and grid end, drain terminal and substrate are received bootstrap voltage mode Vg.Cs is an electric capacity, a termination clock signal clk, another termination bootstrap voltage mode Vg.The one NMOS manages M3, and short circuit is leaked together in the source, is connected to input signal in simultaneously, grid termination inversion clock signal clkb.The 2nd NMOS manages M4, source termination input signal in, and drain terminal is the output out of sampling switch, the grid end is connected to bootstrap voltage mode Vg.The 3rd NMOS manages M5, and short circuit is leaked together in the source, is connected to output out simultaneously, grid termination inversion clock signal clkb.
Description of drawings
Fig. 1 shows the folded interpolating A/D converter structural representation.
Fig. 2 display pipeline type folded interpolating A/D converter structural representation.
Fig. 3 shows the pipeline-type structure of cascade folding interpolation electric circuit.
Fig. 4 shows low-voltage grid voltage bootstrapped switch.
Number in the figure: 10 expression track and hold circuits, 11 expression reference voltage resistance string, the pre-amplifying circuit of the thick son of 12 expressions, the pre-amplifying circuit of the thin son of 13 expressions, 14 expression folding electric circuits, 15 expression interpolating circuits, 16 expression comparators, 17 presentation code circuit, 20 expression track and hold circuits, 21 expression reference voltage resistance string, the pre-amplifying circuit of the thick son of 22 expressions, the pre-amplifying circuit of the thin son of 23 expressions, 24 expressions, first sampling switch, 25 expression folding electric circuits, 26 expressions, second sampling switch, 27 expression interpolating circuits, 28 expression comparators, 29 presentation code circuit, 30 expression first order folding electric circuits, 31 expression first order sampling switchs, 32 expression N level folding electric circuits, 33 expression N level sampling switchs, 34 expression first order interpolating circuits, 35 expression N+1 level sampling switchs, 36 expression M level interpolating circuits.
Embodiment
Further describe the present invention below in conjunction with accompanying drawing.
Fig. 2 is the low-voltage pipelined folded interpolating analog-to-digital converter schematic diagram that the present invention proposes, and its operation principle is:
(1) analog input signal is through track and hold circuit 20 signal that is maintained.
(2) reference level of inhibit signal and reference voltage resistance string 21 generations is output as the difference amplifying signal between inhibit signal and the reference level as the input signal of pre-amplifying circuit 22 of thick son and the pre-amplifying circuit 23 of thin son.
(3) output signal of the pre-amplifying circuit of thick son becomes the input signal of part comparator 28, exports through the thermometer code that relatively obtains of comparator.
(4) output of the pre-amplifying circuit of thin son links first sampling switch 24, and the signal after the maintenance becomes the input signal of folding electric circuit 25.
(5) output of folding electric circuit links second sampling switch 26, and the signal after the maintenance becomes the input signal of interpolating circuit 27.
(6) output signal of interpolating circuit becomes the input signal of comparator 28, exports through the circulating temperature sign indicating number that relatively obtains of comparator.
(7) coding circuit 29 obtains the binary system output code according to the thermometer code of thick sub-comparator output and the circulating temperature sign indicating number coding of thin sub-comparator output.
Real work speed and operating voltage according to analog to digital converter, folding electric circuit and interpolating circuit can adopt cascade form, can insert the time delay that sampling switch reduces the analog to digital converter critical path behind the cascade circuit of each grade, improve the operating rate of analog to digital converter.Fig. 3 has shown the pipeline-type structure of cascade folding interpolation electric circuit, can be used in the alternate figures 2 folding electric circuit 25, adopt the second sample switch 26 and interpolating circuit 27 parts.Operation principle is:
(1) output of first order folding electric circuit 30 links first order sampling switch 31, and the signal after the maintenance becomes the input signal of second level folding electric circuit.The rest may be inferred, and the inhibit signal that N-1 level sampling switch obtains becomes the input signal of N level folding electric circuit 32, and its output links N level sampling switch 33, and the signal after the maintenance is the output signal of folding electric circuit.
(2) output signal of folding electric circuit becomes the input signal of first order interpolating circuit 34, and its output links N+1 level sampling switch 35, and the signal after the maintenance becomes the input signal of second level interpolating circuit.And the like, the inhibit signal that N+M-1 level sampling switch obtains becomes the input signal of M level interpolating circuit 36, and it is output as the output signal of interpolating circuit.
The sampling switch progression that inserts requires to determine according to the operating rate of analog to digital converter reality, inserts one-level sampling switch etc. as every two-stage cascade circuit.
The operation principle of grid voltage bootstrapping sampling switch shown in Figure 4 is: the grid leak of M1 links together, and source end and substrate link together, and constitutes a diode, and anode is attached at bootstrap voltage mode Vg, and negative terminal is attached at power supply Vdd.Grid end, drain terminal and the substrate of M2 link together, and constitute a diode with the source end, and anode is attached at Vg, and negative terminal is attached at Vdd.Cs is the grid voltage bootstrap capacitor, a termination bootstrap voltage mode Vg, a termination clock signal clk.More than three elements constituted boostrap circuit in the grid voltage bootstrapped switch.M4 is a switching tube, and M3 and M5 are in order to reduce the routed logical redundant transistor that injects with electric charge of clock.When clk was low level, the diode that M1 constitutes was anti-inclined to one side, the diode positively biased that M2 constitutes, because the effect of M2, Vg is near Vdd, but can be less than Vdd, and their difference is the conducting voltage of diode.At this moment, the gate source voltage difference of M4 is less than transistorized threshold voltage, and then switching tube is closed.As clk when being high by low saltus step, saltus step can not take place in the voltage at Cs two ends, and then the Vg voltage of ordering is elevated beyond supply voltage Vdd.At this moment, the diode positively biased that M1 constitutes, the diode that M2 constitutes is anti-inclined to one side, because the effect of M1, the magnitude of voltage of Vg approaches the conducting voltage that Vdd adds diode, its effect is to limit the bootstrap voltage mode value, makes it to be unlikely to Tai Gao and the reliability that influences circuit.At this moment, the gate source voltage difference of M4 is greater than transistorized threshold voltage, then switching tube conducting.Owing to adopted the grid voltage bootstrap technique, in the signal trace stage, the raising of M4 gate source voltage difference helps to reduce relevant with input signal non-linear, has improved the linearity of sampling switch.The conducting voltage of two diodes that M1 and M2 constitute can be regulated according to the breadth length ratio of M1 and M2.The grid voltage of the variation of M3 and M5 grid voltage and switching tube M4 changes opposite, so the clock that the breadth length ratio that is fit to of M3 and M5 can be offset M4 leads to bursting of input and output.
Claims (5)
1, a kind of low supply voltage pipelined folded interpolating analog-to-digital converter is characterized in that comprising: track and hold circuit, reference voltage resistance string, thick sub-prime amplifier, thin sub-prime amplifier, folding electric circuit, interpolating circuit, comparator, coding circuit, first sampling switch and second sampling switch;
(1) analog input signal is through track and hold circuit (20) signal that is maintained;
(2) the pre-amplifying circuit (22) of the thick son of reference level conduct of inhibit signal and reference voltage resistance string (21) generation and the carefully input signal of sub pre-amplifying circuit (23) are output as the difference amplifying signal between inhibit signal and the reference level;
(3) output signal of the pre-amplifying circuit of thick son becomes the input signal of part comparator (28), exports through the thermometer code that relatively obtains of comparator;
(4) output of the pre-amplifying circuit of thin son links first sampling switch (24), and the signal after the maintenance becomes the input signal of folding electric circuit (25);
(5) output of folding electric circuit links second sampling switch (26), and the signal after the maintenance becomes the input signal of interpolating circuit (27);
(6) output signal of interpolating circuit becomes the input signal of comparator (28), exports through the circulating temperature sign indicating number that relatively obtains of comparator;
(7) coding circuit (29) obtains the binary system output code according to the thermometer code of thick sub-comparator output and the circulating temperature sign indicating number coding of thin sub-comparator output.
2, analog to digital converter according to claim 1 is characterized in that folding electric circuit (25) and first sampling switch (24), and second sampling switch (26) and interpolating circuit (27) adopt cascade form:
(1) first order folding electric circuit (30) output links first order sampling switch (31), and the signal after the maintenance becomes the input signal of second level folding electric circuit; The rest may be inferred, and the inhibit signal that N-1 level sampling switch obtains becomes the input signal of N level folding electric circuit (32), and its output links N level sampling switch (33), and the signal after the maintenance is the output signal of folding electric circuit;
(2) output signal of folding electric circuit becomes the input signal of first order interpolating circuit (34), and its output links N+1 level sampling switch (35), and the signal after the maintenance becomes the input signal of second level interpolating circuit; And the like, the inhibit signal that N+M-1 level sampling switch obtains becomes the input signal of M level interpolating circuit (36), and it is output as the output signal of interpolating circuit.
3, according to claim 1 or the described analog to digital converter of claim 2, it is characterized in that described first and second sampling switchs all adopt the grid voltage bootstrapped switch, this grid voltage bootstrapped switch is made of five metal-oxide-semiconductors and an electric capacity; The one PMOS manages (M1), and its source end and substrate are received power supply (Vdd), and grid end and drain terminal are connected to bootstrap voltage mode (Vg); The 2nd PMOS manages (M2), and its source terminates to power supply (Vdd), and grid end, drain terminal and substrate are received bootstrap voltage mode (Vg); Electric capacity (Cs), a termination clock signal (clk), another termination bootstrap voltage mode (Vg); The one NMOS manages (M3), and short circuit is leaked together in the source, is connected to input signal (in) simultaneously, grid termination inversion clock signal (clkb); The 2nd NMOS manages (M4), and source termination input signal (in), drain terminal are the output (out) of sampling switch, and the grid end is connected to bootstrap voltage mode (Vg); The 3rd NMOS manages (M5), and short circuit is leaked together in the source, is connected to output (out) simultaneously, grid termination inversion clock signal (clkb).
4, analog to digital converter according to claim 3, it is characterized in that boostrap circuit is made of diode and an electric capacity of the equivalence of two PMOS transistors, the source end of a PMOS pipe (M1) is connected power supply (Vdd) with substrate, the grid end is connected bootstrap voltage mode (Vg) with drain terminal; The source end of another PMOS pipe (M2) connects power supply (Vdd), and grid end, drain terminal and substrate are connected bootstrap voltage mode (Vg); One termination clock signal (clk) of electric capacity, another termination bootstrap voltage mode (Vg).
5, analog to digital converter according to claim 3 is characterized in that switching tube is made of 3 nmos pass transistors; Short circuit is leaked together in the source of a NMOS pipe (M3), connects input signal (in) simultaneously, and the grid end connects inversion clock signal (clkb); The source end of another NMOS pipe (M4) connects input signal (in), and drain terminal is the output (out) of sampling switch, and the grid end connects bootstrap voltage mode (Vg); Short circuit is leaked together in the source of the 3rd NMOS pipe (M5), connects output (out) simultaneously, and the grid end connects inversion clock signal (clkb).
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| CN102055477A (en) * | 2010-11-29 | 2011-05-11 | 复旦大学 | Amplitude-interleaving analog digital composite signal processing circuit |
| CN102761337A (en) * | 2011-04-27 | 2012-10-31 | Nxp股份有限公司 | Tracking and hold operations for analog-to-digital converter |
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| CN102055477A (en) * | 2010-11-29 | 2011-05-11 | 复旦大学 | Amplitude-interleaving analog digital composite signal processing circuit |
| CN102761337B (en) * | 2011-04-27 | 2015-08-05 | Nxp股份有限公司 | Tracking system with the method for following the tracks of and operating is performed to input signal |
| CN102761337A (en) * | 2011-04-27 | 2012-10-31 | Nxp股份有限公司 | Tracking and hold operations for analog-to-digital converter |
| WO2013134987A1 (en) * | 2012-03-15 | 2013-09-19 | 西安交通大学 | Distributed sample-and-hold circuit of rail-to-rail input range |
| CN103066966A (en) * | 2012-12-27 | 2013-04-24 | 成都锐成芯微科技有限责任公司 | High-speed comparator variable in common-mode wide power supply range |
| CN103066966B (en) * | 2012-12-27 | 2015-06-17 | 成都锐成芯微科技有限责任公司 | High-speed comparator variable in common-mode wide power supply range |
| CN103199863A (en) * | 2013-04-24 | 2013-07-10 | 中国电子科技集团公司第二十四研究所 | Charge supplementing circuit for shortening reference settling time in A/D (analog-digital) converter of assembly line |
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| CN104467848A (en) * | 2013-09-16 | 2015-03-25 | 航天信息股份有限公司 | Device containing offset cancelled sampling circuit |
| CN103762985B (en) * | 2014-01-16 | 2017-04-12 | 四川和芯微电子股份有限公司 | Sampling hold circuit |
| CN103762985A (en) * | 2014-01-16 | 2014-04-30 | 四川和芯微电子股份有限公司 | Sampling hold circuit |
| CN104348486A (en) * | 2014-11-13 | 2015-02-11 | 复旦大学 | Single-stage folding interpolation assembly line type analog-digital converter with redundancy bit |
| CN104348486B (en) * | 2014-11-13 | 2017-11-17 | 复旦大学 | A kind of band redundant digit single-stage folded interpolating flow-line modulus converter |
| CN104539292A (en) * | 2015-01-12 | 2015-04-22 | 东南大学 | Low-voltage high-speed sampling holding circuit |
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| CN106656184A (en) * | 2016-12-26 | 2017-05-10 | 中国科学院微电子研究所 | Folding-interpolation type analog-to-digital converter with folding ratio of 3 and error correction method thereof |
| CN106656184B (en) * | 2016-12-26 | 2020-05-19 | 中国科学院微电子研究所 | Folding interpolation type analog-digital converter with folding rate of 3 and error correction method thereof |
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