CN103187251B - The formation method of transistor - Google Patents
The formation method of transistor Download PDFInfo
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- CN103187251B CN103187251B CN201110459401.XA CN201110459401A CN103187251B CN 103187251 B CN103187251 B CN 103187251B CN 201110459401 A CN201110459401 A CN 201110459401A CN 103187251 B CN103187251 B CN 103187251B
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Abstract
The invention provides a kind of formation method of transistor, the method comprises: provide Semiconductor substrate, and described Semiconductor substrate has grid structure; Carry out the first ion implantation, the angle of described first ion implantation is acute angle; And carry out the second ion implantation, the angle of described second ion implantation is obtuse angle, and energy and the dosage of the first ion implantation described in the energy of described second ion implantation and dose ratio are high.By only forming light doping section in drain electrode, reducing the resistance between source, drain electrode, improving the performance of transistor, and technique is simple, and production cost is low.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly a kind of formation method of transistor.
Background technology
Transistor is the elementary cell forming various circuit, is modal semiconductor device.The primary structure of transistor comprises: source electrode (Source), drain electrode (Drain) and grid (Gate).Wherein, source electrode and drain electrode are the doped regions of high concentration.
Along with improving constantly of integrated circuit integrated level, the size of device is scaled step by step, but drain voltage does not reduce thereupon, which results in the increase of the channel region electric field between source electrode and drain electrode.Under the effect of highfield, electronics can obtain energy in an impact, and form the electronics that kinetic energy is larger, this electrons causes thermoelectronic effect (HotElectronEffect).This effect can cause electronics to inject to gate dielectric layer, forms grid current and substrate current, affects the reliability of device and circuit.
Prior art by forming a kind of low-doped leakage (LightlyDopedDrain, LDD) structure to reduce electric field, thus overcomes thermoelectronic effect.
Prior art forms the step with the transistor of LDD structure and comprises:
With reference to figure 1, provide Semiconductor substrate 100, described Semiconductor substrate 100 is formed with grid structure, described grid structure comprises gate dielectric layer 102 and gate electrode 104.
With reference to figure 2, with described grid structure for mask, low dose ion injection is carried out to described Semiconductor substrate 100, in the formation doped regions, both sides 106 of described grid structure.
With reference to figure 3, the described Semiconductor substrate 100 of the side of described grid structure forms mask layer 108, carries out high dose ion injection, form high-doped zone 110 and high-doped zone 111 respectively.Described high-doped zone 110 is being formed with the side of described mask layer 108, and described high-doped zone 111 be not formed with the side of described mask layer 108.Described high-doped zone 111 comprises the ion of High dose implantation and low dosage injection, and the doped region that namely above-mentioned twice ion implantation is formed overlaps, and defines source electrode.Described high-doped zone 110 and described doped regions 106 not exclusively overlap, and the two forms drain electrode jointly.
The technology of more formation LDD structure please refer to the U.S. Patent application file that publication number is US2004/0016927A1.
But due to the reducing of size of transistor, the Semiconductor substrate of grid structure side is formed mask layer needs very accurate technique of alignment, and complex process, cost are higher.Therefore, prior art all forms doped regions in the Semiconductor substrate of grid structure both sides.
Such as, with reference to figure 4, on the basis of structure as described in Figure 2, side wall 112 is formed, then, with described grid structure and described side wall 112 for mask in the both sides of described grid structure, carry out high dose ion injection, thus form symmetrical structure in described grid structure both sides.Therefore, the source electrode of described transistor all has high-doped zone 110 ' and doped regions 106 ' with drain electrode.
But, because the ion concentration in doped regions is lower, form doped regions at source electrode and the resistance between source electrode and drain electrode can be caused to increase, reduce saturation current, cause the decline of device reaction speed.
Therefore, need a kind of formation method of transistor, the resistance between source electrode and drain electrode can be reduced, improve the performance of transistor, and Simplified flowsheet, reduces costs.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of transistor, can reduce the resistance between source electrode and drain electrode, improve the performance of transistor, and Simplified flowsheet, reduce costs.
For solving the problem, embodiments of the invention provide a kind of formation method of transistor, comprising: provide Semiconductor substrate, and described Semiconductor substrate has grid structure; Carry out the first ion implantation, the angle of described first ion implantation is acute angle; And carry out the second ion implantation, the angle that described second daughter ion injects is obtuse angle, and energy and the dosage of the first ion implantation described in the energy of described second ion implantation and dose ratio are high.
Alternatively, before carrying out the first ion implantation, the sidewall being also included in described grid structure both sides forms side wall.
Alternatively, the energy range of described first ion implantation is 0.5keV to 100keV, and dosage range is 1E13/cm
2to 5E15/cm
2.
Alternatively, the energy range of described second ion implantation is 1keV to 200keV, and dosage range is 1E14/cm
2to 1E16/cm
2.
Alternatively, the scope of the angle of described first ion implantation is 45 ° to 88 °.
Alternatively, the scope of the angle of described second ion implantation is 92 ° to 135 °.
Alternatively, through described first ion implantation and described second ion implantation, the first adjacent light doping section and the first heavily doped region is formed in the described Semiconductor substrate of described grid structure side, described first light doping section is closer to described grid structure, and described first light doping section and described first heavily doped region are as the drain electrode of transistor.
Alternatively, the doping content scope of described first light doping section is 1E17/cm
3to 1E20/cm
3, the doping content scope of described first heavily doped region is 1E19/cm
3to 1E21/cm
3.
Alternatively, through described first ion implantation and described second ion implantation, in the described Semiconductor substrate of described grid structure side, be formed with the second heavily doped region, described second heavily doped region is as the source electrode of transistor, and the doping content scope of described second heavily doped region is 1E19/cm
3to 1E21/cm
3.
Alternatively, the material of described side wall comprises: silica, silicon nitride, silicon oxynitride, or its combination in any.
Compared with prior art, embodiments of the invention have the following advantages:
By only forming light doping section in drain electrode, reducing the resistance between source electrode and drain electrode, improving the performance of transistor, and, in the process forming transistor, do not comprise extra mask fabrication, simplify technique, reduce cost.
Further, before carrying out described first ion implantation, the sidewall of described grid structure both sides defines side wall, and what enhance described grid structure blocks effect, prevents from causing damage to grid structure in follow-up ion implantation process.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the cross-sectional view of the intermediate structure of the forming process of existing transistor.
Fig. 5 is the schematic flow sheet of the formation method of the transistor of one embodiment of the present of invention.
Fig. 6 to Fig. 9 is the cross-sectional view of the intermediate structure of the forming process of the transistor of one embodiment of the present of invention.
Embodiment
Embodiments of the invention, by only forming light doping section in drain electrode, reduce the resistance between source electrode and drain electrode, improve the performance of transistor, and embodiments of the invention do not comprise extra mask fabrication, simplify technique, reduce cost.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail embodiments of the invention below in conjunction with accompanying drawing.A lot of detail has been set forth so that fully understand the present invention in description below.But the present invention can implement to be much different from other modes described here, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
The present invention provide firstly a kind of formation method of transistor, and with reference to figure 5, the method comprises:
S101: provide Semiconductor substrate, described Semiconductor substrate has grid structure;
S102: carry out the first ion implantation, the angle of described first ion implantation is acute angle; And
S103: carry out the second ion implantation, the angle of described second ion implantation is obtuse angle, and energy and the dosage of the first ion implantation described in the energy of described second ion implantation and dose ratio are high.
In order to illustrate in greater detail the formation method of transistor provided by the invention, the cross-sectional view below in conjunction with intermediate structure is described in detail.
With reference to figure 6, provide Semiconductor substrate 200, described Semiconductor substrate 200 has grid structure.
Described Semiconductor substrate 200 can be silicon substrate, germanium silicon substrate, silicon-on-insulator substrate, or its combination in any.
Described grid structure comprises gate dielectric layer 202 and gate electrode 204.
The step forming described grid structure can comprise: in described Semiconductor substrate 200, form gate dielectric material layer; Described gate dielectric material layer forms layer of gate electrode material; Described layer of gate electrode material forms photoresist layer; Described photoresist layer is exposed, developing process, form patterned photoresist layer; Using described patterned photoresist layer as mask, etch described layer of gate electrode material and described gate dielectric material layer, until expose described Semiconductor substrate 200, form described grid structure.
The material of described gate dielectric layer 202 comprises silicon dioxide or hafnium, and the material of described gate electrode 204 comprises polysilicon or metal material.
Then, with reference to figure 7, the sidewall of described grid structure both sides forms side wall 206.
In one embodiment of the invention, the sidewall of described grid structure both sides forms described side wall 206.The material of described side wall 206 comprises silica, silicon nitride, silicon oxynitride, or its combination in any.In follow-up ion implantation process, described side wall 206 can protect described grid structure injury-free.The method forming described side wall 206, known by those skilled in the art, does not repeat them here.
It should be noted that, also can not form described side wall 206, directly carry out ion implantation technology.Below to form the explanation of described side wall 206.
Then, with reference to figure 8, carry out the first ion implantation, the angle of described first ion implantation is acute angle.
The angle of the ion implantation related in embodiments of the invention refers to: from the projection straight line of straight line on injection face at place, ion implantation direction rotate in the counterclockwise direction to the straight line parallel with ion implantation direction the angle of process.
The direction of described first ion implantation as shown in Figure 8.The angle of described first ion implantation is acute angle.
When carrying out described first ion implantation, in the side (i.e. drain region) of described grid structure, define original first light doping section 208, described original first light doping section 208 extends in the Semiconductor substrate immediately below described grid structure.At the opposite side (i.e. source area) of described grid structure, form original second light doping section 208 ', due to blocking of described grid structure, entering of ion is not had in Semiconductor substrate near described grid structure, define the first shielded area (Shadowing) 209, thus make Semiconductor substrate immediately below described original second light doping section 208 ' and described grid structure separately.
The angle of described first ion implantation is relevant with the width of the height of described grid structure and the first required shielded area.As one embodiment of the present of invention, the angular range of described first ion implantation is 45 ° to 88 °.
Then, with reference to figure 9, carry out the second ion implantation, the angle of described second ion implantation is obtuse angle, and energy and the dosage of the first ion implantation described in the energy of described second ion implantation and dose ratio are high.
The direction of described second ion implantation as shown in Figure 9.The angle of described second ion implantation is obtuse angle.
When carrying out described second ion implantation, under the blocking of described grid structure, there is a shielded area equally in drain region, i.e. the second shielded area 210.Described second shielded area 210 is merely through described first ion implantation, and other regions of drain region have passed through described first ion implantation and described second ion implantation, define the first heavily doped region 211.Described original first light doping section of the part without described second ion implantation in drain region forms the first light doping section 212.Adjacent described first light doping section 212 and described first heavily doped region 211 together constitute the drain electrode of transistor.
In source area, described first shielded area 209 have passed through described second ion implantation, and remainder have passed through described first ion implantation and described second ion implantation.Due to described second ion implantation dose ratio described in the dosage of the first ion implantation much bigger, such as, two orders of magnitude may be differed between the two, the described doping content of the first shielded area 209 and the doping content in other regions, source area are more or less the same, therefore, after described first ion implantation and described second ion implantation, there is not light doping section in source area, and only define second heavily doped region 211 '.Described second heavily doped region 211 ' constitutes the source electrode of transistor.
In actual applications, the doping content of the energy of described first ion implantation and described second ion implantation and the dosage light doping section that can be formed as required and heavily doped region sets.As one embodiment of the present of invention, the energy range of described first ion implantation is 0.5keV to 100keV, and dosage range is 1E13/cm
2to 5E15/cm
2, the energy range of described second ion implantation is 1keV to 200keV, and dosage range is 1E14/cm
2to 1E16/cm
2.The doping content scope of described first light doping section 212 formed thus is 1E17/cm
3to 1E20/cm
3, the doping content scope of described first heavily doped region 211 is 1E19/cm
3to 1E21/cm
3, the doping content scope of described second heavily doped region 211 ' is 1E19/cm
3to 1E21/cm
3.
The angle of described second ion implantation and the height (H as shown in Figure 9) of described grid structure determine the width (L as shown in Figure 9) of described second shielded area 210, and the width of described second shielded area 210 determines the width (L ' as shown in Figure 9) of described first light doping section 212.As one embodiment of the present of invention, the altitude range of described grid structure is 50 nanometer to 200 nanometers, and the width range of described first light doping section 212 is 5 nanometer to 100 nanometers, and the angular range of described second ion implantation is 92 ° to 135 °.
So far, the transistor of the embodiment of the present invention is defined.Described transistor comprises for the formation of the drain region of drain electrode and the source area for the formation of source electrode, and both are positioned at the Semiconductor substrate of grid structure both sides, and described drain region comprises light doping section and heavily doped region, and described source area does not comprise light doping section.
It should be noted that, also first can carry out described second ion implantation and carry out described first ion implantation again, adjacent light doping section and heavily doped region can be formed respectively equally in the Semiconductor substrate of grid structure side, as drain electrode, heavily doped region is formed, as source electrode in the Semiconductor substrate of opposite side.
Compared with prior art, embodiments of the invention tool has the following advantages:
By only in formation light doping section, drain region, reduce the resistance between source, drain electrode, improve the performance of transistor, and, in the process forming described transistor, do not comprise extra mask fabrication, simplify technique, reduce cost.
Further, before carrying out described first ion implantation, the sidewall of described grid structure both sides defines side wall, and what enhance described grid structure blocks effect, prevent when follow-up injection ion, described ion enters in described Semiconductor substrate through described grid structure.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (10)
1. a formation method for transistor, comprising:
Semiconductor substrate is provided, described Semiconductor substrate has grid structure;
Carry out the first ion implantation, the angle of described first ion implantation is acute angle; And
Carry out the second ion implantation, the angle of described second ion implantation is obtuse angle, energy and the dosage of the first ion implantation described in the energy of described second ion implantation and dose ratio are high, high two orders of magnitude of the dosage of the first ion implantation described in the dose ratio of described second ion implantation;
The angle of described ion implantation refer to from the projection straight line of straight line on injection face at place, ion implantation direction rotate in the counterclockwise direction to the straight line parallel with ion implantation direction the angle of process.
2. the formation method of transistor as claimed in claim 1, is characterized in that, be also included in before carrying out the first ion implantation, the sidewall of described grid structure both sides forms side wall.
3. the formation method of transistor as claimed in claim 1, it is characterized in that, the energy range of described first ion implantation is 0.5keV to 100keV, and dosage range is 1E13/cm
2to 5E15/cm
2.
4. the formation method of transistor as claimed in claim 1, it is characterized in that, the energy range of described second ion implantation is 1keV to 200keV, and dosage range is 1E14/cm
2to 1E16/cm
2.
5. the formation method of transistor as claimed in claim 1, it is characterized in that, the scope of the angle of described first ion implantation is 45 ° to 88 °.
6. the formation method of transistor as claimed in claim 1, it is characterized in that, the scope of the angle of described second ion implantation is 92 ° to 135 °.
7. the formation method of transistor as claimed in claim 1, it is characterized in that, through described first ion implantation and described second ion implantation, the first adjacent light doping section and the first heavily doped region is formed in the described Semiconductor substrate of described grid structure side, described first light doping section is closer to described grid structure, and described first light doping section and described first heavily doped region are as the drain electrode of transistor.
8. the formation method of transistor as claimed in claim 7, it is characterized in that, the doping content scope of described first light doping section is 1E17/cm
3to 1E20/cm
3, the doping content scope of described first heavily doped region is 1E19/cm
3to 1E21/cm
3.
9. the formation method of transistor as claimed in claim 1, it is characterized in that, through described first ion implantation and described second ion implantation, the second heavily doped region is formed in the described Semiconductor substrate of described grid structure side, described second heavily doped region is as the source electrode of transistor, and the doping content scope of described second heavily doped region is 1E19/cm
3to 1E21/cm
3.
10. the formation method of transistor as claimed in claim 2, it is characterized in that, the material of described side wall comprises: silica, silicon nitride, silicon oxynitride, or its combination in any.
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| CN201110459401.XA CN103187251B (en) | 2011-12-31 | 2011-12-31 | The formation method of transistor |
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| CN201110459401.XA CN103187251B (en) | 2011-12-31 | 2011-12-31 | The formation method of transistor |
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| CN103187251B true CN103187251B (en) | 2015-11-25 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1146628A (en) * | 1995-06-02 | 1997-04-02 | 现代电子产业株式会社 | Method for forming junction in high speed EEPROM unit |
| US7105412B1 (en) * | 2005-03-22 | 2006-09-12 | United Microelectronics Corp. | Silicide process utilizing pre-amorphization implant and second spacer |
| US7355221B2 (en) * | 2005-05-12 | 2008-04-08 | International Business Machines Corporation | Field effect transistor having an asymmetrically stressed channel region |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW580729B (en) * | 2001-02-23 | 2004-03-21 | Macronix Int Co Ltd | Method of avoiding electron secondary injection caused by pocket implantation process |
| DE102008026213B3 (en) * | 2008-05-30 | 2009-09-24 | Advanced Micro Devices, Inc., Sunnyvale | Transistor e.g. n-channel metal oxide semiconductor transistor, manufacturing method, involves forming non-electrode material at side wall that is turned towards drain side of transistor |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1146628A (en) * | 1995-06-02 | 1997-04-02 | 现代电子产业株式会社 | Method for forming junction in high speed EEPROM unit |
| US7105412B1 (en) * | 2005-03-22 | 2006-09-12 | United Microelectronics Corp. | Silicide process utilizing pre-amorphization implant and second spacer |
| US7355221B2 (en) * | 2005-05-12 | 2008-04-08 | International Business Machines Corporation | Field effect transistor having an asymmetrically stressed channel region |
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