CN103166622A - Level shifter structure preventing generation of large current in input/output (IO) power-on process - Google Patents
Level shifter structure preventing generation of large current in input/output (IO) power-on process Download PDFInfo
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- CN103166622A CN103166622A CN2011104080406A CN201110408040A CN103166622A CN 103166622 A CN103166622 A CN 103166622A CN 2011104080406 A CN2011104080406 A CN 2011104080406A CN 201110408040 A CN201110408040 A CN 201110408040A CN 103166622 A CN103166622 A CN 103166622A
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Abstract
The invention discloses a level shifter structure preventing generation of a large current in an input/output (IO) power-on process. The level shifter structure preventing the generation of the large current in the IO power-on process comprises a first N-type field-effect tube, a second N-type field-effect tube, a P-type field-effect tube, a first inverter, a second inverter, a third inverter, a first coupling capacitor and a second coupling capacitor. A grid electrode of the first N-type field-effect tube is connected with an input end, a grid electrode of the second N-type field-effect tube is connected with the input end through the third inverter, and source electrodes of the two N-type field-effect tubes are grounded. An input end of the first inverter and an output end of the second inverter are connected with a drain electrode of the first N-type field-effect tube, and an output end of the first inverter and an input end of the second inverter are both connected with a drain electrode of the second N-type field-effect tube and a grid electrode of the P-type field-effect tube. A source electrode of the P-type field-effect tube is connected with an IO power source, one end of the first coupling capacitor is grounded, the other end of the first coupling capacitor is connected with the drain electrode of the first N-type field-effect tube, one end of the second coupling capacitor is connected with the IO power source, and the other end of the second coupling capacitor is connected with the grid electrode of the P-type field-effect tube. Not only is low-to-high level conversion achieved, but also the generation of the large current is restrained in the power-on process.
Description
Technical field
The present invention relates to the semiconductor integrated circuit field, particularly a kind of level translator structure that prevents from producing in the IO power up large electric current.
Background technology
Existing level translator, circuit structure comprise N-type field effect transistor N1, N2 as shown in Figure 1, and P type field effect transistor P1, P2, P3, the first buffer are connected input and are connected the output of described signal generator with inverter.The grid of N-type field effect transistor N1 is connected with the output of the first buffer, source electrode and substrate ground connection thereof.The grid of N-type field effect transistor N2 is connected with the output of inverter, source electrode and substrate ground connection thereof, and drain electrode is connected grid with the drain electrode of P type field effect transistor P2 respectively and is connected with P type field effect transistor P3.The grid of the drain electrode of N-type field effect transistor N1, P type field effect transistor P2 is connected drain electrode and is connected with the input of the second buffer respectively with P type field effect transistor P3, source electrode and the substrate thereof of P type field effect transistor P2, P3 connect respectively the IO power supply.The grid of P type field effect transistor P1 is connected with the output of the second buffer, and source electrode and substrate thereof connect the IO power supply, the AC signal after the conversion of drain electrode output voltage.As shown in Figure 1, VDDIO, VDD are respectively input and output power supply (being called for short the IO power supply) and core power (being called for short the core power supply), and wherein the IO power supply is the high tension apparatus power supply, and the core power supply is the low-voltage device power supply.
As shown in Figure 1, input signal DOUT is low voltage signal.When DOUT=VDD, N1 opens, and N2 closes, and the drain voltage of N1, N2 is respectively 0 and VDDIO.The P1 pipe is opened, and the PAD current potential is VDDIO, has realized the conversion of low-potential signal to high potential signal.If VDDIO first powers on than VDD, the grid of P1 pipe is in unknown levels, might float sky at 0 current potential, and the P1 pipe will be opened, and because the P1 pipe is driving tube, size is usually all very large, has large electric current and flows to PAD.
Summary of the invention
The technical problem to be solved in the present invention is to provide the level translator structure that produces large electric current in a kind of IO of preventing power up, can realize the conversion between high-low level, and can suppress the generation of large electric current in power up.
For solving the problems of the technologies described above, the level translator structure that prevents from producing in the IO power up large electric current provided by the invention comprises that level switch module and electric current suppress module; Described level switch module comprises the first N-type field effect transistor, the second N-type field effect transistor, P type field effect transistor, the first inverter, the second inverter and the 3rd inverter, and the 3rd inverter connects signal input part; Described electric current suppresses module and comprises the first coupling capacitance and the second coupling capacitance;
Wherein, the grid of described the first N-type field effect transistor connects signal input part, source electrode and substrate ground connection thereof;
The grid of described the second N-type field effect transistor connects the output of the 3rd inverter, source electrode and substrate ground connection thereof;
The input of described the first inverter be connected the output of inverter and all be connected with the drain electrode of the first N-type field effect transistor;
The output of described the first inverter be connected the input of inverter and all be connected with the drain electrode of the second N-type field effect transistor, all be connected with the grid of P type field effect transistor simultaneously;
The source electrode of described P type field effect transistor and substrate thereof connect the input and output power supply, and drain electrode is used for output;
Described the first coupling capacitance one end ground connection, the other end connects the drain electrode of the first N-type field effect transistor, the second coupling capacitance one termination input and output power supply, the other end connects the grid of P type field effect transistor;
Described the first inverter and the second inverter are by the input and output Power supply, and the 3rd inverter is powered by core power.
Further, described level translator structure also comprises the first buffer by the core power power supply, and described the first buffer connects input, and its output connects the grid of the first N-type field effect transistor.
Further, described level translator structure also comprises the second buffer, and the input of described the second buffer is connected with the drain electrode of the second N-type field effect transistor, and output is connected with the grid of P type field effect transistor.
The present invention can realize low to high level conversion, can effectively suppress again in power up the generation of large electric current, in process test IO can be with the scope of Current Control in standard in power up.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the circuit diagram of existing level translator;
Fig. 2 is the circuit diagram of level translator of the present invention.
Embodiment
The level translator structure that prevents from producing in the IO power up large electric current of the present invention as shown in Figure 2, comprises that level switch module and electric current suppress module; Described level switch module comprises the first N-type field effect transistor N1, the second N-type field effect transistor N2, P type field effect transistor P1, the first inverter INV1, the second inverter INV2 and the 3rd inverter, and the 3rd inverter connects input; Described electric current suppresses module and comprises the first coupling capacitance C1 and the second coupling capacitance C2.
The grid of described the first N-type field effect transistor N1 connects input, source electrode and substrate ground connection thereof.
The grid of described the second N-type field effect transistor N2 connects output, source electrode and the substrate ground connection thereof of the 3rd inverter.
The input of described the first inverter INV1 be connected the output of inverter INV2 and all be connected with the drain electrode of the first N-type field effect transistor N1.
The output of described the first inverter INV1 be connected the input of inverter INV2 and all be connected with the drain electrode of the second N-type field effect transistor N2, all be connected with the grid of P type field effect transistor P1 simultaneously.
Described P type field effect transistor P1 draws driving tube on being, its source electrode and substrate thereof connect the input and output power supply, and drain electrode is used for output.
Described the first coupling capacitance C1 one end ground connection, the other end connects the drain electrode of the first N-type field effect transistor N1, and the second coupling capacitance C2 one termination input and output power supply, the other end connect the grid of P type field effect transistor P1.
Described level translator structure also comprises input and output power vd DIO, core power VDD, the first buffer and the second buffer, input and output power vd DIO is the first inverter INV1, the second inverter INV2, the second coupling capacitance C2 and P type field effect transistor P1 power supply, and core power VDD is the first buffer and the power supply of the 3rd inverter.
Described the first buffer connects input, and its output connects the grid of the first N-type field effect transistor N1.
The input of described the second buffer is connected with the drain electrode of the second N-type field effect transistor N2, and output is connected with the grid of P type field effect transistor P1.
The normal operation of level translator structure, after namely VDDIO and VDD power on and complete:
When DOUT is high level from the low level upset, the first N-type field effect transistor N1 opens, the second N-type field effect transistor N2 closes, connecting line net0 place between the first coupling capacitance C1 and the first N-type field effect transistor N1 drain electrode pulls down to low level, and the connecting line net1 place between the second coupling capacitance C2 and the first inverter INV1 is turned to high level, draws driving tube P1 to close on this moment;
When DOUT is low level from the high level upset, the first N-type field effect transistor N1 closes, the second N-type field effect transistor N2 opens, connecting line net1 place between the second coupling capacitance C2 and the first inverter INV1 pulls down to low level, and the connecting line net0 place between the first coupling capacitance C1 and the first N-type field effect transistor N1 drain electrode is turned to high level, draws driving tube P1 unlatching on this moment.
The level translator structure is when power up, and core power vd D is produced by linear voltage regulator, and IO power vd DIO first powers on than core power vd D.In the VDDIO power up, to the capacitor C 2 of power supply and capacitor C over the ground 1 with net1, net0 is coupled to respectively certain current potential in two places, and the current potential at net 1 place is higher than the current potential at net0 place, the latch that forms by the first inverter INV1 and the second inverter INV2 amplifies pressure reduction, and net1 place and net0 place current potential reach respectively high level and low level.Therefore, on draw driving tube P1 to close, can not produce large electric current in power up.
Abovely by specific embodiment, the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that do not break away from the principle of the invention, those skilled in the art can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (3)
1. a level translator structure that prevents from producing in the IO power up large electric current, is characterized in that: comprise that level switch module and electric current suppress module; Described level switch module comprises the first N-type field effect transistor, the second N-type field effect transistor, P type field effect transistor, the first inverter, the second inverter and the 3rd inverter, and the 3rd inverter connects signal input part; Described electric current suppresses module and comprises the first coupling capacitance and the second coupling capacitance;
Wherein, the grid of described the first N-type field effect transistor connects signal input part, source electrode and substrate ground connection thereof;
The grid of described the second N-type field effect transistor connects the output of the 3rd inverter, source electrode and substrate ground connection thereof;
The input of described the first inverter be connected the output of inverter and all be connected with the drain electrode of the first N-type field effect transistor;
The output of described the first inverter be connected the input of inverter and all be connected with the drain electrode of the second N-type field effect transistor, all be connected with the grid of P type field effect transistor simultaneously;
The source electrode of described P type field effect transistor and substrate thereof connect the input and output power supply, and drain electrode is used for output;
Described the first coupling capacitance one end ground connection, the other end connects the drain electrode of the first N-type field effect transistor, the second coupling capacitance one termination input and output power supply, the other end connects the grid of P type field effect transistor;
Described the first inverter and the second inverter are by the input and output Power supply, and the 3rd inverter is powered by core power.
2. the level translator structure that prevents from the IO power up producing large electric current according to claim 1, it is characterized in that: described level translator structure also comprises the first buffer by the core power power supply, described the first buffer connects input, and its output connects the grid of the first N-type field effect transistor.
3. the level translator structure that prevents from the IO power up producing large electric current according to claim 1, it is characterized in that: described level translator structure also comprises the second buffer, the input of described the second buffer is connected with the drain electrode of the second N-type field effect transistor, and output is connected with the grid of P type field effect transistor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104080406A CN103166622A (en) | 2011-12-09 | 2011-12-09 | Level shifter structure preventing generation of large current in input/output (IO) power-on process |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011104080406A CN103166622A (en) | 2011-12-09 | 2011-12-09 | Level shifter structure preventing generation of large current in input/output (IO) power-on process |
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| CN103166622A true CN103166622A (en) | 2013-06-19 |
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| CN2011104080406A Pending CN103166622A (en) | 2011-12-09 | 2011-12-09 | Level shifter structure preventing generation of large current in input/output (IO) power-on process |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105049028A (en) * | 2015-08-20 | 2015-11-11 | 上海华力微电子有限公司 | Power-on detecting circuit for preventing uncertainty state of I/O circuit |
| CN109560807A (en) * | 2017-09-25 | 2019-04-02 | 英飞凌科技股份有限公司 | High-voltage level shifter circuit |
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| CN1292169A (en) * | 1998-10-23 | 2001-04-18 | 皇家菲利浦电子有限公司 | Level shifter |
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| US7030678B1 (en) * | 2004-02-11 | 2006-04-18 | National Semiconductor Corporation | Level shifter that provides high-speed operation between power domains that have a large voltage difference |
| US20060139086A1 (en) * | 2002-09-27 | 2006-06-29 | Alpha Microeletronics Gmbh | Circuit arrangement for bridging high voltages using a switching signal |
| CN1825766A (en) * | 2005-02-25 | 2006-08-30 | 艾格瑞系统有限公司 | Self-bypassing voltage level translator circuit |
| CN101174793A (en) * | 2006-10-26 | 2008-05-07 | 东部高科股份有限公司 | Level shifter having single voltage source |
| CN101547001A (en) * | 2008-03-27 | 2009-09-30 | 台湾积体电路制造股份有限公司 | Two voltage input level shifter with switches for core power off application |
| US20090256617A1 (en) * | 2008-04-11 | 2009-10-15 | Asic Advantage Inc. | Voltage level shifter |
| CN102160288A (en) * | 2008-12-29 | 2011-08-17 | 艾格瑞系统有限公司 | Voltage level translator circuit |
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2011
- 2011-12-09 CN CN2011104080406A patent/CN103166622A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1231082A (en) * | 1996-07-26 | 1999-10-06 | 罗姆美国有限公司 | Power-up detector for low power systems |
| CN1292169A (en) * | 1998-10-23 | 2001-04-18 | 皇家菲利浦电子有限公司 | Level shifter |
| US20060139086A1 (en) * | 2002-09-27 | 2006-06-29 | Alpha Microeletronics Gmbh | Circuit arrangement for bridging high voltages using a switching signal |
| CN1614674A (en) * | 2003-11-03 | 2005-05-11 | 联咏科技股份有限公司 | Voltage level converter |
| US7030678B1 (en) * | 2004-02-11 | 2006-04-18 | National Semiconductor Corporation | Level shifter that provides high-speed operation between power domains that have a large voltage difference |
| CN1825766A (en) * | 2005-02-25 | 2006-08-30 | 艾格瑞系统有限公司 | Self-bypassing voltage level translator circuit |
| CN101174793A (en) * | 2006-10-26 | 2008-05-07 | 东部高科股份有限公司 | Level shifter having single voltage source |
| CN101547001A (en) * | 2008-03-27 | 2009-09-30 | 台湾积体电路制造股份有限公司 | Two voltage input level shifter with switches for core power off application |
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| CN102160288A (en) * | 2008-12-29 | 2011-08-17 | 艾格瑞系统有限公司 | Voltage level translator circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105049028A (en) * | 2015-08-20 | 2015-11-11 | 上海华力微电子有限公司 | Power-on detecting circuit for preventing uncertainty state of I/O circuit |
| CN105049028B (en) * | 2015-08-20 | 2018-10-16 | 上海华力微电子有限公司 | A kind of power on detection circuit for preventing I/O circuits from not knowing state |
| CN109560807A (en) * | 2017-09-25 | 2019-04-02 | 英飞凌科技股份有限公司 | High-voltage level shifter circuit |
| US10348304B2 (en) | 2017-09-25 | 2019-07-09 | Infineon Technologies Ag | High-voltage level-shifter circuitry |
| CN109560807B (en) * | 2017-09-25 | 2023-03-10 | 英飞凌科技股份有限公司 | High voltage level shifter circuit |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140110 |
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Application publication date: 20130619 |