CN103152075A - Digital matching filter for WCDMA (wideband code division multiple access) communication - Google Patents
Digital matching filter for WCDMA (wideband code division multiple access) communication Download PDFInfo
- Publication number
- CN103152075A CN103152075A CN2013100549048A CN201310054904A CN103152075A CN 103152075 A CN103152075 A CN 103152075A CN 2013100549048 A CN2013100549048 A CN 2013100549048A CN 201310054904 A CN201310054904 A CN 201310054904A CN 103152075 A CN103152075 A CN 103152075A
- Authority
- CN
- China
- Prior art keywords
- road
- sequence
- module
- matched filter
- path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a digital matching filter for WCDMA (wideband code division multiple access) communication. An A/D (analog to digital) conversion module is used for carrying out sampling quantization on each collected sampling value, a serial/parallel conversion module is used for dividing samplings in former and later n times for a same code sheet to obtain data with an odd power and an even power sequences of a path I and a path Q, a matching filter module is used for carrying out data matching on the data with odd power and the even power sequences of the path I and the path Q through a Golay sequence correlator, the serial/parallel conversion module is used for recovering the data with the odd power and the even power sequences of the path I and the path Q output by the matching filter module into an original data sequences of the path I and the path Q, a quadratic sum calculation module is used for carrying out quadratic sum calculation on the original data sequences of the path I and the path Q, and a relative detection module is used for carrying out peak value detection on a result of the quadratic sum calculation of the original data sequences of the path I and the path Q output by the quadratic sum calculation module to realize synchronization of a main synchronization sequence; and hardware resource is reduced, a data processing speed is improved, a synchronous sequence in time slot synchronization of WCDMA communication system community searching is rapidly captured.
Description
Technical field
The invention belongs to digital signal processing technique field, relate in particular to a kind of digital matched filter for WCDMA communication.
Background technology
WCDMA adopts straight expansion pattern as a new technology, and carrier bandwidths is 5MHz, indoor transmissions speed can reach 2Mbit, the outdoor 384kbps that reaches, and it adopts the MCFDD dual-mode, with the GSM network, good compatibility and interoperability are arranged, be subject to the favor of various manufacturers.Communication under mine in recent years progressively replaces wire communication with radio communication, because the communication environment under mine is extremely disliked slightly, want to realize that radio communication must be optimized processing to the existing wireless communication system and could use, the WCDMA communication system is selection optimum in mine communication.
Do not have synchronous requirement in the WCDMA communication system between the base station, different frequency expansion sequences is used in adjacent base station.The advantage of base station asynchronous work is not need to rely on GPS as the timing standard between the base station, but travelling carriage will with base station communication just must first find target BS and with it settling time synchronous, so must search for the residential quarter, provide communication service with definite which cell base station, and synchronous with it.
The search of WCDMA residential quarter needs three steps, namely with the slot synchronization that the communication service cell base station is provided, frame synchronization with catch main scrambler.WCDMA travelling carriage cell search process is first to obtain slot synchronization on the shorter time, and then obtains frame synchronization on the long time, finally obtains the scrambler that use the residential quarter, place.So slot synchronization is a very crucial step in whole search procedure, dwindles the time of slot synchronization and just can dwindle search time.Each physical channel will realize that slot synchronization essence is the border that obtains each time slot.The Primary Synchronisation Code of all residential quarters is identical, and terminal knows its chip sequence in advance, therefore only need to just can detect, capture with performance matched filtering module preferably this main synchronizing sequence, thus the boundary of time slot of definite each physical channel.The complexity of Cell searching depends primarily on the complexity of the first step, so the complexity of matched filtering module has determined the complexity of Cell searching to a great extent.
The downhole wireless channel circumstance is extremely abominable, in the acquisition algorithm of main synchronizing sequence, requires mean acquisition time short as far as possible on the one hand, requires acquisition probability large as far as possible on the one hand.Traditional digital matched filter exists the characteristics that number of taps is numerous, hardware spending is huge, power consumption is huge, and structure can not satisfy the requirement of WCDMA system small area fast search.The multiplicaton addition unit number of the digital matched filter structure of the main synchronizing sequence of system is 256 * m, and the number of register is 256 * m, and wherein m is over-sampling rate.Obviously, this structure also increases sharply with increase multiplicaton addition unit and the register of sample rate, and data processing speed is reduced.
Summary of the invention
The invention provides a kind of digital matched filter for WCDMA communication, be intended to solve traditional digital matched filter, number of taps is numerous, hardware spending is huge, power consumption is huge, structure can not satisfy the requirement of WCDMA system small area fast search, simultaneously traditional digital matched filter structure also increases sharply with increase multiplicaton addition unit and the register of sample rate, the problem that data processing speed is reduced.
The object of the present invention is to provide a kind of digital matched filter for WCDMA communication, this digital matched filter comprises:
Each sampled value that gathers is carried out the A/D modular converter of sample quantization;
Be connected with described A/D modular converter, n the sampling in front and back that is used for the same chip of image data is carried out separates, obtain odd and the even sequence data on I road and Q road, the serial/parallel modular converter that odd and the even sequence data on the I road that obtains and Q road are exported;
Be connected with described serial/parallel modular converter, be used for receiving odd and the even sequence data on I road and the Q road of described serial/parallel modular converter output, the matched filtering module of odd and the even sequence data on the I road that receives and Q road being carried out Data Matching by the Golay sequence correlator;
Be connected with described matched filtering module, be used for the I road of described matched filtering module output is become original I road and Q circuit-switched data sequence with Q road odd with the even recovered data sequence, and the parallel/serial modular converter that original I road and Q circuit-switched data sequence are exported;
Be connected with described parallel/serial modular converter, be used for receiving original I road and the Q circuit-switched data sequence of described parallel/serial modular converter output, quadratic sum is asked on original I road and Q circuit-switched data sequence, and asked the quadratic sum module to what original I road and Q circuit-switched data sequence asked that the result of quadratic sum exports;
Be connected with the described quadratic sum module of asking, be used for asking the result of quadratic sum to carry out the peak value detection to the described original I road of quadratic sum module output and the Q circuit-switched data sequence asked, realize the coherent detection module that main synchronizing sequence is synchronous.
Further, be provided with a plurality of sub-matched filters in described matched filtering module, if carry out n secondary data sampling, need each chip samples value on I road and Q road is entered respectively a 2n in parallel sub-matched filter.
Further, the described quadratic sum module of asking adopts look-up method that original I road and Q circuit-switched data sequence are asked square, adopts the summation of exampleization quaternary rechoning by the abacus adder, the realization of utilization carry look ahead chain.
Further, it is described that to ask the quaternary rechoning by the abacus adder in the quadratic sum module be asynchronous serial rechoning by the abacus adder, adopting two weights is that 5 high pearl and 5 weights are 1 low pearl structure, a unit can represent that decimal range is 0-15, it is just in time a quarternary numerical representation scope, because square result is 24bit, adopt the exampleization statement to copy the adder unit of 6 quarternary full adders simultaneously, six quaternary adder units adopt the method for carry look ahead chain to carry out cascade.
Further, 2 samplings in the front and back of same chip being carried out when described serial/parallel modular converter separately, carry out 4bit when quantizing to each sampled value, namely 4bitI road and 4bit Q road are converted to parallel 4bit I road odd number sequence, 4bit I road even number sequence, 4bit Q road odd number sequence and 4bit Q road even number sequence, four tunnel sequences are entered respectively the matched filtering module carry out related operation, and convert result the Q road sequence of the I road sequence of 12bit and 12bit to through parallel/serial modular converter.
Further, the transfer function of described sub-matched filter is:
H(z
u)＝[1+z
-8+z
-1(1-z
-8)][1+z
-4+z
-2(1-z
-4)]；
H(z
v)＝(1+z
-1)[1-z
-6+z
-8+z
-14]+(1-z
-1)[z
-2-z
-4+z
-10+z
-12]。
Further, described coherent detection module adopts the bubbling comparison method, be that the correlation of adjacent moment compares higher value is deposited in register A, the position of higher value deposits register B in, constantly updates, until identical value occurs, whether the detection position differs the code length cycle, if so, just carry out one-time detection, both sides detect and just are considered as acquisition success continuously again.
Further, described matched filtering module mainly is made of delay unit and multiplicaton addition unit, and delay unit adopts d type flip flop to realize, multiplicaton addition unit adopts common taking advantage of to add module; Described matched filtering module realization is to the Golay sequence capturing, and sequence enters matched filter by input, be shifted to take advantage of to add, and with result output, when the Golay sequence is arranged by matched filter, matched filter output maximum 256.
digital matched filter for WCDMA communication provided by the invention, the A/D modular converter carries out sample quantization to each sampled value that gathers, serial/parallel modular converter separates n the sampling in front and back that the same chip of image data carries out, obtain odd and the even sequence data on I road and Q road, the matched filtering module is carried out Data Matching by the Golay sequence correlator to odd and the even sequence data on the I road that receives and Q road, parallel/serial modular converter becomes original I road and Q circuit-switched data sequence with the I road of matched filtering module output with Q road odd with the even recovered data sequence, ask the quadratic sum module to ask quadratic sum to original I road and Q circuit-switched data sequence, the coherent detection module asks the result of quadratic sum to carry out the peak value detection to original I road and the Q circuit-switched data sequence of asking the output of quadratic sum module, realize that main synchronizing sequence is synchronous, when the matched filtering module has reduced hardware resource, improve data processing speed, can catch rapidly synchronizing sequence in the slot synchronization of WCDMA communication system cell search, improved the probability of coherent detection, reduced largely false alarm probability.
Description of drawings
Fig. 1 is the structured flowchart of the digital matched filter that is used for WCDMA communication that provides of the embodiment of the present invention;
Fig. 2 is the structural representation of the matched filtering module that provides of the embodiment of the present invention;
Fig. 3 is that the coherent detection module that the embodiment of the present invention provides is carried out the flow chart that peak value detects.
In figure: 11, A/D modular converter; 12, serial/parallel modular converter; 13, matched filtering module; 131, sub-matched filter; 14, parallel/serial modular converter; 15, ask the quadratic sum module; 16, coherent detection module.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is described in further detail.Should be appreciated that specific embodiment described herein only in order to explaining the present invention, and be not used in and limit invention.
Fig. 1 shows the structure of the digital matched filter that is used for WCDMA communication that the embodiment of the present invention provides.For convenience of explanation, only show part related to the present invention.
This digital matched filter comprises:
Each sampled value that gathers is carried out the A/D modular converter 11 of sample quantization;
Be connected with A/D modular converter 11, n the sampling in front and back that is used for the same chip of image data is carried out separates, obtain odd and the even sequence data on I road and Q road, the serial/parallel modular converter 12 that odd and the even sequence data on the I road that obtains and Q road are exported;
Be connected with serial/parallel modular converter 12, be used for receiving odd and the even sequence data on I road and the Q road of serial/parallel modular converter 12 outputs, the matched filtering module 13 of odd and the even sequence data on the I road that receives and Q road being carried out Data Matching by the Golay sequence correlator;
Be connected with matched filtering module 13, be used for the I road of matched filtering module 13 outputs is become original I road and Q circuit-switched data sequence with Q road odd with the even recovered data sequence, and the parallel/serial modular converter 14 that original I road and Q circuit-switched data sequence are exported;
Be connected with parallel/serial modular converter 14, be used for receiving original I road and the Q circuit-switched data sequence of parallel/serial modular converter 14 outputs, quadratic sum is asked on original I road and Q circuit-switched data sequence, and asked quadratic sum module 15 to what original I road and Q circuit-switched data sequence asked that the result of quadratic sum exports;
Be connected with asking quadratic sum module 15, be used for asking the result of quadratic sum to carry out the peak value detection to original I road and the Q circuit-switched data sequence of asking 15 outputs of quadratic sum module, realize the coherent detection module 16 that main synchronizing sequence is synchronous.
In embodiments of the present invention, be provided with a plurality of sub-matched filters 131 in matched filtering module 13, if carry out n secondary data sampling, need each chip samples value on I road and Q road is entered respectively a 2n in parallel sub-matched filter 131.
In embodiments of the present invention, ask quadratic sum module 15 to adopt look-up methods that original I road and Q circuit-switched data sequence are asked square, adopt the summation of exampleization quaternary rechoning by the abacus adder, the realization of utilization carry look ahead chain.
In embodiments of the present invention, asking the quaternary rechoning by the abacus adder in quadratic sum module 15 is asynchronous serial rechoning by the abacus adder, adopting two weights is that 5 high pearl and 5 weights are 1 low pearl structure, a unit can represent that decimal range is 0-15, it is just in time a quarternary numerical representation scope, because square result is 24bit, adopt the exampleization statement to copy the adder unit of 6 quarternary full adders simultaneously, six quaternary adder units adopt the method for carry look ahead chain to carry out cascade.
In embodiments of the present invention, 2 samplings in the front and back of same chip being carried out when serial/parallel modular converter 12 separately, carry out 4bit when quantizing to each sampled value, namely 4bitI road and 4bit Q road are converted to parallel 4bit I road odd number sequence, 4bit I road even number sequence, 4bit Q road odd number sequence and 4bit Q road even number sequence, four tunnel sequences are entered respectively matched filtering module 13 carry out related operation, and convert result the Q road sequence of the I road sequence of 12bit and 12bit to through parallel/serial modular converter 14.
In embodiments of the present invention, the transfer function of sub-matched filter 131 is:
C
iBe by hierarchical sequence u, the v modulation forms, and u is layering Golay sequence u={1, and 1,1,1,1,1 ,-1 ,-1,1 ,-1,1 ,-1,1 ,-1 ,-1,1}, v={1,1,1 ,-1 ,-1,1 ,-1 ,-1,1,1,1 ,-1,1 ,-1,1,1}, C
16m+n=u
nv
m
H(z
u)＝[1+z
-8+z
-1(1-z
-8)][1+z
-4+z
-2(1-z
-4)]；
H(z
v)＝(1+z
-1)[1-z
-6+z
-8+z
-14]+(1-z
-1)[z
-2-z
-4+z
-10+z
-12]。
In embodiments of the present invention, coherent detection module 16 adopts the bubbling comparison method, be that the correlation of adjacent moment compares higher value is deposited in register A, the position of higher value deposits register B in, constantly updates, until identical value occurs, whether the detection position differs the code length cycle, if so, just carry out one-time detection, both sides detect and just are considered as acquisition success continuously again.
In embodiments of the present invention, described matched filtering module mainly is made of delay unit and multiplicaton addition unit, and delay unit adopts d type flip flop to realize, multiplicaton addition unit adopts common taking advantage of to add module; Described matched filtering module realization is to the Golay sequence capturing, and sequence enters matched filter by input, be shifted to take advantage of to add, and with result output, when the Golay sequence is arranged by matched filter, matched filter output maximum 256.
Below in conjunction with drawings and the specific embodiments, application principle of the present invention is further described.
, the purpose of this invention is to provide and a kind ofly reduce delay unit and multiplicaton addition unit based on the digital matched filter in the WCDMA communication of FPGA under this structure with not enough for the shortcoming of prior art, improve data processing speed.Mainly comprise following content:
(1) sampled data is separated through serial/parallel modular converter 12 n the sampling in front and back that same chip carries out, parallel Input matching filtration module 13;
(2) the data Golay sequence correlator of processing in (1) is carried out Data Matching, this matched filtering module 13 is developed new structure as shown in Figure 2 according to layering Golay sequence characteristic;
(3) ask quadratic sum module 15 to adopt look-up methods to ask square, exampleization quaternary rechoning by the abacus adder is adopted in summation, the realization of utilization carry look ahead chain;
(4) coherent detection module 16 is taked the neighboring and correlative value to carry out novel bubbling method and is relatively detected peak value, and the double method that correlation peak detected is carried out peak value and detected realization synchronously;
Should based on the digital matched filter in WCDMA of FPGA communication, comprise: serial/parallel modular converter 12, matched filtering module 13, parallel/serial modular converter 14, ask quadratic sum module 15, coherent detection module 16;
Serial/parallel modular converter 12 realizes that 2 samplings in front and back that same chip is carried out separate, each sampled value is carried out 4bit quantize, namely 4bitI road and 4bit Q road are converted to parallel 4bit I road odd number sequence and 4bit I road even number sequence and 4bit Q road odd number sequence and 4bit Q road even number sequence; Four tunnel sequences are entered respectively sub-matched filter 131 carry out related operation, and result is carried out the Q road sequence of the parallel/serial I road sequence that converts 12bit to and 12bit, if carry out n sampling, need 2n sub-matched filter 131, each chip samples value on I road and Q road is entered respectively a 2n in parallel sub-matched filter 131, simultaneously the two-way sequence is sent into and is asked quadratic sum module 15 to sue for peace, acquired results send into coherent detection module 16 carry out peak value detect realize main synchronizing sequence synchronously.
Matched filtering module 13 is one of major parts of the present invention, is the major effect time-delay, the part of speed and hardware consumption amount, sub-matched filter 131 ssystem transfer functions
C
iBe by hierarchical sequence u, the v modulation forms, and u is layering Golay sequence u={1, and 1,1,1,1,1 ,-1 ,-1,1 ,-1,1 ,-1,1 ,-1 ,-1,1}, v={1,1,1 ,-1 ,-1,1 ,-1 ,-1,1,1,1 ,-1,1 ,-1,1,1}, C
16m+n=u
nv
m,
Can improve transfer function according to the Golay sequence of layering, have:
H(z
u)＝[1+z
-8+z
-1(1-z
-8)][1+z
-4+z
-2(1-z
-4)]；
H(z
v)＝(1+z
-1)[1-z
-6+z
-8+z
-14]+(1-z
-1)[z
-2-z
-4+z
-10+z
-12]。
The present invention's 4 parallel sub-matched filters 131 of rear employing of considering to sample according to the characteristics of WCDMA system Primary Synchronisation Code sequence, improve as shown in Figure 2 traditional structure.
In the present invention, the correlation detection principle of coherent detection module 16 is novel bubbling comparison method, be that the correlation of adjacent moment compares higher value is deposited in register A, the position of higher value deposits register B in, constantly updates, until identical value occurs, whether the detection position differs the code length cycle, if just carry out one-time detection, both sides detect and just are considered as acquisition success continuously again, and specific algorithm as shown in Figure 3, improve the probability of coherent detection, reduced false alarm probability.
In a word, improve data processing speed in the time of this matched filtering module 13 structure decrease hardware resource, when simplifying the structure, can catch rapidly synchronizing sequence in the slot synchronization of WCDMA communication system small area search.
The present invention is based on FPGA and realize, realize this function with the VHDL language programming, mainly comprise serial/parallel modular converter 12, matched filtering module 13, serial/parallel modular converter 12, ask quadratic sum module 15, coherent detection module 16;
The present invention adopts common A/D modular converter 11, and signal carries out sample quantization through A/D modular converter 11, considers to choose that 4bit quantizes and 2 times of over-samplings describe.
Serial/parallel conversion unit after sampling the odd of data and even separately, odd and the even sequence on I road and Q road enter respectively sub-matched filter 131.
Matched filtering module 13 is key components of the present invention, analyzes the Golay sequence signature of layering, and traditional digital matched filter structure is improved.As shown in Figure 2.Z
-iThe expression delay unit, the present invention takes 2 times of over-samplings to describe as example take data, owing to taking 2 samplings, thus I road and Q circuit-switched data each need two sub-matched filters 131, (if adopt the n sampling, just needing 2n sub-matched filter 131).The present invention adopts the logical multiplexing technology, with a digital matched filter carry out 2n time multiplexing, hardware area can be reduced, the impact of the time that over-sampling rate catches main synchronizing sequence can greatly be reduced when this structure improves acquisition probability by high sampling rate.
Serial/parallel modular converter 12 reverts to the original order data to odd and the even data of filter output, and when adopting 4bit to quantize, Output rusults is the 12bit data, sends into and asks quadratic sum module 15.
Asking quadratic sum module 15 is also the critical component that affects data processing speed, and the present invention uses the method for secondary look-up table to ask quadratic sum, and a square result is pre-deposited in RAM, tables look-up and reads a square result, input summer.
16 pairs of coherent detection modules ask the data of quadratic sum module 15 outputs to detect, signal when input signal confirmation of peak detector output during greater than a certain threshold value, confirm that namely list entries synchronizes with local code, coherent detection concrete grammar flow chart of the present invention as shown in Figure 3, adopt continuous several times peak value decision method, sequence difference between two minor peaks is that a pseudo-code is thought acquisition success during the cycle, and this kind method can reduce false alarm probability largely.
the digital matched filter that is used for WCDMA communication that the embodiment of the present invention provides, each sampled value that 11 pairs of A/D modular converters gather is carried out sample quantization, serial/parallel modular converter 12 separates n the sampling in front and back that the same chip of image data carries out, obtain odd and the even sequence data on I road and Q road, matched filtering module 13 is carried out Data Matching by the Golay sequence correlator to odd and the even sequence data on the I road that receives and Q road, parallel/serial modular converter 14 becomes original I road and Q circuit-switched data sequence with the I road of matched filtering module 13 output with Q road odd with the even recovered data sequence, ask 15 pairs of original I roads of quadratic sum module and Q circuit-switched data sequence to ask quadratic sum, 16 pairs of coherent detection modules ask the original I road of quadratic sum module 15 outputs and Q circuit-switched data sequence to ask the result of quadratic sum to carry out the peak value detection, realize that main synchronizing sequence is synchronous, when matched filtering module 13 has reduced hardware resource, improve data processing speed, can catch rapidly synchronizing sequence in the slot synchronization of WCDMA communication system cell search, improved the probability of coherent detection, reduced largely false alarm probability.
These are only preferred embodiment of the present invention, not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (8)
1. a digital matched filter that is used for WCDMA communication, is characterized in that, this digital matched filter comprises:
Each sampled value that gathers is carried out the A/D modular converter of sample quantization;
Be connected with described A/D modular converter, n the sampling in front and back that is used for the same chip of image data is carried out separates, obtain odd and the even sequence data on I road and Q road, the serial/parallel modular converter that odd and the even sequence data on the I road that obtains and Q road are exported;
Be connected with described serial/parallel modular converter, be used for receiving odd and the even sequence data on I road and the Q road of described serial/parallel modular converter output, the matched filtering module of odd and the even sequence data on the I road that receives and Q road being carried out Data Matching by the Golay sequence correlator;
Be connected with described matched filtering module, be used for the I road of described matched filtering module output is become original I road and Q circuit-switched data sequence with Q road odd with the even recovered data sequence, and the parallel/serial modular converter that original I road and Q circuit-switched data sequence are exported;
Be connected with described parallel/serial modular converter, be used for receiving original I road and the Q circuit-switched data sequence of described parallel/serial modular converter output, quadratic sum is asked on original I road and Q circuit-switched data sequence, and asked the quadratic sum module to what original I road and Q circuit-switched data sequence asked that the result of quadratic sum exports;
Be connected with the described quadratic sum module of asking, be used for asking the result of quadratic sum to carry out the peak value detection to the described original I road of quadratic sum module output and the Q circuit-switched data sequence asked, realize the coherent detection module that main synchronizing sequence is synchronous.
2. digital matched filter as claimed in claim 1, it is characterized in that, be provided with a plurality of sub-matched filters in described matched filtering module, if carry out n secondary data sampling, need each chip samples value on I road and Q road is entered respectively a 2n in parallel sub-matched filter.
3. digital matched filter as claimed in claim 1, is characterized in that, the described quadratic sum module of asking adopts look-up method that original I road and Q circuit-switched data sequence are asked square, adopts the summation of exampleization quaternary rechoning by the abacus adder, the realization of utilization carry look ahead chain.
4. digital matched filter as claimed in claim 1, it is characterized in that, it is described that to ask the quaternary rechoning by the abacus adder in the quadratic sum module be asynchronous serial rechoning by the abacus adder, adopting two weights is that 5 high pearl and 5 weights are 1 low pearl structure, a unit can represent that decimal range is 0-15, it is just in time a quarternary numerical representation scope, simultaneously because square result is 24bit, adopt the exampleization statement to copy the adder unit of 6 quarternary full adders, six quaternary adder units adopt the method for carry look ahead chain to carry out cascade.
5. digital matched filter as claimed in claim 1, it is characterized in that, 2 samplings in the front and back of same chip being carried out when described serial/parallel modular converter separately, carry out 4bit when quantizing to each sampled value, namely 4bitI road and 4bit Q road are converted to parallel 4bit I road odd number sequence, 4bit I road even number sequence, 4bit Q road odd number sequence and 4bit Q road even number sequence, four tunnel sequences are entered respectively the matched filtering module carry out related operation, and convert result the Q road sequence of the I road sequence of 12bit and 12bit to through parallel/serial modular converter.
6. digital matched filter as claimed in claim 1, is characterized in that, the transfer function of described sub-matched filter is:
C
iBe by hierarchical sequence u, the v modulation forms, and u is layering Golay sequence u={1, and 1,1,1,1,1 ,-1 ,-1,1 ,-1,1 ,-1,1 ,-1 ,-1,1}, v={1,1,1 ,-1 ,-1,1 ,-1 ,-1,1,1,1 ,-1,1 ,-1,1,1}, C
16m+n=u
nv
m
H(z
u)＝[1+z
-8+z
-1(1-z
-8)][1+z
-4+z
-2(1-z
-4)]；
H(z
v)＝(1+z
-1)[1-z
-6+z
-8+z
-14]+(1-z
-1)[z
-2-z
-4+z
-10+z
-12]。
7. digital matched filter as claimed in claim 1, it is characterized in that, described coherent detection module adopts the bubbling comparison method, and namely the correlation of adjacent moment compares higher value is deposited in register A, and the position of higher value deposits register B in, constantly update, until identical value occurs, whether the detection position differs the code length cycle, if, just carry out one-time detection, both sides detect and just are considered as acquisition success continuously again.
8. digital matched filter as claimed in claim 1, is characterized in that, described matched filtering module mainly is made of delay unit and multiplicaton addition unit, and delay unit adopts d type flip flop to realize, multiplicaton addition unit adopts common taking advantage of to add module; Described matched filtering module realization is to the Golay sequence capturing, and sequence enters matched filter by input, be shifted to take advantage of to add, and with result output, when the Golay sequence is arranged by matched filter, matched filter output maximum 256.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100549048A CN103152075A (en) | 2013-02-04 | 2013-02-04 | Digital matching filter for WCDMA (wideband code division multiple access) communication |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100549048A CN103152075A (en) | 2013-02-04 | 2013-02-04 | Digital matching filter for WCDMA (wideband code division multiple access) communication |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103152075A true CN103152075A (en) | 2013-06-12 |
Family
ID=48549971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013100549048A Pending CN103152075A (en) | 2013-02-04 | 2013-02-04 | Digital matching filter for WCDMA (wideband code division multiple access) communication |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103152075A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105450255A (en) * | 2015-11-06 | 2016-03-30 | 天津津航计算技术研究所 | High-efficiency high-reliability burst communication method |
| CN105496702A (en) * | 2016-02-25 | 2016-04-20 | 滕艳玲 | Surgical nursing dressing-changing device |
| CN106203855A (en) * | 2016-07-15 | 2016-12-07 | 西南石油大学 | A kind of drilling platforms information management system |
| CN106302680A (en) * | 2016-08-06 | 2017-01-04 | 内蒙古大学 | A kind of data based on Internet of Things display background system |
| CN106296343A (en) * | 2016-08-01 | 2017-01-04 | 王四春 | A kind of e-commerce transaction monitoring method based on the Internet and big data |
| CN106446249A (en) * | 2016-10-13 | 2017-02-22 | 刘海玲 | Geographic information acquisition method and geographic information acquisition system |
| CN106453274A (en) * | 2016-09-22 | 2017-02-22 | 华北水利水电大学 | Intelligent data security management control system and control method |
| CN106430586A (en) * | 2016-10-27 | 2017-02-22 | 中国人民解放军后勤工程学院 | Enhanced nitrogen-removing A/O flow-separating biochemical pond |
| CN106647399A (en) * | 2016-12-26 | 2017-05-10 | 北华大学 | Control system and method for intelligent English learning machine |
| CN106779146A (en) * | 2016-11-15 | 2017-05-31 | 广州铁路职业技术学院 | A kind of tourism service system for providing recommendation tourism route |
| CN107067273A (en) * | 2016-11-30 | 2017-08-18 | 四川省巴食巴适电子商务有限公司 | Control system and method with promoting is issued based on internet electronic business information |
| CN108366420A (en) * | 2018-02-02 | 2018-08-03 | 东南大学 | A kind of synchronization detecting method based on Golay complementary series |
| CN113098441A (en) * | 2021-03-30 | 2021-07-09 | 太原理工大学 | Electromagnetic wave optimization model based on particle filter algorithm |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1286587A (en) * | 1999-11-12 | 2001-03-07 | 深圳市中兴通讯股份有限公司 | Time slot synchronizer in regional search for WCDMA system |
| US6345069B1 (en) * | 1998-10-16 | 2002-02-05 | Texas Instruments Incorporated | Simplified cell search scheme for first and second stage |
| CN1347218A (en) * | 2001-10-22 | 2002-05-01 | 信息产业部电信传输研究所 | Method and device for implementing multipath search in WCDMA down link |
| CN1347217A (en) * | 2001-10-22 | 2002-05-01 | 信息产业部电信传输研究所 | Configurable W-CDMA time slot synchronization matched filter device |
| WO2003007519A1 (en) * | 2001-07-11 | 2003-01-23 | Linkair Communications, Inc. | A match filter for code division multiple access communication system |
| WO2006079949A1 (en) * | 2005-01-31 | 2006-08-03 | Nxp B.V. | Method and apparatus for implementing matched filters in a wireless communication system |
| US20070036122A1 (en) * | 2005-08-15 | 2007-02-15 | Research In Motion Limited | Joint Space-Time Optimum Filters (JSTOF) for Interference Cancellation |
| CN101674050A (en) * | 2009-09-21 | 2010-03-17 | 清华大学 | Time-domain parallel digital demodulation system |
-
2013
- 2013-02-04 CN CN2013100549048A patent/CN103152075A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6345069B1 (en) * | 1998-10-16 | 2002-02-05 | Texas Instruments Incorporated | Simplified cell search scheme for first and second stage |
| CN1286587A (en) * | 1999-11-12 | 2001-03-07 | 深圳市中兴通讯股份有限公司 | Time slot synchronizer in regional search for WCDMA system |
| WO2003007519A1 (en) * | 2001-07-11 | 2003-01-23 | Linkair Communications, Inc. | A match filter for code division multiple access communication system |
| CN1347218A (en) * | 2001-10-22 | 2002-05-01 | 信息产业部电信传输研究所 | Method and device for implementing multipath search in WCDMA down link |
| CN1347217A (en) * | 2001-10-22 | 2002-05-01 | 信息产业部电信传输研究所 | Configurable W-CDMA time slot synchronization matched filter device |
| WO2006079949A1 (en) * | 2005-01-31 | 2006-08-03 | Nxp B.V. | Method and apparatus for implementing matched filters in a wireless communication system |
| US20070036122A1 (en) * | 2005-08-15 | 2007-02-15 | Research In Motion Limited | Joint Space-Time Optimum Filters (JSTOF) for Interference Cancellation |
| CN101674050A (en) * | 2009-09-21 | 2010-03-17 | 清华大学 | Time-domain parallel digital demodulation system |
Non-Patent Citations (5)
| Title |
|---|
| 侯山民: "《基于匹配滤波的直扩同步系统的研究与实现》", 《大连海事大学硕士学位论文》, 15 October 2012 (2012-10-15) * |
| 刘兆霆: "《WCDMA系统同步序列的研究及匹配滤波的FPGA实现》", 《大连海事大学硕士学位论文》, 15 December 2005 (2005-12-15) * |
| 徐阳扬,杨银堂,周端,弥晓华: "《异步算盘加法器设计》", 《西北大学学报（自然科学版）》, vol. 41, no. 4, 31 August 2011 (2011-08-31) * |
| 牛凯,王双全,吴伟陵: "《一种新颖的W-CDMA主同步信道匹配滤波器》", 《电子学报》, vol. 30, no. 10, 31 October 2002 (2002-10-31) * |
| 郭经红,尤肖虎,程时昕: "《WCDMA系统中匹配滤波器的FPGA实现》", 《通信学报》, vol. 22, no. 1, 31 January 2001 (2001-01-31) * |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105450255A (en) * | 2015-11-06 | 2016-03-30 | 天津津航计算技术研究所 | High-efficiency high-reliability burst communication method |
| CN105496702A (en) * | 2016-02-25 | 2016-04-20 | 滕艳玲 | Surgical nursing dressing-changing device |
| CN106203855A (en) * | 2016-07-15 | 2016-12-07 | 西南石油大学 | A kind of drilling platforms information management system |
| CN106296343A (en) * | 2016-08-01 | 2017-01-04 | 王四春 | A kind of e-commerce transaction monitoring method based on the Internet and big data |
| CN106302680A (en) * | 2016-08-06 | 2017-01-04 | 内蒙古大学 | A kind of data based on Internet of Things display background system |
| CN106453274A (en) * | 2016-09-22 | 2017-02-22 | 华北水利水电大学 | Intelligent data security management control system and control method |
| CN106446249A (en) * | 2016-10-13 | 2017-02-22 | 刘海玲 | Geographic information acquisition method and geographic information acquisition system |
| CN106430586A (en) * | 2016-10-27 | 2017-02-22 | 中国人民解放军后勤工程学院 | Enhanced nitrogen-removing A/O flow-separating biochemical pond |
| CN106779146A (en) * | 2016-11-15 | 2017-05-31 | 广州铁路职业技术学院 | A kind of tourism service system for providing recommendation tourism route |
| CN107067273A (en) * | 2016-11-30 | 2017-08-18 | 四川省巴食巴适电子商务有限公司 | Control system and method with promoting is issued based on internet electronic business information |
| CN106647399A (en) * | 2016-12-26 | 2017-05-10 | 北华大学 | Control system and method for intelligent English learning machine |
| CN108366420A (en) * | 2018-02-02 | 2018-08-03 | 东南大学 | A kind of synchronization detecting method based on Golay complementary series |
| CN108366420B (en) * | 2018-02-02 | 2020-08-11 | 东南大学 | Synchronous detection method based on Golay complementary sequence |
| CN113098441A (en) * | 2021-03-30 | 2021-07-09 | 太原理工大学 | Electromagnetic wave optimization model based on particle filter algorithm |
| CN113098441B (en) * | 2021-03-30 | 2023-01-24 | 太原理工大学 | Electromagnetic wave optimization model based on particle filter algorithm |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103152075A (en) | Digital matching filter for WCDMA (wideband code division multiple access) communication | |
| CN101969319A (en) | Universal digital dual modulation-demodulation technology in wireless communication | |
| CN108366420B (en) | Synchronous detection method based on Golay complementary sequence | |
| CN112187338B (en) | Two-stage processing interference cancellation system and method for asynchronous CDMA system | |
| CN101924577B (en) | Time slot synchronization method for resisting sampling clock frequency deviation in WCDMA (Wideband Code Division Multiple Access) system | |
| CN105049081A (en) | Long-code spread spectrum signal rapid capturing method adaptive to high dynamic environment | |
| CN101360087B (en) | Low-complexity implementing method and apparatus for base-band forming SRRC digital filter | |
| CN102123431B (en) | Time slot synchronizing and time slot power detecting methods and systems applied to global system for mobile communication (GSM) | |
| CN101938347B (en) | Timing error extraction device and method | |
| CN108347259A (en) | A kind of MSK demodulation methods based on matched filter | |
| CN102137484B (en) | Method and device for measuring RSCP (received signal code power) of adjacent cells | |
| CN205336269U (en) | Frequency hopping transceiver on on -vehicle net platform | |
| CN100377504C (en) | First-step search of initial zone in time division synchronizing CDMA system | |
| CN100555894C (en) | Multipath searching method in a kind of cdma system and device | |
| CN105471788A (en) | Low delay interpretation method and apparatus for DVBS2 signal | |
| CN101002407A (en) | Sample acquisition timing adjustment | |
| CN103841074A (en) | Ultra wideband receiver synchronization method based on FPGA parallel processing | |
| CN107395541B (en) | The signal-timing method and system of continuous phase modulated signal | |
| CN103023528B (en) | A kind of TD-SCDMA time-division switching search system of efficient stable and method | |
| CN202268895U (en) | Data compression transmission system | |
| CN101917781A (en) | Method and device for achieving digital down-conversion function of RRU (Remote Radio-frequency Unit) uplink chain path | |
| CN1595834A (en) | Method and apparatus for initial synchronization in CDMA mobile communication system | |
| CN112600784A (en) | Large frequency offset bit synchronization method based on quadratic differential correlation | |
| CN101888267A (en) | Base band receiver of base station in digital wireless trunking communication system based on TDMA (Time Division Multiple Address) technique and signal processing method thereof | |
| CN107276654A (en) | Signal processing method and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20130612 |