CN1347217A - Configurable W-CDMA time slot synchronization matched filter device - Google Patents
Configurable W-CDMA time slot synchronization matched filter device Download PDFInfo
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Abstract
A configurable match filter with W-CDMA time slot synchronization is disclosed for higher flexibility and robustness of match filter. It is based on a basic match filter with 8-class operating and 255XN-order delay. For the input data and the outupt of each operating class, a decreament of bits is used. The number of bits for input data is fixed for adapting the variation of input signal intensity. For the result of intermediate operating, the number of bits is not increased, resulting in lower complexity and higher match performance.
Description
(1) technical field:
The invention belongs to field of mobile communication, WCDMA (Wideband Code Division Multiple Access (WCDMA)) system of FDD (Frequency Division Duplexing (FDD)) pattern in the 3 g mobile communication system that relates in particular to is specifically related to the Cell searching technology of MT in the WCDMA system (portable terminal).
(2) technical background:
In Wideband Code Division Multiple Access (WCDMA) (WCDMA) system, communicating by letter between travelling carriage and base station is based upon on the basis of down-going synchronous, be the timing information that travelling carriage need obtain the base station, comprise chip (chip) regularly, time slot (slot) regularly, frame (frame) regularly and superframe (super frame) regularly.In the WCDMA system, the regularly synchronous foundation in travelling carriage and base station comprises the process in two stages, and first stage is an initial synchronisation, obtains the base station at this stage travelling carriage and comprises the thick timing regularly of chip timings, slot timing and frame; Second stage is a precise synchronization, and accurate regularly tracking is carried out in the thick timing that travelling carriage obtained according to the initial synchronisation stage, and obtains superframe regularly.Initial synchronization is called Cell searching (cellsearch) in WCDMA, this process is divided into three steps, at first obtain slot timing according to descending primary synchronization channel (PSCH), obtain frame regularly according to descending auxiliary synchronization channel (SSCH) then, obtain descending main scrambling code information according to Common Pilot Channel (CPICH) at last.The present invention is directed to that first step master synchronization acquistion has provided the synchronous matched filter device of a kind of configurable master in the Cell searching.
The Primary Synchronisation Code word that sends length in the primary synchronization channel and be 256chip is used for main synchronization acquistion, and this code word sends in the time at the initial 256chip of each time slot (length is 2560chip).By to the catching of Primary Synchronisation Code word phase place, travelling carriage can obtain the slot timing of base station.To slightly generally can realizing synchronously of this sequence phase by two kinds of methods: the one, correlator bank, promptly relevant with list entries on out of phase by a plurality of correlators, obtain the result from the correlated results judgement; The 2nd, matched filter is promptly done matched filtering with filter and list entries that an impulse response is known synchronizing sequence, obtains phase information from the matched filtering result judgement that provides continuously.Consider that main synchronizing sequence length is 256 among the WCDMA, and the initial phase distribution is 2560chip, it is excessive if serial search is then delayed time to adopt correlator method, if parallel search realizes that then scale is excessive, then in the search time-delay greater advantage is arranged with matched-filter approach.But traditional matched filter memory cell, arithmetic element scale are all bigger, for the Primary Synchronisation Code matched filter of 1/Nchip precision (N is a positive integer), only need the storage depth of 256 * N; For the Primary Synchronisation Code word of 256chip length, whenever obtain the weighted sum computing that a matching result need carry out 256 data.Fortunately, we can reduce to 13 to the arithmetic element that obtains a matching result according to the particularity of Primary Synchronisation Code, greatly reduce the scale and the complexity of realization, and as shown in Figure 1, wherein Dn represents the time-delay memory cell of n level.Can see, under such structure,, only need 256 * N memory cell and 13 arithmetic elements (adding/subtracter), greatly reduce the complexity of computing and the physics scale of realization for the synchronous matched filter device of the master of 1/Nchip precision.Can see from this structure, each matching result need be through 8 grades arithmetic element, realize for circuit, every data bits will increase by one through once adding/subtract computing, if do not do any processing like this, every grade of computing increases by one, end product increases by 8 than entry data, and one side causes a back level arithmetic element scale to strengthen thus, makes that on the other hand grade memory cell that needs is big more more backward.And from the autocorrelation performance of Primary Synchronisation Code word, the amplitude ratio of its peak-peak and maximum secondary lobe is 4, and coupling output is the result do not need to represent with too high figure place.We can reduce the scale of memory cell and arithmetic element by the cut position in the calculating process like this, and being unlikely to simultaneously has tangible loss to performance.
Take all factors into consideration the influence of above factor, the present invention proposes the synchronous matched filter device of a kind of configurable WCDMA master, reach the purpose that under less realization scale, realizes the synchronous matched filtering of high-performance master flexibly.
(3) summary of the invention:
Apparatus of the present invention technical scheme is as follows:
As shown in Figure 1, apparatus of the present invention are a configurable time slot synchronization matched filter, comprise 102 two modules of matched filter 101 and parameter control device, the input data are through providing the matched filtering result of Primary Synchronisation Code behind the matched filter, the external parameter configuration data comprises the control of input data processing and the processing controls of matched filter inner stages operation result by the characteristic of parameter control device control matched filter.
Because slot synchronization is by being that the matched filtering of 256chip is carried out to length, therefore for the matched filter of 1/Nchip precision, needs the time-delay memory cell of 256 * N level at least.The data of every 1/Nchip output can be regarded as 256 inputs data and the relevant result of local Primary Synchronisation Code word, and circuit visible and that the supporting needs of memory cell are fairly large is finished the related operation of 256 length in the time of 1/Nchip.In order to reduce the scale of arithmetic section, apparatus of the present invention list of references [1] has adopted a kind of matched filter structure based on 8 grades of arithmetic elements, as shown in Figure 2.Accompanying drawing 2 has provided the basic structure block diagram of this matched filter.As shown in the figure, this matched filter is combined by delay unit 201, coefficient multiplication unit 202, adder unit 203 and subtrator 204.Wherein delay unit Dn realizes the n of input signal is clapped delay function, and accompanying drawing 3 has provided the internal structure that n claps delay unit, and a visible n claps delay unit and is made up of the delayer D1 serial of a bat of n time-delay; Coefficient multiplication unit and corresponding positive-negative coefficient make the impulse of this filter should be reverse Primary Synchronisation Code word mutually; Adder unit and subtrator cooperate delay unit and coefficient multiplication unit to guarantee that the correct impulse of filter is corresponding on the one hand, play main computing effect simultaneously in the matched filtering to the input data.
Can see from Filter Structures, the input data obtain the matched filtering result after through the time-delay memory cell of 8 grades of different umber of beats and arithmetic element, if do not consider the choice of data bits, when being input as M bit signed number, every process one-level arithmetic element data bits increases 1, exports the result at last and is the M+8 bit.The increase of data bits makes the memory space change that needs circuit scale big, arithmetic element increase on the one hand, causes the realization scale of circuit to increase, because the data bits of participation computing increases, the reliably working speed of circuit is descended on the other hand.Therefore, in apparatus of the present invention, we have taked such processing method, the M Bit data of input is treated to bit according to the size of useful signal stores computing for the back level, operation result to each grade in 8 grades of computings carries out the conversion of N+1 Bit data to the N Bit data, the storage data and the operation result that have guaranteed each grade like this are the N Bit data, have controlled whole unit scale, have guaranteed the speed of work.Wherein the processing of the processing of input signal and every grade of operation result has all been adopted the method for configurable parameter, the flexibility that had both improved this matched filter, the acquisition for unfailing performance provides assurance again.
Input data processing unit and computing post-processing unit at different levels have been hidden in the accompanying drawing 3.The input data processing unit is in after the input data, before first storage, the arithmetic element.Accompanying drawing 4 has provided the structured flowchart of input data processing unit, mainly comprises the transducer 301 of a M bit to the N bit.The configuration parameter 1 that this transducer provides according to the parameter control device is realized a kind of conversion of input M Bit data to the N Bit data.Under the condition of M 〉=N, configuration parameter 1 total M-N+1 kind is selected, and a kind of feasible conversion regime is:
When configuration parameter 1 is chosen as L between 0～M-N, if the bit sequence of input M Bit data from a high position to the low level is M-1 to 0, then to making progress carry according to the principle that rounds up after, casts out 0 bit wherein hanging down L-1, if high M is the sign bit expansion to the M-L-N bit then casts out, obtain the output result of N bit, if high M to the not expansion of full is-symbol position of M-L-N bit, then obtains the N bit dateout of amplitude peak according to input data symbol position.
The processing unit of middle operation results at different levels is positioned at each and adds/subtracter after, accompanying drawing 4 has provided its structured flowchart, mainly comprises the transducer 302 of a N+1 bit to the N bit.The configuration parameter i that this transducer provides according to the parameter control device realizes the conversion of input N+1 Bit data to the N Bit data.This configuration parameter has 2 kinds of values and selects, respectively representative:
A) lowest order of input data is got high N bit after doing the operation that rounds up;
B) whether be that low N bit or input N bit are got in sign bit expansion decision according to input data highest order
Maximum (little) value.
Beneficial effect of the present invention: the synchronous matched filter device of configurable W-CDMA master that the present invention describes has adopted one 8 grades storage computing structures, reduced the scale of arithmetic element, the bit number processing of falling of falling bit number processing and operation results at different levels to the input data makes the storage size of whole device obtain effective control, has reduced the scale of arithmetic element simultaneously.The parameter configurability that the bit process unit falls in each data makes whole device have very big flexibility, provides assurance for obtaining of optimum Match filtering performance under certain realization scale simultaneously.
(4) description of drawings:
Fig. 1 is configurable time slot synchronization matched filter device structure chart;
Fig. 2 is the matched filter structure chart;
Fig. 3 claps the delay unit structure chart for n;
Fig. 4 is input data processing unit structure chart;
Fig. 5 is intermediate operations result treatment cellular construction figure;
Fig. 6 is the application of configurable time slot synchronization matched filter device in the W-CDMA travelling carriage.
(5) embodiment:
Fig. 6 has provided the application example of apparatus of the present invention in the W-CDMA travelling carriage.In this example, analog signal that antenna receives through radio frequency front-end device 401 eh, obtain the baseband sampling signal of W-CDMA down link behind A/D converter 402 and the filter 403, this signal is through obtaining the matching result to the Primary Synchronisation Code word behind the configurable time slot synchronization matched filter 404, slot synchronization decision device 405 provides the judgement of slot synchronization by the analysis to matching result, finishes the slot synchronization process.
Claims (6)
1. configurable WCDMA time slot synchronization matched filter device is characterized in that: comprise matched filter (101) and parameter control device (102); Wherein matched filter is finished the matched filtering to the WCDMA master sync signal, and the control of parameter control device is configured the parameters of matched filter, adapts to different applied environments.
2. configurable WCDMA time slot synchronization matched filter device as claimed in claim 1 is characterized in that: it is the matched filtering of 256 WCDMA Primary Synchronisation Code word that described matched filter adopts the structure of 8 grades of time-delay groups, 13 arithmetic elements to realize length.
3. configurable WCDMA time slot synchronization matched filter device as claimed in claim 2, it is characterized in that: comprise the word length processing unit after the described matched filter arithmetic elements at different levels, carry out processing, the control of WCDMA time slot synchronization matched filter word lengths at different levels by variable parameter configuration.
4. configurable WCDMA time slot synchronization matched filter device as claimed in claim 3, it is characterized in that: the input at described matched filter carries out the word length processing first time, determines input sample signal and the transformation relation of exporting to the matched filter signal according to the height of incoming level.
5. as claim 3 and 4 described configurable WCDMA time slot synchronization matched filter devices, it is characterized in that: described word length is handled and is included in input M bit N+1 bit is to the conversion of N bit after the conversion of N bit and the matched filter arithmetic elements at different levels, and the conversion here can be an amplitude limit, round off (comprise and rounding up) or both comprehensive operations.
6. configurable WCDMA time slot synchronization matched filter device as claimed in claim 1 is characterized in that: the base-band digital sampled signal of input is the spreading rate of 2 times or many times.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB01136713XA CN1141812C (en) | 2001-10-22 | 2001-10-22 | Configurable W-CDMA time slot synchronization matched filter device |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB01136713XA CN1141812C (en) | 2001-10-22 | 2001-10-22 | Configurable W-CDMA time slot synchronization matched filter device |
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| CN1347217A true CN1347217A (en) | 2002-05-01 |
| CN1141812C CN1141812C (en) | 2004-03-10 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101924577A (en) * | 2010-09-02 | 2010-12-22 | 上海交通大学 | Time slot synchronization method for resisting sampling clock frequency deviation in WCDMA (Wideband Code Division Multiple Access) system |
| CN103152075A (en) * | 2013-02-04 | 2013-06-12 | 太原理工大学 | Digital matching filter for WCDMA (wideband code division multiple access) communication |
-
2001
- 2001-10-22 CN CNB01136713XA patent/CN1141812C/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101924577A (en) * | 2010-09-02 | 2010-12-22 | 上海交通大学 | Time slot synchronization method for resisting sampling clock frequency deviation in WCDMA (Wideband Code Division Multiple Access) system |
| CN101924577B (en) * | 2010-09-02 | 2013-05-01 | 上海交通大学 | Time slot synchronization method for resisting sampling clock frequency deviation in WCDMA (Wideband Code Division Multiple Access) system |
| CN103152075A (en) * | 2013-02-04 | 2013-06-12 | 太原理工大学 | Digital matching filter for WCDMA (wideband code division multiple access) communication |
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| Publication number | Publication date |
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| CN1141812C (en) | 2004-03-10 |
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Owner name: MINISTRY OF INFORMATION INDUSTRY INSTITUTE OF TEL Free format text: FORMER OWNER: MINISTRY OF INFORMATION INDUSTRY INSTITUTE OF TELECOMMUNICATIONS TRANSMISSION; QINGHUA UNIVERSITY Effective date: 20060714 |
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Effective date of registration: 20060714 Address after: 100045 Beijing City, 11 South Street on the altar Co-patentee after: Tsinghua University Patentee after: Telecommunication Transmission Inst., Ministry of Information Industry Co-patentee after: Zhanxun Communication (Shanghai) Co., Ltd. Address before: 100045 Beijing City, 11 South Street on the altar Co-patentee before: Tsinghua University Patentee before: Telecommunication Transmission Inst., Ministry of Information Industry |
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