CN101924577A - Time slot synchronization method for resisting sampling clock frequency deviation in WCDMA (Wideband Code Division Multiple Access) system - Google Patents

Abstract

The invention discloses a time slot synchronization method for resisting sampling clock frequency deviation in a WCDMA (Wideband Code Division Multiple Access) system in the technical field of communication. The time slot synchronization of a downgoing signal in the WCDMA system is completed by steps of: carrying out high-rate oversampling on an input signal, wherein the sampling rate is chipping rate of 6-10 multiples; dividing the input signal into multiple paths of signal searching time slot boundaries after downsampling; and finally finding out a correct time slot boundary point with a comparison and combination method. The invention not only can eliminate the influence of the sampling clock frequency deviation to the time slot synchronization in the initial synchronization period, but also needs no extra sampling clock synchronization device compared with the prior art; and moreover, the system has the advantages of lower complexity and less resource consumption, which ensures the synchronization time to be greatly shortened.

Description

The slotted synchronous method of antagonism sampling clock frequency deviation in the WCDMA system

Technical field

What the present invention relates to is a kind of method of communication technical field, the slotted synchronous method that particularly relates to antagonism sampling clock frequency deviation in WCDMA (abbreviation of Wideband CDMA, the Wideband Code Division Multiple Access (WCDMA)) system of a kind of Frequency Division Duplexing (FDD) (FrequencyDivision Duplexing) pattern.

Background technology

Broadband CDMA system is a kind ofly specifically to be formulated by 3GPP, and based on GSM MAP core net, (UMTS Terrestrial Radio Access Network) is the 3-G (Generation Three mobile communication system) of wave point with the UMTS grounding wireless access network.Different with other two kinds of 3-G (Generation Three mobile communication system) (CDMA2000 and TD-SCDMA), the WCDMA system is an asynchronous wireless telecommunication system.Therefore before communicating between the base station in travelling carriage and the honeycomb, must be in synchronous regime with the base station, promptly travelling carriage need obtain the timing information of base station, comprises chip timings, slot timing, frame timing etc.

After travelling carriage has just been started shooting or lost synchronously, Cell searching need be carried out and initial synchronisation is carried out in the base station.The cell search process of mentioning in the WCDMA system in the standard document of WCDMA " ETSI TS 125 214 v8.2.0 " is divided into three steps, at first utilize synchronizing channel (the Synchronization Channel in the down channel, abbreviation SCH) Primary Synchronisation Code (the PrimarySynchronization Code in, be called for short PSC) the acquisition slot synchronization, utilize secondary synchronization code (the Secondary Synchronization Code in the synchronizing channel then, be called for short SSC) acquisition frame synchronization and the affiliated scrambler block number of the employed scrambler of current area, utilize Common Pilot Channel (Common Pilot Channel is called for short CPICH) to obtain the employed scrambler in sub-district, the current place of travelling carriage at last.

The first step slot synchronization of Cell searching is mainly utilized the Primary Synchronisation Code of launching on the descending synchronous signal channel.In the WCDMA system, descending synchronous signal channel comprises two subchannels: primary synchronization channel (Primary SCH) and auxiliary synchronization channel (Secondary SCH).The time span of primary synchronization channel and auxiliary synchronization channel radio frames is 10ms, is divided into 15 time slots, and each time slot comprises 2560 chips.

Synchronizing channel is used for synchronous signal in preceding 256 chip time intercycles transmissions of each time slot, wherein primary synchronization channel repeats to send Primary Synchronisation Code, the different time-gap of secondary synchronization code in each frame sends different secondary synchronization codes, and the identical time slot in the different frame sends identical secondary synchronization code.

The Primary Synchronisation Code that sends in the primary synchronization channel is a broad sense level Golay sign indicating number sequence (Generalized HierarchicalGolay Sequence), and the Primary Synchronisation Code that sends in each time slot of primary synchronization channel all is identical.The generation method of Primary Synchronisation Code can be with reference to 5.2 trifles in the WCDMA standard document " ETSI TS 125 213 v8.2.0 ".Primary Synchronisation Code itself has good autocorrelation aperiodic, also has good orthogonality each other with secondary synchronization code simultaneously.Fig. 1 is the auto-correlation peak value of Primary Synchronisation Code.The WCDMA system utilizes this character of Primary Synchronisation Code just, carry out filtering at receiving terminal to received signal by using the matched filter or the correlator that are complementary with Primary Synchronisation Code, obtain the slot timing information of received signal by the peak of search relevant peaks.Therefore in theory, as long as use a performance matched filter or correlator preferably, just can find the boundary of time slot of downstream signal at receiving terminal.

Find that by prior art documents Chinese patent application number has just proposed a kind of matched filter efficiently for 01136713.X, name are called in " configurable W-CDMA time slot synchronization matched filter device ".Because the asynchronous behavior between WCDMA system base-station and the travelling carriage will be considered the influence that the sampling clock frequency deviation is brought the correlation of Primary Synchronisation Code when carrying out slot synchronization.Owing to more or less have frequency departure between the crystal oscillator that use travelling carriage and base station, between the sampled point of the digital baseband signal that the travelling carriage sample quantization obtains interval greater than or less than the desirable time interval (clock cycle of the baseband digital signal that the base station sends), cause being not equal to 2560 chips (chip lengths of a time slot) through the interval between the correlation peak that obtains behind the matched filter.

Processing method for the sampling clock frequency deviation is divided into two kinds at present.A kind of feedback loop that is to use is estimated the sampling clock frequency deviation in digital baseband part, produces the frequency change direction of error signal control sampling clock, finally makes the clock of travelling carriage and the clock of base station reach synchronous regime; Another kind is by the method for interpolation digital baseband signal to be handled, and uses this class device of Farrow filter digital baseband signal to be carried out the adjustment of sample rate at numeric field.These two kinds of methods cut both ways, and all have certain complexity in the realization.

Summary of the invention

The objective of the invention is at the deficiencies in the prior art, propose the slotted synchronous method of antagonism sampling clock frequency deviation in a kind of WCDMA system.The present invention can not only effectively obtain the slot timing information of received signal, and does not need the device of extra correction sampling clock frequency deviation, and system's implementation complexity of slot synchronization is lower.

The present invention includes following steps:

The first step is carried out frequency departure to N times of over-sampling (sample rate is 6 times to 10 times a the chip-rate) digital baseband signal of importing and is estimated, obtains frequency departure estimated value Δ f _eEstimated value Δ f according to frequency departure _eDigital baseband signal is carried out frequency compensation, is specially:

r _comp(n)＝r(n)×exp[2πn×Δf _e/f _samp]

F wherein _SampIt is the sample rate of digital baseband signal.

Described frequency departure is estimated, be may further comprise the steps:

1. 2M frequency departure precompensation control word is set

Δf _p(n)＝n×1000

N={-M wherein ,-M+1 ... ,-1,1 ..., M-1, M}, the frequency values of precompensation is carried out in expression.

2. with described frequency departure precompensation control word { Δ f _p(n) } carry out the frequency departure precompensation respectively to receiving digital baseband signal { r (n) }, obtain 2M road precompensated signal, specific as follows

$r_{\mathrm{comp}}^{\left(k\right)}\left(n\right)=r\left(n\right)\×\exp [2\mathrm{\πn}\×\mathrm{\Δ}{f}_p\left(k\right)/f_{\mathrm{samp}}],$ k∈{-M，...，1，1，...，M}

F wherein _SampIt is the sample rate of digital baseband signal.

With the 2M road precompensated signal of { r (n) } and gained respectively by with the filter of Primary Synchronisation Code coupling, obtain 2M+1 road Primary Synchronisation Code correlation; Search for maximum from the correlation that obtains, the employed frequency departure precompensation of maximum respective signal control word is exactly frequency departure estimated value Δ f to received signal _e

Second step is to the signal { r behind the compensate of frequency deviation _Comp(n) } extracted at equal intervals is carried out down-sampling, extracts to equal over-sampling multiple N at interval; Owing to the skew difference that extracts, can obtain the baseband digital signal of the single times of chip-rate in N road, be specially K ∈ 1 .., N}

Wherein: the deviant of k for primary signal is extracted, n is the sampled point sequence number of down-sampled signal.

The 3rd step is with each road down-sampling digital baseband signal

K ∈ 1, and .., N} obtains N road Primary Synchronisation Code correlation by the Primary Synchronisation Code matched filter, is specially

$s^{\left(k\right)}\left(n\right)=\underset{i=1}{\overset{256}{\mathrm{\Σ}}}{r}_{\mathrm{dn}}^{\left(k\right)}(n+i-1)*C_{\mathrm{psc}}\left(i\right),$ k∈{1，..，N}

Then each road correlation value signal is carried out normalized, obtain N road normalization correlation, be specially

$s_{\mathrm{norm}}^{\left(k\right)}\left(n\right)=\frac{\left|s^{\left(k\right)}\left(n\right)\right|}{\sqrt{\underset{i=1}{\overset{256}{\mathrm{\Σ}}}{\left|r_{\mathrm{dn}}^{\left(k\right)}(n+i-1)\right|}^2}},$ k∈{1，..，N}

The 4th step is to N road normalization correlation value signal { s ^(k)(n) }, { 1 .., N} compare and obtain one road maximum normalization correlation value signal { s k ∈ _Max(n) }.In N road normalization correlation value signal, from N normalization correlation of same sequence number, select maximum as { s _Max(n) } value of this sequence number in; Write down { s simultaneously _Max(n) } which signal each point in is selected from.Be specially:

$s_{\max }\left(n\right)=\max \left\{s_{\mathrm{norm}}^{\left(k\right)}\left(n\right)\right\},$ k∈{1，..，N}

$d_{\mathrm{idx}}\left(n\right)=k|{\{s}_{\max }\left(n\right)=s_{\mathrm{norm}}^{\left(k\right)}\left(n\right)\}$

The 5th step is from { s _Max(n) } maximizing H in preceding two time slots (2560 * 2=5120 chip).

If H greater than normalization threshold value NT, then with its down-sampling initial value as the boundary of time slot point of received signal, that is to say that this is first the effective boundary of time slot point that finds during this is handled.Clock the down-sampling subscript sequence of crack boundary point for { t _Idx(n) }, t then _Idx(0)=i|{s _Max(i)=H=max{s _Max(n) }, n ∈ 1,2 .., 5120}}; Simultaneously effective boundary of time slot counter is changed to 1, is specially b _Num=1.

If maximum H less than normalization threshold value NT, then slides backward search window 5120 chips, repeat this step, till finding first effective boundary of time slot point.

The 6th step is with t _Idx(0) is initial value, begins to search for the sequence number of remaining boundary of time slot point.Concrete method is, with n-1 boundary of time slot point is that basic point is searched n boundary of time slot point, owing to there is the sampling clock frequency deviation, interval between two adjacent Primary Synchronisation Code correlation peaks is not equal to 2560 chips (number of chips of a time slot correspondence), therefore the time slot position of the individual effective boundary of time slot point of search n in the theoretical position with n boundary of time slot point is the minizone at center.If the maximum in this interval has surpassed the threshold value NT of normalization correlation, then write down n boundary of time slot point and be

t _idx(n)＝x|{s _max(x)＝max{s _max(i)，i∈[t _idx(n-1)+2560-w，t _idx(n-1)+2560+w]}}

Wherein w is the parameter that region of search width is set, common desirable 2 to 4; Simultaneously effective boundary of time slot counter is increased by 1, be specially b _Num=b _Num+ 1.

If the maximum in this interval does not surpass the threshold value NT of normalization correlation, then write down n boundary of time slot point and be

t _idx(n)＝t _idx(n-1)+2560

Effectively the boundary of time slot counter remains unchanged simultaneously.

In the 7th step, after handling a complete WCDMA frame (15 time slots) in the previous step, check b _NumIn value, if b _NumIn value greater than preset time slot detection threshold value SN, the expression correctly finished slot synchronization, then with b _NumZero clearing is simultaneously according to resulting boundary of time slot dot position information { t _Idx(n) } also export the position of calculating corresponding boundary of time slot point in the primary signal, is specially:

b _num＝0

T _idx(n)＝[t _idx(n)-1]*N+d _idx[t _idx(n)]-1

If b _NumIn value less than threshold value SN, the expression do not finish slot synchronization, then with b _NumZero clearing begins to handle the next frame data.

The present invention not only can overcome the influence that slot synchronization is brought in initial synchronisation initial stage sampling clock frequency deviation, and compared with prior art, not needing extra sampling clock synchronizer, the complexity of system is lower, resource consumption is littler, makes shorten widely lock in time.

Description of drawings

Fig. 1 is the autocorrelation performance of Primary Synchronisation Code;

Fig. 2 is an embodiment of the invention operation principle structural representation block diagram;

Fig. 3 is an embodiment of the invention implementing procedure schematic diagram.

Embodiment

Below in conjunction with accompanying drawing method of the present invention is further described: present embodiment is being to implement under the prerequisite with the technical solution of the present invention, provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment.

Embodiment

As shown in Figure 2, operation principle structural representation block diagram in the present embodiment implementation process, the present embodiment structure comprises frequency departure estimation and compensating module 201, uniformly-spaced down sample module 202, Primary Synchronisation Code correlator bank 203, correlation normalization module 204, correlation is relatively selected module 205, boundary of time slot point search module 206, boundary of time slot point sequence number computing module 207.

As shown in Figure 3, present embodiment may further comprise the steps:

Step 301 according to the frequency deviation estimating method described in the first step in the summary of the invention, is carried out frequency departure to 8 times of over-sampling digital baseband signals importing and is estimated, obtains frequency departure estimated value Δ f _eEstimated value Δ f according to frequency departure _eDigital baseband signal is carried out frequency compensation, be specially

r _comp(n)＝r(n)×exp[2πn×Δf _e/f _samp]

F wherein _SampBeing the sample rate of digital baseband signal, is 8 times of WCDMA signal chip-rate.

Step 302 is to the signal { r behind the compensate of frequency deviation _Comp(n) } extracted at equal intervals is carried out down-sampling, extracts to equal over-sampling multiple 8 at interval; Owing to the start offset position difference that extracts, obtain the digital baseband signal of 8 tunnel single times of chip-rate, be specially

$r_{\mathrm{dn}}^{\left(k\right)}\left(n\right)=r_{\mathrm{comp}}\{(n-1)\×8+k\},$ k∈{1，..，8}

Wherein: the deviant of k for primary signal is extracted, n is the sampled point sequence number of down-sampled signal.

Step 303 is with 8 road down-sampling digital baseband signals

{ 1 .., 8} by the Primary Synchronisation Code correlator, obtain 8 road Primary Synchronisation Code correlations respectively to k ∈, are specially

$s^{\left(k\right)}\left(n\right)=\underset{i=1}{\overset{256}{\mathrm{\Σ}}}{r}_{\mathrm{dn}}^{\left(k\right)}(n+i-1)*C_{\mathrm{psc}}\left(i\right),$ k∈{1，..，8}

Then 8 road Primary Synchronisation Code correlations are carried out normalized, obtain 8 tunnel normalization Primary Synchronisation Code correlations, be specially

$s_{\mathrm{norm}}^{\left(k\right)}\left(n\right)=\frac{\left|s^{\left(k\right)}\left(n\right)\right|}{\sqrt{\underset{i=1}{\overset{256}{\mathrm{\Σ}}}{\left|r_{\mathrm{dn}}^{\left(k\right)}(n+i-1)\right|}^2}},$ k∈{1，..，8}

Step 304 in 8 tunnel normalization correlation value signal that obtain, is selected a maximum from per 8 normalization correlations of same sequence number in step 303, be designated as { s _Max(n) } value of this sequence number in; Write down { s simultaneously _Max(n) } which signal each point in is selected from.Be specially:

$s_{\max }\left(n\right)=\max \left\{s_{\mathrm{norm}}^{\left(k\right)}\left(n\right)\right\},$ k∈{1，..，8}

$d_{\mathrm{idx}}\left(n\right)=k|{\{s}_{\max }\left(n\right)=s_{\mathrm{norm}}^{\left(k\right)}\left(n\right)\}$

Step 305 is from { s _Max(n) } maximizing H in preceding two time slots (2560 * 2=5120 chip).

If maximum H greater than normalization threshold value 0.3, then with its down-sampling initial value as the boundary of time slot point of received signal, that is to say that this is first the effective boundary of time slot point that finds during this is handled.Clock the down-sampling subscript sequence of crack boundary point for { t _Idx(n) }, t then _Idx(0)=i|{s _Max(i)=H=max{s _Max(n) }, n ∈ 1,2., 5120}}; Simultaneously effective boundary of time slot counter is changed to 1, is specially b _Num=1.

If maximum H is less than normalization threshold value 0.3, expression does not search effective boundary of time slot point, and search window is slided backward 5120 chips, repeats this step, till finding first effective boundary of time slot point.

Step 306 is with the t that finds in the step 305 _Idx(0) is initial value, begins to search for the sequence number of remaining boundary of time slot point.Concrete method is, is that basic point is searched n boundary of time slot point with n-1 boundary of time slot point, and the theoretical position of n boundary of time slot point is

t _idx(n)＝t _idx(n-1)+2560

Owing to there is a sampling clock frequency deviation, with the theoretical position of n boundary of time slot point the time slot position of n effective boundary of time slot point of search in the minizone at center, search radius is apart from 3 chips of theoretical boundary of time slot point.If the maximum in this interval has surpassed the threshold value 0.3 of normalization correlation, the position of then writing down n boundary of time slot point is

t _idx(n)＝x|{s _max(x)＝max{s _max(i)，i∈[t _idx(n-1)+2560-3，t _idx(n-1)+2560+3]}}

Simultaneously effective boundary of time slot counter is increased by 1, be specially b _Num=b _Num+ 1.

If the maximum in this interval does not surpass the threshold value 0.3 of normalization correlation, represent not have in this interval effective boundary of time slot point, the position of then writing down n boundary of time slot point is

t _idx(n)＝t _idx(n-1)+2560

Effectively the boundary of time slot counter remains unchanged simultaneously.

If handle the complete WCDMA frame that is over this moment, just obtained the position of the boundary of time slot point of 15 time slots, then carry out next step processing; If do not handle a complete WCDMA frame, then continue the position of the next boundary of time slot point of search.

Step 307 is checked b _NumIn value, if b _NumIn value greater than preset time slot synchronous detecting threshold value 13, therefore expression has correctly searched abundant effective boundary of time slot point, has finished slot synchronization, with b _NumZero clearing is simultaneously according to resulting boundary of time slot dot position information { t _Idx(n) } position of corresponding boundary of time slot point in the calculating primary signal is specially

b _num＝0

T _idx(n)＝[t _idx(n)-1]*8+d _idx{t _idx(n)}-1

The boundary of time slot point sequence number that obtain this moment is exactly the boundary of time slot information that receives data, outputs in the next stage module for use.

If b _NumIn value less than slot synchronization detection threshold value 13, expression does not search abundant effective boundary of time slot point, the slot synchronization failure is therefore with b _NumZero clearing begins the next frame data are handled.

Claims (6)

1. the slotted synchronous method of antagonism sampling clock frequency deviation in the WCDMA system is characterized in that, may further comprise the steps:

The first step is carried out frequency departure to the N times of over-sampling digital baseband signal of importing and is estimated, obtains frequency departure estimated value Δ f _eEstimated value Δ f according to frequency departure _eDigital baseband signal is carried out frequency compensation is:

r _comp(n)＝r(n)×exp[2πn×Δf _e/f _samp]

F wherein _SampIt is the sample rate of digital baseband signal;

Second step is to the signal { r behind the compensate of frequency deviation _Comp(n) } extracted at equal intervals is carried out down-sampling, extracts to equal over-sampling multiple N at interval; Because the skew difference that extracts, the baseband digital signal that can obtain the single times of chip-rate in N road is:

$r_{\mathrm{dn}}^{\left(k\right)}\left(n\right)=r_{\mathrm{comp}}\{(n-1)\×N+k\},$ k∈{1，..，N}

Wherein: the deviant of k for primary signal is extracted, n is the sampled point sequence number of down-sampled signal;

The 3rd step is with each road down-sampling digital baseband signal K ∈ 1, and .., N} passes through the Primary Synchronisation Code matched filter, obtains N road Primary Synchronisation Code correlation and is:

$s^{\left(k\right)}\left(n\right)=\underset{i=1}{\overset{256}{\mathrm{\Σ}}}{r}_{\mathrm{dn}}^{\left(k\right)}(n+i-1)*C_{\mathrm{psc}}\left(i\right),$ k∈{1，..，N}，

Then each road correlation value signal is carried out normalized, obtains N road normalization correlation and be:

$s_{\mathrm{norm}}^{\left(k\right)}\left(n\right)=\frac{\left|s^{\left(k\right)}\left(n\right)\right|}{\sqrt{\underset{i=1}{\overset{256}{\mathrm{\Σ}}}{\left|r_{\mathrm{dn}}^{\left(k\right)}(n+i-1)\right|}^2}},$ k∈{1，..，N}；

The 4th step is to N road normalization correlation value signal { s ^(k)(n) }, { 1 .., N} compare and obtain one road maximum normalization correlation value signal { s k ∈ _Max(n) };

The 5th step is from { s _Max(n) } maximizing H in preceding two time slots (2560 * 2=5120 chip);

The 6th step is with t _Idx(0) is initial value, begins to search for the sequence number of remaining boundary of time slot point;

In the 7th step, after handling a complete WCDMA frame in the previous step, check b _NumIn value, if b _NumIn value greater than preset time slot detection threshold value SN, the expression correctly finished slot synchronization, then with b _NumZero clearing is simultaneously according to resulting boundary of time slot dot position information { t _Idx(n) } also export the position of calculating corresponding boundary of time slot point in the primary signal.

2. the slotted synchronous method of antagonism sampling clock frequency deviation in the WCDMA according to claim 1 system is characterized in that described frequency departure is estimated, be may further comprise the steps:

1. 2M frequency departure precompensation control word be set:

Δf _p(n)＝n×1000

Wherein: n={-M ,-M+i ... ,-1,1 ..., M-1, M}, the frequency values of precompensation is carried out in expression;

2. use described frequency departure precompensation control word { Δ f _p(n) } carry out the frequency departure precompensation respectively to receiving digital baseband signal { r (n) }, obtain 2M road precompensated signal:

$r_{\mathrm{comp}}^{\left(k\right)}\left(n\right)=r\left(n\right)\×\exp [2\mathrm{\πn}\×\mathrm{\Δ}{f}_p\left(k\right)/f_{\mathrm{samp}}],$ k∈{-M，...，-1，1，...，M}

Wherein: f _SampIt is the sample rate of digital baseband signal;

3. with the 2M road precompensated signal of { r (n) } and gained respectively by with the filter of Primary Synchronisation Code coupling, obtain 2M+1 road Primary Synchronisation Code correlation; Search for maximum from the correlation that obtains, the employed frequency departure precompensation of maximum respective signal control word is exactly frequency departure estimated value Δ f to received signal _e

3. the slotted synchronous method of antagonism sampling clock frequency deviation is characterized in that in the WCDMA according to claim 1 system, in described N road normalization correlation value signal, selects maximum conduct { s from N normalization correlation of same sequence number _Max(n) } value of this sequence number in; Write down { s simultaneously _Max(n) } which signal each point in is selected from is:

$s_{\max }\left(n\right)=\max \left\{s_{\mathrm{norm}}^{\left(k\right)}\left(n\right)\right\},$ k∈{1，..，N}，

$d_{\mathrm{idx}}\left(n\right)=k|{\{s}_{\max }\left(n\right)=s_{\mathrm{norm}}^{\left(k\right)}\left(n\right)\}.$

4. the slotted synchronous method of antagonism sampling clock frequency deviation is characterized in that in the WCDMA according to claim 1 system, the maximum H described in the 5th step:

If H greater than normalization threshold value NT, then with its down-sampling initial value as the boundary of time slot point of received signal, that is to say that this is first the effective boundary of time slot point that finds during this is handled, the down-sampling subscript sequence of the crack boundary point that clocks is { t _Idx(n) }, t then _Idx(0)=i|{s _Max(i)=H=max{s _Max(n) }, n ∈ 1,2 .., 5120}}; Simultaneously effective boundary of time slot counter is changed to 1, is specially b _Num=1;

If maximum H less than normalization threshold value NT, then slides backward search window 5120 chips, repeat this step, till finding first effective boundary of time slot point.

5. the slotted synchronous method of antagonism sampling clock frequency deviation is characterized in that in the WCDMA according to claim 1 system, the sequence number of remaining the boundary of time slot point of search described in the 6th step, and its method is as follows:

With n-1 boundary of time slot point is that basic point is searched n boundary of time slot point, owing to there is the sampling clock frequency deviation, interval between two adjacent Primary Synchronisation Code correlation peaks is not equal to 2560 chips, therefore the time slot position of the individual effective boundary of time slot point of search n in the theoretical position with n boundary of time slot point is the minizone at center, if the maximum in this interval has surpassed the threshold value NT of normalization correlation, then write down n boundary of time slot point and be:

t _idx(n)＝x|{s _max(x)＝max{s _max(i)，i∈[t _idx(n-1)+2560-w，t _idx(n-1)+2560+w]}}

Wherein w is the parameter that region of search width is set, common desirable 2 to 4; Simultaneously effective boundary of time slot counter is increased by 1, be specially b _Num=b _Num+ 1,

If the maximum in this interval does not surpass the threshold value NT of normalization correlation, then write down n boundary of time slot point and be:

t _idx(n)＝t _idx(n-1)+2560，

Effectively the boundary of time slot counter remains unchanged simultaneously.

6. the slotted synchronous method of antagonism sampling clock frequency deviation is characterized in that in the WCDMA according to claim 1 system, and the position of corresponding boundary of time slot point is in the primary signal described in the 7th step:

b _num＝0，

T _idx(n)＝[t _idx(n)-1]*N+d _idx{t _idx(n)}-1，

If b _NumIn value less than threshold value SN, the expression do not finish slot synchronization, then with b _NumZero clearing begins to handle the next frame data.

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