CN101499844B - Frequency synchronization method for WCDMA system downlink receiver - Google Patents
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Abstract
The invention discloses a frequency synchronizing method that is used in a downstream receiver of WCDMA systems. The frequency synchronizing method uses an adjustable window length W to substitute a spreading factor 256 and accumulate descrambling results, the adjustable window length W can be better fit for the phase rotation that is caused by frequency swing in practice and find a balance point between resistance to noise interference and adaptation to phase rotation; zero-fill operation and fast Fourier transform of accumulated results are sequentially implemented, thus raising the resolution of spectrum simulation domain, namely, improving the precision of frequency swing estimation; only one step of accurate frequency swing adjustment is required, and coarse frequency swing adjustment of traditional methods is avoided, thus reducing computation and storage requirements.
Description
Technical field
The present invention relates to a kind of frequency synchronization method, particularly a kind of frequency synchronization method that is used for the WCDMA system downlink receiver.
Background technology
In the GSM, subscriber equipment needs to obtain time synchronized and Frequency Synchronization through the synchronous searching process with certain sub-district when initial the access.Asynchronous operation is adopted in the search of WCDMA system cell.In cell search process, the frame synchronization and the Frequency Synchronization of sub-district of user equipment searches and definite down link scrambler, this sub-district.
The physical channel relevant with the WCDMA down-going synchronous has primary synchronization channel PSCH, auxiliary synchronization channel SSCH and down public guide frequency channel PCPICH.Synchronous channel SCH comprises the primary synchronization channel PSCH and the auxiliary synchronization channel SSCH of quadrature, and PSCH and the SSCH structure in 10ms one frame is as shown in Figure 1.
Referring to Fig. 1, synchronous channel SCH was sent in the preceding 256chips cycle of each time slot Slot.The information that transmits among the primary synchronization channel PSCH is called Primary Synchronisation Code PSC, representes with Cpsc; The information that transmits among the auxiliary synchronization channel SSCH is called auxiliary synchronous code SSC, representes with Cssc.Among Fig. 1, Cpsc is a Primary Synchronisation Code, and the length of definition Primary Synchronisation Code is 256chips in the WCDMA standard, and all time slots all are identical in all sub-districts.Through identification, can confirm slot timing to Primary Synchronisation Code PSC.
Primary Synchronisation Code PSC is called broad sense Golay sign indicating number by different level in the standard, it modulates the PSC that generates 256bits through the sign indicating number a of a 16bits through following mode, and generating mode is following:
a＝<x1，x2，x3，…，x16>＝<1，1，1，1，1，1，-1，-1，1，-1，1，-1，1，-1，-1，1>
Cpsc＝(1+j)×<a，a，a，-a，-a，a，-a，-a，a，a，a，-a，a，-a，a，a>；
16 length have also been defined in the system and are 256 auxiliary synchronous code.Cssc among the figure
I, kBe in 16 auxiliary synchronous codes, i=1～64th, the block number of auxiliary synchronous code, by the base station decision, and k is the serial number of place time slot, k=0～14.Like this, (Cssc
I, 0, Cssc
I, 1..., Cssc
I, 14) just represented of the output of the auxiliary synchronous code of i code character at each time slot.Through identification to auxiliary synchronous code, can find frame boundaries on the one hand, can identify the block number of the scrambler that is using the sub-district, place on the other hand.
The SSC sequence is the product of Golay sign indicating number and hardmard sequence by different level, and it generates through following mode:
b＝<x1，x2，x3，x4，x5，x6，x7，x8，-x9，-x10，-x11，-x12，-x13，-x14，-x15，-x16>
z＝<b，b，b，-b，b，b，-b，-b，b，-b，b，-b，-b，-b，-b，-b>
Cssc，k＝(1+j)×<hm(0)×z(0)，hm(1)×z(1)，hm(2)×z(2)，…，hm(255)×z(255)>；
Wherein hm (n) is the Hardmard sequence of 16 (k-1) for sequence number.
Down public guide frequency channel PCPICH is to be that 38400chips long code (long code) constitutes by the cycle.Long code constitutes the GOLD sequence of blocking through the M sequence of the shift register generation on two 18 rank of Fig. 2.
According to the above-mentioned and characteristics sync correlation physical channel, the WCDMA method, system time synchronization generally is divided into three steps: slot synchronization, frame synchronization and code character are confirmed, scrambler is confirmed.The process of Frequency Synchronization and time synchronized is closely related, and existing frequency synchronization method generally is divided into 2 steps:
Step 1: frequency deviation coarse adjustment
The frequency deviation coarse adjustment comprises the rough estimate and the adjustment of frequency deviation.It is to utilize the result of slot synchronization difference matched filtering to carry out the rough estimate of frequency deviation.Concrete, promptly obtain its peak value filtRes through search difference matched filtering result
Peak, then the rough estimate of frequency deviation is suc as formula (1):
Arg () representes that asking phase place, unit is rad in the formula (1); W1 representes that the window of difference matched filtering is long; Δ T representes sampling time interval.
Step 2: frequency deviation accurate adjustment
The frequency deviation accurate adjustment comprises the accurate estimation and the adjustment of frequency deviation.It is to utilize the result behind the PCPICH descrambling and de-spreading to carry out the accurate estimation of frequency deviation.Because the signal equivalence that the PCPICH channel sends is the direct current signal of base band, if having under the situation of frequency deviation existence, the signal of PCPICH then equivalence is the tone signal of frequency deviation for frequency.Therefore, can obtain its peak value, frequency deviation accurately estimated according to the phase place of peak value through result's behind the search descrambling and de-spreading fast Fourier transform (FFT).
Existing frequency synchronization method need comprise frequency deviation coarse adjustment and two steps of frequency deviation accurate adjustment, need take more calculating, storage resources.
Summary of the invention
The present invention is in order to overcome the deficiency that above prior art exists, provide a kind of simplification, accurately, take the frequency synchronization method that is used for the WCDMA system downlink receiver of less calculating storage resources.
The object of the invention is realized through following technical scheme: originally be used for the frequency synchronization method of WCDMA system downlink receiver, it is characterized in that may further comprise the steps:
(1) the WCDMA base station data of on PCPICH, sending are the scrambler SC of its use product with+1/-1; Scrambler SC is the cycle with the frame, and what PCPICH carried after the descrambling module descrambling is that frequency is the tone signal of frequency deviation, with corresponding scrambler SC one frame data is carried out descrambling; Obtain Dsc=< dsc1; Dsc2 ..., dsc38400 >;
(2) pressing the long accumulator module of window; Long W adds up to Dsc according to window; Obtain Asc=< asc1; Asc2; Asc
38400/W
>;
expression rounds downwards, and the value of W depends on the size of frequency deviation;
(3) in the zero padding module; According to the points N of FFT Asc is carried out zero padding and obtain Zsc=< zsc1; Zsc2; ZscN >=< asc1; Asc2 ..., asc
38400/W
; Zero1; Zero2 ..., zero (N-
38400/W
) >;
(4) in the FFT module, to Zsc carry out FFT FFT obtain Fsc=fsc1, fsc2 ..., fscN >;
(5) in search maximum module, the maximum among the search Fsc obtains its corresponding subscript m axIndex;
(6) at frequency offset estimating value computing module, maxIndex is adjusted, obtain index: if maxIndex is<N/2, then index=maxIndex according to the points N of Fourier transform; If maxIndex>=N/2, index=maxIndex-N then, the accurate estimated value of frequency deviation is foe=-(3.84e6 * index)/(W * N).
Said descrambling module comprises one or more than one multiplier.
Saidly comprise one or more than one accumulator by the long accumulator module of window.
Said zero padding module comprises one or more than one comparator.
Said FFT module comprises one or more than one multiplier and adder.
Said search maximum module comprises one or more than one comparator.
Said frequency offset estimating value computing module comprises one or more than one multiplier, adder, comparator and divider.
Said frequencies method for synchronous process is described with the single-time sampling rate, and this frequency synchronization method of situation of multiple sampling rate is suitable equally.
The present invention has following advantage with respect to prior art:
One, the frequency synchronization method that originally is used for the WCDMA system downlink receiver has been simplified the step of Frequency Synchronization, has improved the precision of Frequency Synchronization, takies less calculating, storage resources, more is applicable to the Frequency Synchronization of WCDMA system downlink receiver;
Two, use the long W of variable window to replace spreading factor 256, the result adds up to descrambling, uses the long W of variable window can better adapt to the phase place rotation that practical application intermediate frequency local derviation causes, and obtains compromise in antinoise interference and adaptation phase place aspect rotating two;
Three, the result who adds up is carried out carrying out FFT again after the zero padding operation, improved the resolution of frequency spectrum analog domain, promptly improved the precision of frequency offset estimating;
Four, with respect to existing frequency synchronization method, save the frequency deviation coarse adjustment, only need step of frequency deviation accurate adjustment, reduced computation requirement and storage demand.
This method can be under the situation of frequency deviation for ± 6000Hz between 3dB, user side and base station in signal to noise ratio, can within a frame, accomplish the accurate estimation of frequency deviation.
The present invention is applied to the concrete application form of downlink receivers such as user terminal, road measuring device, intelligent straight placement station.The present invention is not only applicable to the situation of single sub-district, is applicable to the situation of common frequency multi-cell yet.
Description of drawings
Fig. 1 is the frame structure sketch map of WCDMA system descending synchronous channel SCH.
Fig. 2 is the principle schematic that existing shift register generates descending scrambler.
Fig. 3 is the block diagram of the frequency synchronization method of a kind of WCDMA of being used for system downlink receiver of the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is described further.
As shown in Figure 3, originally be used for the frequency synchronization method of WCDMA system downlink receiver, may further comprise the steps:
(1) the WCDMA base station data of on PCPICH, sending are the scrambler SC of its use product with+1/-1; Scrambler SC is the cycle with the frame, and what PCPICH carried after the descrambling module descrambling is that frequency is the tone signal of frequency deviation, with corresponding scrambler SC one frame data is carried out descrambling; Obtain Dsc=< dsc1; Dsc2 ..., dsc38400 >;
(2) pressing the long accumulator module of window; Long W adds up to Dsc according to window; Obtain Asc=< asc1; Asc2; Asc
38400/W
>;
expression rounds downwards, and the value of W depends on the size of frequency deviation;
(3) in the zero padding module; According to the points N of FFT Asc is carried out zero padding and obtain Zsc=< zsc1; Zsc2; ZscN >=< asc1; Asc2 ..., asc
38400/W
; Zero1; Zero2 ..., zero (N-
38400/W
) >;
(4) in the FFT module, to Zsc carry out FFT FFT obtain Fsc=fsc1, fsc2 ..., fscN >;
(5) in search maximum module, the maximum among the search Fsc obtains its corresponding subscript m axIndex;
(6) at frequency offset estimating value computing module, maxIndex is adjusted, obtain index: if maxIndex＜N/2, then index=maxIndex according to the points N of Fourier transform; If maxIndex >=N/2, index=maxIndex-N then, the accurate estimated value of frequency deviation is foe=-(3.84e6 * index)/(W * N).
Above-mentioned descrambling module can be realized with multiplier; Can realize with accumulator by the long accumulator module of window; The zero padding module can realize with comparator; The FFT module can use multiplier and adder to realize; Search maximum module can realize with comparator; Frequency offset estimating value computing module can use multiplier, adder, comparator and divider to realize.Above-mentioned multiplier, adder, accumulator, comparator and divider can be realized on a slice/multiple FPGA or dsp chip.
Above-mentioned embodiment is the preferred embodiments of the present invention; Can not limit claim of the present invention; Other any change or other equivalent substitute mode that does not deviate from technical scheme of the present invention and made is included within protection scope of the present invention.
Claims (7)
1. the frequency synchronization method that is used for the WCDMA system downlink receiver is characterized in that may further comprise the steps:
(1) the WCDMA base station data of on PCPICH, sending are the scrambler SC of its use and+1 or-1 product; Scrambler SC is the cycle with the frame, and what PCPICH carried after the descrambling module descrambling is that frequency is the tone signal of frequency deviation, with corresponding scrambler SC one frame data is carried out descrambling; Obtain Dsc=< dsc1; Dsc2 ..., dsc38400 >;
(2) pressing the long accumulator module of window; Long W adds up to Dsc according to window; Obtain Asc=< asc1; Asc2;
>,
expression rounds downwards, and the value of W depends on the size of frequency deviation;
(3) in the zero padding module; According to the points N of FFT Asc is carried out zero padding and obtain Zsc=< zsc1; Zsc2 ..., zscN >=< asc1; Asc2;,
zerol, zero2;,
>;
(4) in the FFT module, to Zsc carry out FFT FFT obtain Fsc=fsc1, fsc2 ..., fscN >;
(5) in search maximum module, the maximum among the search Fsc obtains its corresponding subscript m axIndex;
(6) at frequency offset estimating value computing module, maxIndex is adjusted, obtain index: if maxIndex＜N/2, then index=maxIndex according to the points N of Fourier transform; If maxIndex >=N/2, index=maxIndex-N then, the accurate estimated value of frequency deviation is foe=-(3.84e6 * index)/(W * N).
2. the frequency synchronization method that is used for the WCDMA system downlink receiver according to claim 1 is characterized in that: said descrambling module comprises more than one multiplier.
3. the frequency synchronization method that is used for the WCDMA system downlink receiver according to claim 1 is characterized in that: saidly comprise more than one accumulator by the long accumulator module of window.
4. the frequency synchronization method that is used for the WCDMA system downlink receiver according to claim 1 is characterized in that: said zero padding module comprises more than one comparator.
5. the frequency synchronization method that is used for the WCDMA system downlink receiver according to claim 1 is characterized in that: said FFT module comprises more than one multiplier and adder.
6. the frequency synchronization method that is used for the WCDMA system downlink receiver according to claim 1 is characterized in that: said search maximum module comprises more than one comparator.
7. the frequency synchronization method that is used for the WCDMA system downlink receiver according to claim 1 is characterized in that: said frequency offset estimating value computing module comprises more than one multiplier, adder, comparator and divider.
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| CN111490955B (en) * | 2020-03-10 | 2023-05-05 | 西安宇飞电子技术有限公司 | Method and device for realizing synchronous head search under large frequency offset |
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| CN1710833A (en) * | 2005-06-17 | 2005-12-21 | 凯明信息科技股份有限公司 | Relative method for primary synchronizing in CDMA mobile communication system |
| CN1988427A (en) * | 2005-12-23 | 2007-06-27 | 上海华龙信息技术开发中心 | Method for accurately catching frequency in wide band CDMA communication system |
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| CN1988427A (en) * | 2005-12-23 | 2007-06-27 | 上海华龙信息技术开发中心 | Method for accurately catching frequency in wide band CDMA communication system |
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