CN103188067A - Method for estimating and correcting deviation and error of chip clock frequency of spread spectrum system - Google Patents
Method for estimating and correcting deviation and error of chip clock frequency of spread spectrum system Download PDFInfo
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- CN103188067A CN103188067A CN2013101162386A CN201310116238A CN103188067A CN 103188067 A CN103188067 A CN 103188067A CN 2013101162386 A CN2013101162386 A CN 2013101162386A CN 201310116238 A CN201310116238 A CN 201310116238A CN 103188067 A CN103188067 A CN 103188067A
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Abstract
The invention provides a method for estimating and correcting deviation and error of a chip clock frequency of a spread spectrum system. After receiving a radio-frequency signal, a receiving antenna firstly converts the radio-frequency signal into a digital baseband signal, then a practical zero crossing point value is obtained sequentially through primary synchronization, frequency domain interpolation, secondary synchronization, de-frequency offset and de-phase offset, and calculation of a zero crossing point serial number, and finally a practical chip clock frequency is obtained through the number of the chip corresponding to the zero crossing point and a first-order linear relationship at the moment of the zero crossing point, so that the error of the chip clock frequency is obtained, therefore, compensation and correction of the clock frequency are realized, the chip clock frequency of a transmitter and the chip clock frequency of a receiving end are guaranteed to be consistent, the demodulation performance of a receiver is improved, and the data received by the receiver can be well recovered.
Description
Technical field
The present invention relates to a kind of spread spectrum system chip clock frequency error and estimate and bearing calibration, particularly the method for a kind of WiFi system's chip clock frequency error estimation and correction.
Background technology
Spread spectrum is to the process much larger than baseband signal bandwidth with the spread spectrum of baseband signal.Spread spectrum communication has stronger anti-interference, anti-multipath performance and availability of frequency spectrum height, supports characteristics such as multiple access communication.
WiFi a kind ofly carries out interconnective technology with terminals such as computer network interface card and mobile phones by using radio.Be applied in the business district now widely, university, airport, and other public domains.WiFi institute use standard is 802.11 series standards of IEEE definition.
802.11b be to use the agreement of direct sequence spread spectrum skill.At transmitting terminal, data to be sent form broadband signal after by the chip clock signal spread-spectrum, and are modulated, and by antenna transmission of wireless signals are gone out then; At receiving terminal, receiver uses the chip clock identical with transmitter that wideband spread-spectrum signal is carried out the demodulation despreading, thereby recovers original transmitted data signal.
Because may there be deviation in the chip clock frequency of transmitter and the chip clock frequency of receiving terminal, at receiving terminal, this deviation may cause receiver can't intactly recover the data that transmitter transmits.Therefore, the chip clock estimation error is come out in must will transmitting, and receiver is received that signal errors proofreaies and correct.
Summary of the invention
Technical problem to be solved by this invention provides the method that a kind of spread spectrum system chip clock frequency error is estimated and proofreaied and correct, and the chip frequency that makes receiving terminal receive chip clock signal frequency and transmitter is consistent.
For solving above technical problem, the present invention by the following technical solutions:
A kind of chip clock frequency departure estimation approach of spread spectrum system may further comprise the steps:
Step 1: reception antenna is sampled to L times of speed digital baseband signal with it after the radiofrequency signal that receives is converted to digital baseband signal;
Step 2: the L times of speed digital baseband signal that step 1 obtains carried out the first time synchronously, find out the original position of frame data, judge the type of these frame data then;
Step 3: the signal that step 2 is obtained becomes doubly fast data of M by frequency domain interpolation, wherein, M=4*L, then to M doubly fast data to carry out the second time synchronous, find out the original position of frame data;
Step 4: the data after synchronous to the second time are carried out frequency departure and phase deviation estimation and are removed frequency deviation, skew;
Step 5: the I circuit-switched data of the data that extraction step 4 obtains, obtain the mean value I of its I circuit-switched data then
Mean, with this I circuit-switched data and its mean value I
MeanSubtract each other, constitute the new I circuit-switched data IData that removes direct current offset;
Step 6: the new I circuit-switched data IData that removes direct current offset that step 5 is obtained carries out linear fit, obtains all zero crossing sequence numbers;
Step 7: for each zero crossing sequence number m
i, choose m
i-1, m
iCarry out the first-order linear match with their corresponding data, obtain actual zero passage point value n
i
Step 8: according to the chip number chip of zero crossing correspondence
iWith zero crossing moment t
iFirst-order linear relation obtain actual chip clock frequency f
Chip', and then obtain chip clock frequency error Δ f;
Step 9: the chip clock frequency error Δ f that step 8 is obtained compensates in the actual chip clock frequency, the clock frequency after can obtaining proofreading and correct.
As the preferred embodiments of the present invention, in the step 1, the method that radiofrequency signal is converted to digital baseband signal is: at first radiofrequency signal is carried out down-conversion and be converted into intermediate-freuqncy signal, and then intermediate-freuqncy signal is converted to digital baseband signal;
As the preferred embodiments of the present invention, after described radiofrequency signal is converted to baseband signal, by low-pass filtering, the signal shielding beyond the desired signal bandwidth is fallen;
As the preferred embodiments of the present invention, described step 2 and the synchronous processing described in the step 3 with the method for the original position of finding out frame data are: utilize the barker sign indicating number to slide relevant to front K point of frame data, wherein, K〉L*100, get the point of coefficient correlation maximum, whether judge this point greater than a threshold value, if greater than threshold value, this point is exactly the original position of frame data;
As the preferred embodiments of the present invention, the method of judging the preceding conductivity type of frame data in the described step 2 is: the data cutout one piece of data is synchronously carried out cross-correlation respectively with reference to long and short targeting sequencing, then the data behind the related operation are compared, if the correlated results of long preambles sequence is greater than the correlated results of short leader sequence, judge that then these data are the long preambles sequence, otherwise be short leader sequence; Wherein, the data length of intercepting comprises the length with reference to long preambles sequence and short leader sequence at least;
As the preferred embodiments of the present invention, the frequency domain interpolation method described in the step 3 is: earlier L is doubly mended 0 in fast data back, make it become 2 a Nth power data; The data of mending after 0 are carried out fast Fourier transform; 0,0 number determines by the multiple of interpolation to interleaving in the frequency domain data after the Fourier transform; Data behind the frequency domain interpolation are carried out inverse fast fourier transform, finish interpolation arithmetic;
As the preferred embodiments of the present invention, the computational methods of frequency deviation described in the step 4 and skew are: targeting sequencing is carried out conjugate complex and takes advantage of and obtain n the phase difference θ on the symbol with reference to modulation signal and the actual signal code that receives
nThen, according to phase accumulation side-play amount θ
n=2 π * Δ f*T
s* n+ θ+φ
nTo θ
nCarry out the first-order linear match, i.e. θ
n=k*n+b, wherein, θ
nBe frequency deviation, T
sBe element duration, θ is phase deviation, φ
nBe phase noise, draw coefficient k and b by linear fit.
As the preferred embodiments of the present invention, the determination methods of the zero crossing sequence number described in the step 6 is: for the I circuit-switched data IData of u position
uGet M/2-1 point of front M/2 point and back, if the value of front M/2 point entirely less than zero and the number of back M/2-1 point entirely greater than zero, perhaps the value of front M/2 point entirely greater than zero and the number of back M/2-1 point entirely less than zero, then u to put be zero crossing;
As the preferred embodiments of the present invention, the actual chip clock frequency f described in the described step 8
Chip' computational methods be: order: actual sample frequency is f
s, the chip clock frequency of standard is f
Chip, for i zero crossing constantly
, its corresponding chip number is:
Formula (1) distortion is obtained:
Chip number chip with the zero crossing correspondence
iBe transverse axis, the moment of zero crossing
For the longitudinal axis is done the first-order linear match, the slope of gained is exactly actual chip clock frequency f
Chip' inverse.
Compared with prior art, the chip clock frequency departure estimation approach of spread spectrum system of the present invention has the following advantages at least: in the methods of the invention, after reception antenna receives radiofrequency signal, at first be converted into digital baseband signal, subsynchronous by one successively then, frequency domain interpolation, second synchronization, go frequency deviation and skew, ask the zero crossing sequence number, obtain actual zero passage point value, finally obtain actual chip clock frequency by chip number and the zero crossing first-order linear relation constantly of zero crossing correspondence, and then obtain the chip clock frequency error, compensate and proofread and correct receiving clock frequency, guarantee that the chip clock frequency of transmitter is consistent with the chip clock frequency of receiving terminal.
Description of drawings
Fig. 1 is 802.11b system transmitting terminal physical layer link process schematic diagram.
Fig. 2 is receiver front end processing procedure schematic diagram;
The system block diagram that Fig. 3 estimates for frequency deviation of clock;
Fig. 4 is the flow chart of chip clock estimation error module;
Fig. 5 is the flow chart of zero crossing judge module.
Embodiment
Below in conjunction with Fig. 1 to Fig. 5 the chip clock frequency departure estimation approach of spread spectrum system of the present invention is described in detail:
The technical solution used in the present invention is that the desirable chip clock signal that the reception chip signal received by receiver and this machine produce accurately compares, thereby obtains evaluated error, and the chip clock signal that receives is proofreaied and correct; Its step is as follows:
Step 1: radiofrequency signal receives and signal is handled
Step 2: chip clock Frequency Estimation
Step 3: chip clock error correction
It is that reception antenna is sent transmitting terminal here by the 802.11b agreement radiofrequency signal is converted to digital baseband signal that above-mentioned steps 1 described radiofrequency signal receives.Fig. 2 has illustrated the main flow process of step 1, and its main process is as follows:
Be converted into intermediate-freuqncy signal 1.1 utilize radio-frequency module that radiofrequency signal is carried out down-conversion, and then intermediate-freuqncy signal is converted to digital baseband signal.
1.2 utilize band pass filter that the frequency range beyond the bandwidth is masked, namely baseband signal is carried out low-pass filtering, the signal shielding beyond the desired signal bandwidth is fallen.
1.3 baseband signal is carried out the A/D conversion, and sample frequency is set to J*11MHz (J=2l; L=1,2,3 ...).
1.4 the data after the low-pass filtering are sampled, sampled signals is L times of speed digital baseband signal.
May there be the chip clock error in data after the sampling.The chip clock error can influence the demodulation performance of receiver, therefore, need estimate the chip clock error.
Step 2 chip clock Frequency Estimation described above is that the baseband signal that obtains after step 1 is handled is carried out the module that a chip clock estimation of deviation is added in L times of speed sampling later on.The system block diagram of whole chip clock estimation of deviation module as shown in Figure 3.The handling process of this module is as follows:
2.1. to L doubly fast data to carry out the first time synchronous, find out the roughly original position of frame data.Synchronous principle is: utilize barker sign indicating number (1 ,-1,1,1 ,-1,1,1,1 ,-1 ,-1,-1) to one section of the front of frame data (getting the individual point of K (K〉L*100)) slide relevant (the relevant related operation that namely carries out slidably slides), get the maximum point of coefficient correlation (coefficient correlation is the numerical value that obtains behind the related operation) and whether judge this point greater than a threshold value, if greater than threshold value, this point is exactly Barker code synchronization position (i.e. the original position of frame data).
2.2. to the data of Barker code after synchronously (that is the data after synchronously) for the first time, the intercepting one piece of data carries out cross-correlation respectively with reference to long and short targeting sequencing, can judge the preceding conductivity type of these frame data by comparing the coefficient correlation size, wherein, the standard to the data cutout one piece of data of Barker code after synchronously is: the data length of intercepting comprises the length with reference to long preambles sequence and short leader sequence at least; The method of conductivity type is before judging: at first the data that obtain are carried out related operation respectively with reference to long and short targeting sequencing, then the data behind the related operation are compared, if the correlated results of long preambles sequence is greater than the correlated results of short leader sequence, judge that then these data are the long preambles sequence, otherwise be short leader sequence.
2.3. the L after subsynchronous doubly fast data (comprising the long and short targeting sequencing of determining after the type) becomes doubly speed (M=4*L) data of M by frequency domain interpolation, the purpose of interpolation is the precision that finds the sync bit of frame data and improve the chip clock estimation of deviation for more accurate.The method of frequency domain interpolation is: earlier L is doubly mended 0 in fast data back, make it become 2 a Nth power data (benefit 0 is according to nearby principle); The data of mending after 0 are carried out fast Fourier transform (FFT); Be that multiple by interpolation determines to interleaving 0,0 number in the frequency domain data after the Fourier transform; Data behind the frequency domain interpolation are carried out inverse fast fourier transform, finish interpolation arithmetic.
2.4. to the M after step 2.3 interpolation doubly fast data to carry out the second time synchronous, find out the original position of frame data.Synchronous principle is: utilize step 2.2 determine reference of type long/lack one section of leading front to frame data (getting the individual point of X (X〉M*100)) to slide relevant, get the coefficient correlation maximum point and judge that whether this point is greater than a threshold value, if greater than threshold value, this point is exactly synchronization position.
2.5. the data after step 2.4 second synchronization are carried out frequency departure and phase deviation estimation and are removed frequency deviation, skew.Frequency deviation and skew estimation principles are: targeting sequencing is carried out conjugate complex and takes advantage of and obtain n the phase difference θ on the symbol with reference to modulation signal and the actual signal code that receives
nAccording to phase accumulation side-play amount θ
n=2 π * Δ f*T
s* n+ θ+φ
n(θ
nBe frequency deviation, T
sBe element duration, θ is phase deviation, φ
nBe phase noise), to θ
nCarry out the first-order linear match, i.e. θ
n=k*n+b.The coefficient k and the b that receive by linear fit; Thereby, can draw frequency departure and phase deviation.
2.6. to step 2.5 go after frequency deviation and the skew M doubly fast data carry out the chip clock estimation of deviation.
Step 3 chip clock error correction described above is to estimate that the deviate that obtains compensates on the received signal.
Figure 4 shows that the concrete steps of chip clock error correction, its main process comprises:
3.1. the M that step 2 is obtained the at last doubly I circuit-switched data of fast data (I circuit-switched data namely circuit-switched data) in the same way takes out, and obtains the mean value I of its I circuit-switched data
Mean, then with I circuit-switched data and its mean value I
MeanSubtract each other, thereby constituted one group of new I circuit-switched data IData that removes direct current offset.
3.2. new I circuit-switched data IData is carried out linear fit, obtains wherein all zero crossing sequence number m
i(i=1,2 ... .u).The foundation that zero crossing is judged is: for the I circuit-switched data IData of u position
u, get front M/2 point, M/2-1 point got in the back, if the value of front M/2 point entirely less than zero and the number of back M/2-1 point entirely greater than zero, can judge that then putting for u is zero crossing; If the value of front M/2 point entirely greater than zero and the number of back M/2-1 point entirely less than zero, can judge that also putting for u is zero crossing.In actual design, in order to reduce operand, improve the operating efficiency of the inclined to one side estimation module of clock, only got data partly and judged that its effect is also fine.
3.3. for each zero crossing sequence number m
i, choose m
i-1, m
iCarry out the first-order linear match with their corresponding data, obtain actual zero passage point value n
iThe block diagram of zero crossing judge module as shown in Figure 5.
3.4. suppose that actual sampling rate is f
s, the chip clock frequency of standard is f
Chip, for i zero crossing constantly
, the chip number that it is corresponding
Can be drawn by expression formula (1)
Namely
3.5. can be drawn the chip number chip of zero crossing correspondence by expression formula (3)
iMoment t with zero crossing
iIt is the first-order linear relation.Therefore, with the chip number chip of zero crossing correspondence
iBe transverse axis, the moment of zero crossing
For the longitudinal axis is done the first-order linear match, the slope of gained is exactly actual chip clock frequency f
Chip' inverse.
3.6. with actual chip clock frequency f
Chip' with the chip clock frequency f of receiver reference
ChipSubtract each other, can obtain chip clock frequency error Δ f.
3.7. the chip clock error is converted to PPM (Parts Per Million) unit value, and compensates in the actual chip clock frequency and get final product (chip clock frequency error Δ f namely adds deduct on the basis of actual chip clock frequency).
The present invention has also disclosed a kind of for realizing system for carrying out said process.According to 802.11b agreement regulation, that each frame data comprises is leading, header and physical layer are assembled rules service data units (PSDU:Physical layer convergence protocol Service Data Unit).Leading have long preambles and lack leading two types.Physical layer is carried out scrambling to the data unit, after the band spectrum modulation, is converted into base band data, and transmitter is converted to digital baseband signal continuous signal and sends radio-frequency module to according to certain chip clock frequency to be launched.The main process of transmitting terminal physical layer link as shown in Figure 1.
Because may there be deviation in the chip clock frequency of transmitter and desirable chip clock frequency, at receiving terminal, this deviation may cause receiver can't intactly recover the data that transmitter transmits.Therefore, the chip clock estimation error is come out in must will transmitting, and receiver is received that signal errors proofreaies and correct.
In the present invention, desirable chip clock is 11MHz, the chip clock error that in the process that sends, has 30ppm, the signal channel transmitted is ideal communication channel (signal to noise ratio〉30dB), receiving terminal carries out producing after the front-end processing digital baseband signal of 4 times of speed to it, after 4 times of fast data are gathered, carries out analysis verification with this algorithm, before carrying out the frequency deviation of clock estimation, the data of 4 times of speed have been become the data of 64X by frequency domain interpolation.The chip clock estimation of deviation algorithm that utilizes the present invention to propose is estimated its simulation result 29.8145PPM to the chip clock error, calibrated back and desirable chip clock frequency basically identical.
The above only is one embodiment of the present invention, it or not whole or unique execution mode, the conversion of any equivalence that those of ordinary skills take technical solution of the present invention by reading specification of the present invention is claim of the present invention and contains.
Claims (9)
1. a spread spectrum system chip clock frequency error is estimated and bearing calibration, it is characterized in that: may further comprise the steps:
Step 1: reception antenna is sampled to L times of speed digital baseband signal with it after the radiofrequency signal that receives is converted to digital baseband signal;
Step 2: the L times of speed digital baseband signal that step 1 obtains carried out the first time synchronously, find out the original position of frame data, judge the type of these frame data then;
Step 3: the signal that step 2 is obtained becomes doubly fast data of M by frequency domain interpolation, M=4*L wherein, then to M doubly fast data to carry out the second time synchronous, find out the original position of frame data;
Step 4: the data after synchronous to the second time are carried out frequency departure and phase deviation estimation and are removed frequency deviation, skew;
Step 5: the I circuit-switched data of the data that extraction step 4 obtains, obtain the mean value I of its I circuit-switched data then
Mean, with this I circuit-switched data and its mean value I
MeanSubtract each other, constitute the new I circuit-switched data IData that removes direct current offset;
Step 6: the new I circuit-switched data IData that removes direct current offset that step 5 is obtained carries out linear fit, obtains all zero crossing sequence numbers;
Step 7: for each zero crossing sequence number m
i, choose m
i-1, m
iCarry out the first-order linear match with their corresponding data, obtain actual zero passage point value n
i
Step 8: according to the chip number chip of zero crossing correspondence
iWith zero crossing moment t
iFirst-order linear relation obtain actual chip clock frequency f
Chip', and then obtain chip clock frequency error Δ f;
Step 9: the chip clock frequency error Δ f that step 8 is obtained compensates in the actual chip clock frequency, the clock frequency after can obtaining proofreading and correct.
2. a kind of spread spectrum system chip clock frequency error as claimed in claim 1 is estimated and bearing calibration, it is characterized in that: in the step 1, the method that radiofrequency signal is converted to digital baseband signal is: at first radiofrequency signal is carried out down-conversion and be converted into intermediate-freuqncy signal, and then intermediate-freuqncy signal is converted to digital baseband signal.
3. a kind of spread spectrum system chip clock frequency error as claimed in claim 1 or 2 is estimated and bearing calibration, it is characterized in that: after described radiofrequency signal is converted to baseband signal, by low-pass filtering, the signal shielding beyond the desired signal bandwidth is fallen.
4. a kind of spread spectrum system chip clock frequency error as claimed in claim 1 is estimated and bearing calibration, it is characterized in that: step 2 and the synchronous processing described in the step 3 with the method for the original position of finding out frame data are: utilize the barker sign indicating number to slide relevant to front K point of frame data, wherein, K〉L*100, get the point of coefficient correlation maximum, whether judge this point greater than a threshold value, if greater than threshold value, this point is exactly the original position of frame data.
5. estimate and bearing calibration as claim 1 or 4 described a kind of spread spectrum system chip clock frequency errors, it is characterized in that: the method for judging the preceding conductivity type of frame data in the step 2 is: the data cutout one piece of data is synchronously carried out cross-correlation respectively with reference to long and short targeting sequencing, then the data behind the related operation are compared, if the correlated results of long preambles sequence is greater than the correlated results of short leader sequence, judge that then these data are the long preambles sequence, otherwise be short leader sequence; Wherein, the data length of intercepting comprises the length with reference to long preambles sequence and short leader sequence at least.
6. a kind of spread spectrum system chip clock frequency error as claimed in claim 1 is estimated and bearing calibration, and it is characterized in that: the frequency domain interpolation method described in the step 3 is: earlier L is doubly mended 0 in fast data back, make it become 2 a Nth power data; The data of mending after 0 are carried out fast Fourier transform; 0,0 number determines by the multiple of interpolation to interleaving in the frequency domain data after the Fourier transform; Data behind the frequency domain interpolation are carried out inverse fast fourier transform, finish interpolation arithmetic.
7. a kind of spread spectrum system chip clock frequency error as claimed in claim 1 is estimated and bearing calibration, and it is characterized in that: the computational methods of frequency deviation described in the step 4 and skew are: targeting sequencing is carried out conjugate complex and takes advantage of and obtain n the phase difference θ on the symbol with reference to modulation signal and the actual signal code that receives
nThen, according to phase accumulation side-play amount θ
n=2 π * Δ f*T
s* n+ θ+φ
nTo θ
nCarry out the first-order linear match, i.e. θ
n=k*n+b, wherein, θ
nBe frequency deviation, T
sBe element duration, θ is phase deviation, φ
nBe phase noise, draw coefficient k and b by linear fit.
8. a kind of spread spectrum system chip clock frequency error as claimed in claim 1 estimates and bearing calibration that it is characterized in that: the determination methods of the zero crossing sequence number described in the step 6 is: for the I circuit-switched data IData of u position
uGet M/2-1 point of front M/2 point and back, if the value of front M/2 point entirely less than zero and the number of back M/2-1 point entirely greater than zero, perhaps the value of front M/2 point entirely greater than zero and the number of back M/2-1 point entirely less than zero, then u to put be zero crossing.
9. a kind of spread spectrum system chip clock frequency error as claimed in claim 8 is estimated and bearing calibration, it is characterized in that: the actual chip clock frequency f described in the step 8
Chip' computational methods be: order: actual sample frequency is f
s, the chip clock frequency of standard is f
Chip, for i zero crossing constantly
Its corresponding chip number is:
Formula (1) distortion is obtained:
, wherein, Δ chip
i=chip
i-chip
I-1, Δ n
i=n
i-n
I-1,
Chip number chip with the zero crossing correspondence
iBe transverse axis, the moment of zero crossing
For the longitudinal axis is done the first-order linear match, the slope of gained is exactly actual chip clock frequency f
Chip' inverse.
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| US9722831B2 (en) | 2013-12-02 | 2017-08-01 | Shanghai Eastsoft Microelectronics Co., Ltd. | Carrier frequency offset processing method and apparatus and receiver |
| CN108540417A (en) * | 2018-04-08 | 2018-09-14 | 深圳市盛路物联通讯技术有限公司 | A kind of method of Automatic Frequency Control, system and automatic frequency controller |
| CN112019282A (en) * | 2020-08-13 | 2020-12-01 | 西安烽火电子科技有限责任公司 | Short-wave time-varying channel fading bandwidth estimation method |
| CN112162152A (en) * | 2020-08-31 | 2021-01-01 | 南京亿杰明信息技术有限公司 | Sine wave coherent pulse train signal frequency estimation method based on phase straight line fitting |
| CN114598354A (en) * | 2022-03-18 | 2022-06-07 | 中国电子科技集团公司第十研究所 | Method and device for maintaining continuous phase of frequency hopping system under non-integral multiple sampling rate |
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