CN103188067B - A kind of chip clock frequency departure estimation error of spread spectrum system and the method for correction - Google Patents

Abstract

The invention provides a kind of spread spectrum system chip clock frequency error to estimate and bearing calibration, after reception antenna receives radiofrequency signal, first digital baseband signal is converted into, then subsynchronous by one successively, frequency domain interpolation, second synchronization, go frequency deviation and skew, ask zero crossing sequence number, obtain actual zero passage point value, the chip number corresponding eventually through zero crossing and the first-order linear relation in zero crossing moment obtain actual chip clock frequency, and then obtain chip clock frequency error, realize the compensation to clock frequency and correction, ensure that the chip clock frequency of transmitter is consistent with the chip clock frequency of receiving terminal, improve the demodulation performance of receiver, the data making receiver better recover it to receive.

Description

A kind of chip clock frequency departure estimation error of spread spectrum system and the method for correction

Technical field

The present invention relates to a kind of spread spectrum system chip clock frequency error to estimate and bearing calibration, a kind of method of particularly WiFi system chip clock frequency error estimation and correction.

Background technology

Spread spectrum is to the process much larger than baseband signal bandwidth by the spread spectrum of baseband signal.Spread spectrum communication has stronger anti-interference, anti-multipath performance and the availability of frequency spectrum is high, support the features such as multiple access communication.

WiFi is that the terminals such as computer network interface card and mobile phone are carried out interconnective technology by using radio by one.Be applied in business district widely, university, airport now, and other public domains.WiFi use standard be IEEE definition 802.11 series standards.

802.11b is the agreement using direct sequence spread spectrum skill.At transmitting terminal, data to be sent are formed broadband signal by after chip clock signal spread spectrum, and are modulated, and then transmission of wireless signals are gone out by antenna; At receiving terminal, the receiver chip clock identical with transmitter carries out demodulation to wideband spread-spectrum signal, thus recovers original transmitted data signal.

Because the chip clock frequency of transmitter and the chip clock frequency of receiving terminal may exist deviation, at receiving terminal, the data that this deviation may cause receiver intactly cannot recover transmitter transmitting.Therefore, must will transmit middle chip clock estimation error out, signal errors be received to receiver and corrects.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of method that spread spectrum system chip clock frequency error is estimated and corrected, and the chip frequency making receiving terminal receive chip clock signal frequency and transmitter is consistent.

For solving above technical problem, the present invention by the following technical solutions:

A method for the chip clock frequency offset estimation of spread spectrum system, comprises the following steps:

Step 1: after the radiofrequency signal received is converted to digital baseband signal by reception antenna, is sampled to L speed digital baseband signal;

Step 2: carried out synchronously first time to the L speed digital baseband signal that step 1 obtains, finds out the original position of frame data, then judge the type of these frame data;

Step 3: signal step 2 obtained becomes M speed data by frequency domain interpolation, wherein, M=4*L, then carries out second time synchronously to M speed data, finds out the original position of frame data;

Step 4: the data after synchronous to second time are carried out frequency departure and phase equivocation and removed frequency deviation, skew;

Step 5: the I circuit-switched data of the data that extraction step 4 obtains, then obtains the mean value I of its I circuit-switched data _mean, by this I circuit-switched data and its mean value I _meansubtract each other, form the new I circuit-switched data IData removing direct current offset;

Step 6: linear fit is carried out to the new I circuit-switched data IData removing direct current offset that step 5 obtains, obtains all zero crossing sequence numbers;

Step 7: for each zero crossing sequence number m _i, choose m _i-1, m _icarry out first-order linear matching with the data corresponding to them, obtain actual zero passage point value n _i;

Step 8: the chip number chip corresponding according to zero crossing _iwith zero crossing moment t _ifirst-order linear relation obtain actual chip clock frequency f _chip', and then obtain chip clock frequency error Δ f;

Step 9: chip clock frequency error Δ f step 8 obtained compensates in actual chip clock frequency, can obtain the clock frequency after correcting.

As the preferred embodiments of the present invention, in step 1, the method that radiofrequency signal is converted to digital baseband signal is: first radiofrequency signal is carried out down-conversion and be converted into intermediate-freuqncy signal, and then intermediate-freuqncy signal is converted to digital baseband signal;

As the preferred embodiments of the present invention, after described radiofrequency signal is converted to baseband signal, by low-pass filtering, the signal shielding beyond desired signal bandwidth is fallen;

As the preferred embodiments of the present invention, described step 2 with the synchronous process described in step 3 to find out the method for the original position of frame data is: to carry out slip relevant to K point before frame data to utilize barker code, wherein, K>L*100, get the point that coefficient correlation is maximum, judge whether this point is greater than a threshold value, if be greater than threshold value, this point is exactly the original position of frame data;

As the preferred embodiments of the present invention, judge in described step 2 that the method for the header type of frame data is: respectively with reference to long and short targeting sequencing cross-correlation is carried out to the data cutout one piece of data after synchronous, then the data after related operation are compared, if the correlated results of long preamble is greater than the correlated results of short leader sequence, then judge that these data are long preamble, otherwise be short leader sequence; Wherein, the data length of intercepting at least comprises the length with reference to long preamble and short leader sequence;

As the preferred embodiments of the present invention, the frequency domain interpolation method described in step 3 is: first carry out benefit 0 to after L speed data, makes it become a Nth power data of 2; Fast Fourier transform is carried out to the data after benefit 0; Interleave 0 in the frequency domain data after Fourier transform, the number of 0 is determined by the multiple of interpolation; Inverse fast fourier transform is carried out to the data after frequency domain interpolation, completes interpolation arithmetic;

As the preferred embodiments of the present invention, the computational methods of frequency deviation described in step 4 and skew are: targeting sequencing is carried out conjugate complex with reference to modulation signal and actual Received signal strength symbol and takes advantage of the phase difference θ obtained on the n-th symbol _n; Then, according to phase accumulation side-play amount θ _n=2 π * Δ f*T _s* n+ θ+φ _nto θ _ncarry out first-order linear matching, i.e. θ _n=k*n+b, wherein, θ _nfor frequency deviation, T _sfor element duration, θ is phase deviation, φ _nfor phase noise, draw coefficient k and b by linear fit.

As the preferred embodiments of the present invention, the determination methods of the zero crossing sequence number described in step 6 is: for the I circuit-switched data IData of u position _uget M/2 point and M/2-1 point below above, if above M/2 point value be entirely less than zero and below M/2-1 point number be entirely greater than zero, or above M/2 point value be entirely greater than zero and below M/2-1 put number be entirely less than zero, then u put is zero crossing;

As the preferred embodiments of the present invention, the actual chip clock frequency f described in described step 8 _chip' computational methods be: order: actual sample frequency is f _s, the chip clock frequency of standard is f _chip, for i-th zero crossing moment , the chip number of its correspondence is:

${\mathrm{chip}}_i={\mathrm{chip}}_{i-1}+\frac{(n_i-n_{i-1})}{(f_s/f_{\mathrm{chip}})}$ , formula (1)

Formula (1) distortion is obtained:

, wherein, Δ chip _i=chip _i-chip _i-1, Δ n _i=n _i-n _i-1,

With the chip number chip that zero crossing is corresponding _ifor transverse axis, the moment of zero crossing for the longitudinal axis does first-order linear matching, the slope of gained is exactly actual chip clock frequency f _chip' inverse.

Compared with prior art, the method of the chip clock frequency offset estimation of spread spectrum system of the present invention at least has the following advantages: in the methods of the invention, after reception antenna receives radiofrequency signal, first digital baseband signal is converted into, then subsynchronous by one successively, frequency domain interpolation, second synchronization, go frequency deviation and skew, ask zero crossing sequence number, obtain actual zero passage point value, the chip number corresponding eventually through zero crossing and the first-order linear relation in zero crossing moment obtain actual chip clock frequency, and then obtain chip clock frequency error, compensate receiving clock frequency and correct, ensure that the chip clock frequency of transmitter is consistent with the chip clock frequency of receiving terminal.

Accompanying drawing explanation

Fig. 1 is 802.11b systems radiate end physical layer link process schematic.

Fig. 2 is receiver front end processing procedure schematic diagram;

Fig. 3 is the system block diagram that frequency deviation of clock is estimated;

Fig. 4 is the flow chart of chip clock estimation error module;

Fig. 5 is the flow chart of zero crossing judge module.

Embodiment

Below in conjunction with Fig. 1 to Fig. 5, the method for the chip clock frequency offset estimation of spread spectrum system of the present invention is described in detail:

The technical solution used in the present invention is that the desirable chip clock signal that the receive chip signal received by receiver and the machine are produced carries out accurate comparison, thus obtains evaluated error, and is corrected the chip clock signal received; Its step is as follows:

Step 1: rf signal reception and signal transacting

Step 2: chip clock Frequency Estimation

Step 3: chip clock error correction

Rf signal reception described in above-mentioned steps 1 is that the radiofrequency signal that transmitting terminal is sent here by 802.11b agreement is converted to digital baseband signal by reception antenna.Fig. 2 describes the main flow of step 1, and its main process is as follows:

1.1 utilize radio-frequency module radio frequency signal to carry out down-conversion is converted into intermediate-freuqncy signal, and then intermediate-freuqncy signal is converted to digital baseband signal.

1.2 utilize band pass filter to be fallen by the spectrum mask beyond bandwidth, namely carry out low-pass filtering to baseband signal, are fallen by the signal shielding beyond desired signal bandwidth.

1.3 pairs of baseband signals carry out A/D conversion, and sample frequency is set to J*11MHz (J=2l; L=1,2,3 ...).

Data after 1.4 pairs of low-pass filtering are sampled, and the signal after sampling is L speed digital baseband signal.

Chip clock error may be there is in the data after sampling.Chip clock error can affect the demodulation performance of receiver, therefore, needs to estimate chip clock error.

Step 2 chip clock Frequency Estimation described above is the module of adding a chip clock estimation of deviation after the baseband signal obtained after processing step 1 carries out the sampling of L speed.The system block diagram of whole chip clock deviation estimation block as shown in Figure 3.The handling process of this module is as follows:

2.1. carried out synchronously first time to L speed data, find out the roughly original position of frame data.Synchronous principle is: utilize barker code (1,-1,1,1,-1,1,1,1 ,-1 ,-1,-1) slip relevant (namely sliding is correlated with carries out related operation slidably) is carried out to one section (getting the individual point of K (K>L*100)) before frame data, get coefficient correlation (numerical value obtained after coefficient correlation and related operation) maximum point and judge whether this point is greater than a threshold value, if be greater than threshold value, this point is exactly the synchronous position of Barker code (i.e. the original position of frame data).

2.2. data after synchronous to Barker code (that is first time synchronous after data), intercept one piece of data and carry out cross-correlation respectively with reference to long and short targeting sequencing, the header type of these frame data can be judged by comparing coefficient correlation size, wherein, the standard of the data cutout one piece of data after synchronous to Barker code is: the data length of intercepting at least comprises the length with reference to long preamble and short leader sequence; Judge that the method for header type is: first the data obtained are carried out related operation respectively with reference to long and short targeting sequencing, then the data after related operation are compared, if the correlated results of long preamble is greater than the correlated results of short leader sequence, then judge that these data are long preamble, otherwise be short leader sequence.

2.3. the L speed data (comprising the long and short targeting sequencing after determining type) after subsynchronous become M speed (M=4*L) data by frequency domain interpolation, and the object of interpolation is to find the sync bit of frame data more accurately and improving the precision of chip clock estimation of deviation.The method of frequency domain interpolation is: first carry out benefit 0 to after L speed data, makes it become a Nth power data (mending 0 according to nearby principle) of 2; Fast Fourier transform (FFT) is carried out to the data after benefit 0; Interleave 0 in the frequency domain data after Fourier transform, the number of 0 is determined by the multiple of interpolation; Inverse fast fourier transform is carried out to the data after frequency domain interpolation, completes interpolation arithmetic.

2.4. second time is carried out synchronously to the M speed data after step 2.3 interpolation, find out the original position of frame data.Synchronous principle is: utilizing step 2.2 to determine the reference of type, long/short leading to carry out slip to one section (getting the individual point of X (X>M*100)) frame data before relevant, get coefficient correlation maximum point and judge whether this point is greater than a threshold value, if be greater than threshold value, this point is exactly synchronous position.

2.5. the data after step 2.4 second synchronization carried out frequency departure and phase equivocation and remove frequency deviation, skew.The principle that frequency deviation and skew are estimated is: targeting sequencing is carried out conjugate complex with reference to modulation signal and actual Received signal strength symbol and takes advantage of the phase difference θ obtained on the n-th symbol _n; According to phase accumulation side-play amount θ _n=2 π * Δ f*T _s* n+ θ+φ _n(θ _nfor frequency deviation, T _sfor element duration, θ is phase deviation, φ _nfor phase noise), to θ _ncarry out first-order linear matching, i.e. θ _n=k*n+b.The coefficient k received by linear fit and b; Thus, frequency departure and phase deviation can be drawn.

2.6. frequency deviation is gone to carry out chip clock estimation of deviation with M speed data mutually to the rear to step 2.5.

Step 3 chip clock error correction described above to estimate that the deviate obtained compensates on received signal.

Figure 4 shows that the concrete steps of chip clock error correction, its main process comprises:

The I circuit-switched data of the M speed data 3.1. step 2 finally obtained (I circuit-switched data namely in the same way circuit-switched data) is taken out, and obtains the mean value I of its I circuit-switched data _mean, then by I circuit-switched data and its mean value I _meansubtract each other, thus constitute the new I circuit-switched data IData that a group is removed direct current offset.

3.2. linear fit is carried out to new I circuit-switched data IData, obtain wherein all zero crossing sequence number m _i(i=1,2 ... .u).The foundation that zero crossing judges is: for the I circuit-switched data IData of u position _u, get M/2 point above, after get M/2-1 point, if the value of M/2 point is less than zero and the number of M/2-1 point is greater than zero entirely entirely below, then can judge that u is put as zero crossing above; If the value of M/2 point is greater than zero and the number of M/2-1 point is less than zero entirely entirely below, also can judge that u is put as zero crossing above.In actual design, in order to reduce operand, improve the operating efficiency of the inclined estimation module of clock, the data of only having got part point judge, its effect is also fine.

3.3. for each zero crossing sequence number m _i, choose m _i-1, m _icarry out first-order linear matching with the data corresponding to them, obtain actual zero passage point value n _i.The block diagram of zero crossing judge module as shown in Figure 5.

3.4. suppose that actual sampling rate is f _s, the chip clock frequency of standard is f _chip, for i-th zero crossing moment , the chip number of its correspondence

${\mathrm{chip}}_i={\mathrm{chip}}_{i-1}+\frac{(n_i-n_{i-1})}{(f_s/f_{\mathrm{chip}})}---\left(1\right)$

Can be drawn by expression formula (1)

${\mathrm{chip}}_i={\mathrm{chip}}_{i-1}=\frac{(n_i-n_{i-1})}{f_s}{f}_{\mathrm{chip}}---\left(2\right)$

Namely

${\mathrm{\Δchip}}_i=\frac{{\mathrm{\Δn}}_i}{f_s}{f}_{\mathrm{chip}}---\left(3\right)$

3.5. can draw by expression formula (3) the chip number chip that zero crossing is corresponding _iwith the moment t of zero crossing _iit is first-order linear relation.Therefore, with the chip number chip that zero crossing is corresponding _ifor transverse axis, the moment of zero crossing for the longitudinal axis does first-order linear matching, the slope of gained is exactly actual chip clock frequency f _chip' inverse.

3.6. by actual chip clock frequency f _chip' with the chip clock frequency f of receiver reference _chipsubtract each other, chip clock frequency error Δ f can be obtained.

3.7. chip clock error is converted to PPM (PartsPerMillion) unit value, and compensate in actual chip clock frequency can (namely add deduct on the basis of actual chip clock frequency chip clock frequency error Δ f).

Present invention further teaches a kind of system for realizing said method.According to 802.11b agreement regulation, each frame data comprises leading, header and physical layer assembles code service data unit (PSDU:PhysicallayerconvergenceprotocolServiceDataUnit).Leading have long preambles and short leading two types.Physical layer carries out scrambling to data cell, after band spectrum modulation, is converted into base band data, and digital baseband signal is converted to continuous signal and sends radio-frequency module to according to certain chip clock frequency by transmitter to be launched.The main process of transmitting terminal physical layer link as shown in Figure 1.

Because the chip clock frequency of transmitter and desirable chip clock frequency may exist deviation, at receiving terminal, the data that this deviation may cause receiver intactly cannot recover transmitter transmitting.Therefore, must will transmit middle chip clock estimation error out, signal errors be received to receiver and corrects.

In the present invention, desirable chip clock is 11MHz, the chip clock error of 30ppm is there is in the process sent, the channel of Signal transmissions is ideal communication channel (signal to noise ratio >30dB), receiving terminal produces the digital baseband signal of 4 speeds after carrying out front-end processing to it, after gathering, carry out analysis verification with this algorithm to 4 speed data, before carrying out frequency deviation of clock estimation, the data of 4 speeds are become the data of 64X by frequency domain interpolation.The chip clock estimation of deviation algorithm utilizing the present invention to propose estimates its simulation result 29.8145PPM to chip clock error, and the chip clock frequency with desirable after calibrated is basically identical.

The foregoing is only one embodiment of the present invention, it not whole or unique execution mode, the conversion of those of ordinary skill in the art by reading specification of the present invention to any equivalence that technical solution of the present invention is taked, is claim of the present invention and contains.

Claims (9)

1. spread spectrum system chip clock frequency error is estimated and a bearing calibration, it is characterized in that: comprise the following steps:

Step 1: after the radiofrequency signal received is converted to digital baseband signal by reception antenna, is sampled to L speed digital baseband signal;

Step 2: carried out synchronously first time to the L speed digital baseband signal that step 1 obtains, finds out the original position of frame data, then judge the header type of these frame data;

Step 3: signal step 2 obtained becomes M speed data by frequency domain interpolation, wherein M=4*L, then carries out second time synchronously to M speed data, finds out the original position of frame data;

Step 4: the data after synchronous to second time are carried out frequency departure and phase equivocation and removed frequency deviation, skew;

Step 5: the circuit-switched data in the same way of the data that extraction step 4 obtains, then obtains the mean value I of circuit-switched data in the same way _mean, by this circuit-switched data and its mean value I in the same way _meansubtract each other, form the new circuit-switched data IData in the same way removing direct current offset;

Step 6: linear fit is carried out to the new circuit-switched data IData in the same way removing direct current offset that step 5 obtains, obtains all zero crossing sequence numbers;

Step 7: for each zero crossing sequence number m _i, choose m _i-1, m _icarry out first-order linear matching with the data corresponding to them, obtain actual zero passage point value n _i;

Step 8: the chip number chip corresponding according to zero crossing _iwith zero crossing moment t _ifirst-order linear relation obtain actual chip clock frequency f _chip', and then obtain chip clock frequency error Δ f;

Step 9: chip clock frequency error Δ f step 8 obtained compensates in actual chip clock frequency, can obtain the clock frequency after correcting.

2. a kind of spread spectrum system chip clock frequency error as claimed in claim 1 is estimated and bearing calibration, it is characterized in that: in step 1, the method that radiofrequency signal is converted to digital baseband signal is: first radiofrequency signal is carried out down-conversion and be converted into intermediate-freuqncy signal, and then intermediate-freuqncy signal is converted to digital baseband signal.

3. a kind of spread spectrum system chip clock frequency error as claimed in claim 1 or 2 is estimated and bearing calibration, it is characterized in that: after described radiofrequency signal is converted to baseband signal, by low-pass filtering, is fallen by the signal shielding beyond desired signal bandwidth.

4. a kind of spread spectrum system chip clock frequency error as claimed in claim 1 is estimated and bearing calibration, it is characterized in that: step 2 with the synchronous process described in step 3 to find out the method for the original position of frame data is: to carry out slip relevant to K point before frame data to utilize barker code, wherein, K>L*100, get the point that coefficient correlation is maximum, judge whether this point is greater than a threshold value, if be greater than threshold value, this point is exactly the original position of frame data.

5. a kind of spread spectrum system chip clock frequency error as described in claim 1 or 4 is estimated and bearing calibration, it is characterized in that: in step 2, judge that the method for the header type of frame data is: respectively with reference to long and short targeting sequencing cross-correlation is carried out to the data cutout one piece of data after synchronous, then the data after related operation are compared, if the correlated results of long preamble is greater than the correlated results of short leader sequence, then judge that these data are long preamble, otherwise be short leader sequence; Wherein, the data length of intercepting at least comprises the length with reference to long preamble and short leader sequence.

6. a kind of spread spectrum system chip clock frequency error as claimed in claim 1 is estimated and bearing calibration, it is characterized in that: the frequency domain interpolation method described in step 3 is: first carry out benefit 0 to after L speed data, makes it become a Nth power data of 2; Fast Fourier transform is carried out to the data after benefit 0; Interleave 0 in the frequency domain data after Fourier transform, the number of 0 is determined by the multiple of interpolation; Inverse fast fourier transform is carried out to the data after frequency domain interpolation, completes interpolation arithmetic.

7. a kind of spread spectrum system chip clock frequency error as claimed in claim 1 is estimated and bearing calibration, it is characterized in that: the computational methods of frequency deviation described in step 4 and skew are: targeting sequencing is carried out conjugate complex with reference to modulation signal and actual Received signal strength symbol and takes advantage of the phase difference θ obtained on the n-th symbol _n; Then, according to phase accumulation side-play amount θ _n=2 π * Δ f*T _s* n+ θ+φ _nto θ _ncarry out first-order linear matching, i.e. θ _n=k*n+b, wherein, θ _nfor frequency deviation, T _sfor element duration, θ is phase deviation, φ _nfor phase noise, draw coefficient k and b by linear fit.

8. a kind of spread spectrum system chip clock frequency error as claimed in claim 1 is estimated and bearing calibration, it is characterized in that: the determination methods of the zero crossing sequence number described in step 6 is: for the circuit-switched data IData in the same way of u position _uget M/2 point and M/2-1 point below above, if above M/2 point value be entirely less than zero and below M/2-1 point number be entirely greater than zero, or above M/2 point value be entirely greater than zero and below M/2-1 put number be entirely less than zero, then u put is zero crossing.

9. a kind of spread spectrum system chip clock frequency error as claimed in claim 8 is estimated and bearing calibration, it is characterized in that: the actual chip clock frequency f described in step 8 _chip' computational methods be: order: actual sample frequency is f _s, the chip clock frequency of standard is f _chip, for i-th zero crossing moment the chip number of its correspondence is:

${\mathrm{chip}}_i={\mathrm{chip}}_{i-1}+\frac{(n_i-n_{i-1})}{(f_s/f_{chip})},$ Formula (1)

Formula (1) distortion is obtained:

wherein, Δ chip _i=chip _i-chip _i-1, Δ n _i=n _i-n _i-1,

With the chip number chip that zero crossing is corresponding _ifor transverse axis, the moment of zero crossing for the longitudinal axis does first-order linear matching, the slope of gained is exactly actual chip clock frequency f _chip' inverse.