WO2009155864A1

WO2009155864A1 - Method and device for downlink synchronization tracking

Info

Publication number: WO2009155864A1
Application number: PCT/CN2009/072435
Authority: WO
Inventors: 梁立宏
Original assignee: 中兴通讯股份有限公司
Priority date: 2008-06-24
Filing date: 2009-06-24
Publication date: 2009-12-30
Also published as: CN101615922B; CN101615922A

Abstract

A method and device for downlink synchronization tracking are provided by the present invention. The method includes the following steps: the Downlink Synchronization (SYNC-DL) code in the Downlink Piloting Time Slot (DwPTS) of each subframe is obtained, and the obtained SYNC-DL code data segment is correlated with the SYNC-DL code local to the User Equipment (UE) to obtain the Delay Profile (DP) values; the Power Delay Profile (PDP) values are calculated according to the DP values; Infinite Impulse Response (IIR) filtering is performed on the PDP values of each subframe, and the filtered PDP values are stored; the peak value of the PDP values of each subframe is searched for, and the position of the peak value is output. The present invention can guarantee that the position of the frame head can be captured exactly when the UE moving speed is changed among the static state, the slow speed and the high speed, so the downlink synchronization requirement is satisfied.

Description

Downlink synchronization tracking method and device

Technical field

The present invention relates to the field of code division multiple access (CDMA), and more particularly to a downlink synchronization tracking method and apparatus.

Background technique

In the TD-SCDMA (Time Division Synchronous Code Division Multiple Access) system, the uplink channel and the downlink channel operate at the same frequency and different time slots. For the user equipment (UE, User Equipment), the uplink channel and the downlink channel may interfere with each other. At the same time, there are interferences between different cells, and a better synchronization technique is needed to ensure the communication quality of the TD-SCDMA system.

In practical applications, the UE may be in a scene of stationary, slow moving, or high-speed movement. When moving at a stationary or slow speed, such as indoors or in a walking scene, the downlink synchronization tracking at the UE side can provide stable frame header information, and when the UE moves at high speed, such as in an intercity train or a maglev train scenario, the UE The position of the frame header caused by the fast movement changes rapidly, which brings difficulty to the downlink synchronization tracking of the UE.

In general, the synchronization method in a CDMA system is: Using a pseudo-random code based on pseudo-random number (PN), the frame header information is captured by determining the correlation peak position, that is, the PN code generated locally for the UE The received PN code performs correlation operation to detect the identity of the two signals. If the two signal waveforms are the same, the peak appearing at the advance and the lag is the correlation peak, and the position of the correlation peak is the position of the frame header.

The TD-SCDMA system is also a CDMA system. The frame structure of the TD-SCDMA system is shown in Figure 1, each frame length is 10 ms. Frame i and frame i+1; each frame is divided into two 5 ms sub-frames, and the two sub-frames are identical in structure; each sub-frame is further divided into 7 regular time slots and 3 special times with a length of 675 μ _δ Gap. The seven regular time slots are TS0 to TS6, respectively, and the three special time slots are the downlink pilot time slot (DwPTS, Downlink Piloting Time Slot) of length 96 chips, and the guard interval of length 96chip (GP, Guard). Period ) and uplink pilot time slot of length 160chip (UpPTS, Uplink Piloting Time Slot). In 7 regular time slots, TS0 is always assigned to the downlink, and TS1 is always assigned to the uplink. The uplink time slot and the downlink time slot are separated by a transition point.

The DwPTS has a length of 75 μs and is structured as shown in Figure 2. It includes a 32-chip GP and a 64-chip downlink synchronization (SYNC-DL, Downlink Synchronize) code. In the downlink synchronization tracking of the existing TD-SCDMA system, since the two subframes are identical, the SYNC-DL code of one subframe of the TD-SCDMA transmitted from the far end is related to the local SYNC-DL code of the UE, and the relevant correlation is searched. Peak to achieve.

In the typical channel environment described by the 3GPP (Third Generation Partnership Project), for example, the Additive White Gaussian Noise (AWGN) channel, the simple SYNC of the sub-frame The DL code is associated with the local SYNC-DL code of the UE, and the method of searching for the correlation peak can obtain relatively accurate downlink synchronization information. However, in a multipath fading channel, such as the third case (CASE3), the SYNC-DL code length of the TD-SCDMA system is only 64 chips, which is difficult to capture, especially when the UE moves quickly. Obtaining downlink synchronization information by correlating the SYNC-DL code of a single subframe with the local SYNC-DL code of the UE may not be accurate enough to meet the high-precision synchronization requirements of the TD-SCDMA system. Summary of the invention

In view of this, the main object of the present invention is to provide a downlink synchronization tracking method and apparatus, which filter information between subframes and improve downlink synchronization tracking performance.

In order to achieve the above object, the technical solution of the present invention is achieved as follows:

A downlink synchronization tracking method, the method comprising:

A. Obtain a downlink synchronization SYNC-DL code in the downlink pilot time slot DwPTS in each subframe, and correlate the obtained SYNC-DL code data segment with a downlink synchronization SYNC-DL code locally of the user equipment UE to obtain a delay function. a DP value, and calculating an energy delay function PDP value according to the delay function DP value; wherein, the SYNC-DL data segment in the downlink pilot time slot DwPTS includes a SYNC-DL code sequence and a guard interval of a predetermined number of chips before and after GP; B. Perform an infinite impulse response IIR filtering on the energy delay function PDP value of each subframe, and save the filtered energy delay function PDP value;

C. Find the energy delay function of each sub-frame The peak value of the PDP value, and output the peak position.

Further, the method further includes:

D. Comparing the peak position of the energy delay function PDP value of each subframe with the ideal peak position, and determining and storing the peak identification value of each subframe according to the comparison result;

E. Adjust the filter coefficient according to the statistical result of the peak identification value in the buffer.

Further, step A is specifically:

Al. Obtaining Time Division Synchronous Code Division Multiple Access TD-SCDMA determines the number of GPs, downlink synchronization SYNC-DL codes, and downlink synchronization SYNC-DL codes of a certain number of chips before downlink synchronization SYNC-DL code. Data of the GP of the chip, the data is correlated with the downlink synchronization SYNC-DL code of the user equipment UE by using at least 2 times the sampling rate, and the delay function DP value is obtained;

A2. Perform a n-time interpolation on the DP function of the delay function to obtain a delay function DP interpolation value, where n is a natural number;

A3. Calculating an energy delay function PDP value, the energy delay function PDP value is a delay function

The square of the modulus of the DP interpolated value.

Preferably, the calculation formula of the energy delay function PDP value in step B is: PDP(n) = (1 -α)* PDP(n - \) + a * PDP(n) , where PDP ( n ) is The energy delay function PDP value calculated in the nth subframe, PDP (n-1) is the energy delay function PDP value of the previous subframe of the nth subframe, and the energy delay function PDP value after infinite impulse response IIR filtering , α is the filter coefficient; when η=1, the energy delay function PDP ( 1 ) value is directly saved.

Preferably, the determining rule of the peak identification value of the subframe in step D is:

If the peak position of the energy delay function PDP value of the current subframe is greater than the ideal peak position, the peak identification value of the subframe is 1;

If the peak position of the energy delay function PDP value of the current subframe is less than the ideal peak position, the peak identification value of the subframe is -1; If the peak position of the energy delay function PDP value of the current subframe is equal to the ideal peak position, the peak identification value of the subframe is zero.

Further, the rule for adjusting the filter coefficient in step E is:

Sl, if the peak position of each subframe completely coincides with the ideal peak position, the filter coefficient is reduced; S2, if the peak position of the subframe is less than the ideal peak position exceeds the set threshold, or the peak position of the subframe is larger than the ideal If the number of peak positions exceeds the set threshold, the filter coefficient is increased; all current peak identification values are cleared, and the peak identification values of subsequent subframes are 0;

S3. If it is not the case in S1 or S2, keep the filter coefficient unchanged.

A downlink synchronization tracking device, wherein the device includes: a correlator, an interpolation module, an energy delay function calculation module, a register, a filter, a peak comparator, and an output module, where

The correlator is configured to acquire a downlink synchronous SYNC-DL code data segment in a downlink pilot time slot DwPTS in each subframe of the TD-SCDMA by time division synchronization code division multiple access, and obtain the obtained SYNC-DL code data segment and the user. The downlink synchronization SYNC-DL code of the local UE of the device performs a correlation operation to obtain a delay function DP value of each subframe. The SYNC-DL data segment in the downlink pilot time slot DwPTS includes a SYNC-DL code sequence and before and after. Determining the number of chips of the GP;

The interpolation module is configured to perform n-time interpolation on the DP function of the delay function of each subframe to obtain an interpolation value of the delay function DP value;

The energy delay function calculation module is configured to calculate an energy delay function PDP value of each subframe according to the interpolated value of the DP value;

The register is configured to store an energy delay function PDP value of each subframe;

The filter is configured to perform an infinite impulse response IIR filtering on the energy delay function PDP value of each subframe, and store the filtered energy delay function PDP value back to the corresponding position of the register;

The peak comparator is configured to find a peak value of a PDP value of each subframe, and send a peak position of a PDP value of each subframe to an output module;

The output module is configured to output a peak position of a PDP value of each subframe.

Further, the apparatus further includes a buffer and a filter coefficient adjustment module, where The peak comparator is further configured to compare a peak position and an ideal peak position of a PDP value of each subframe to obtain a peak identification value of each subframe;

The buffer is configured to store a peak identification value of each subframe;

The filter coefficient adjustment module is configured to count the peak identification value in the buffer, adjust the filter coefficient according to the set condition, and send the adjusted filter coefficient to the filter, and the filter performs an infinite impulse response IIR according to the adjusted filter coefficient. Filtering.

Preferably, the buffer is a first in first out buffer.

The SYNC-DL code in the subframe is used as the object of downlink synchronization tracking, and the far-end SYNC-DL code is correlated with the local SYNC-DL code, and the time domain resolution of the original signal is improved by interpolation. And filtering the interference signal through the Infinite Impulse Response (IIR) filter to obtain the correlation peak, and adjusting the filter coefficient α of the IIR filter according to the comparison result of the correlation peak and the ideal peak, thereby ensuring that the UE moving speed is static, When changing between slow speed and high speed, the position of the frame header can be accurately captured to meet the downlink synchronization requirement. BRIEF abstract

1 is a schematic diagram of a frame structure of a TD-SCDMA system;

2 is a schematic structural diagram of a downlink pilot time slot DwPTS;

3 is a flowchart of a downlink synchronization tracking method according to the present invention;

4 is a structural diagram of an embodiment of a downlink synchronization tracking device according to the present invention;

FIG. 5 is a partially improved structural diagram of an embodiment of a downlink synchronization tracking device according to the present invention. Preferred embodiment of the invention

The basic idea of the present invention is to: use the SYNC-DL code in the subframe as the object of downlink synchronization tracking, correlate the far-end SYNC-DL code with the local SYNC-DL code, and use the interpolation method to improve the original signal. The time domain resolution, and filtering the interference signal through the IIR filter to obtain the correlation peak, and adjusting the filter coefficient α of the IIR filter according to the comparison result of the correlation peak and the ideal peak, thereby ensuring the UE moving speed is static, slow, high speed When the transition is made, the position of the frame header can be accurately captured to meet the downlink synchronization requirement. The downlink synchronization tracking method of the TD-SCDMA system will be described below with reference to the accompanying drawings of the present invention.

In this embodiment, the signal speed of the TD-SCDMA system is 350 km/h, and there are 128 sub-frames. The filter coefficient α can be selected as 0.06, 0.125 or 0.25, the peak advance threshold is 6, and the peak delay threshold is 6, which is twice as large. Rate, downlink synchronization tracking accuracy is l/8chip. The sampling rate refers to the number of discrete signals extracted from consecutive signals of the same chip per second. The sampling rate is two samples per chip. The specific process of the downlink synchronization tracking method is shown in Figure 3:

Step 1: Acquire a SYNC-DL code data segment in a downlink pilot time slot DwPTS in each subframe of the TD-SCDMA, and correlate the SYNC-DL code data segment with a local SYNC-DL code of the UE to obtain a delay function (DP) And a delay profile value, the value of the power delay profile (PDP) of each subframe is calculated according to the DP value, where the SYNC-DL data segment in the downlink pilot time slot DwPTS includes the SYNC-DL code sequence and Determine the GP of the number of chips before and after.

Step 1 specifically includes the following steps:

Step 101: Acquire a GP, a SYNC-DL code of a certain number of chips and a GP of a determined number of chips after the SYNC-DL code before the SYNC-DL code of the TD-SCDMA transmitted from the remote end,

Here, the number of chips of the GP before the SYNC-DL code and the number of chips of the GP after the SYNC-DL code are determined according to specific conditions, and are generally determined according to the performance of the terminal and the complexity of the hardware.

Here, the number of chips of the GP before the SYNC-DL code is 32 chips, and the number of chips of the GP after the SYNC-DL code is also 32 chips. The SYNC-DL code is 64chip to obtain a total of 128 chips, 256 samples of data r ( η ), and the data r ( η ) is related to the UE's local SYNC-DL code sync:

DP(n)=r(n) ® conj(sync) ( i ) where 2 represents the convolution operation, r ( n ) represents the data of the received nth subframe, sync is the local SYNC-DL code of the UE, sync For 64 chips, 128 samples, conj represents the conjugate function, DP ( n ) value is the correlation result of the nth subframe, DP ( n ) value is 128 samples, and n is a natural number. The 32chip data before and after the SYNC-DL code is the information between the TD-SCDMA sub-frames. In the subsequent steps, the information is filtered together to eliminate the signal interference between the sub-frames.

Step 102: Perform 4 times interpolation on the DP value to obtain DP interpolated DPinterp with l/8 chip precision. value.

The so-called 4x interpolation is performed between every two DP(n) values. According to the calculation of the DP(n) value, three DPinter values are inserted at equal intervals, and the obtained DPinterp(n) value is 512 samples. The DPinterp ( n ) value spectrum is the data of the DP ( n ) value spectrum which is compressed by 4 times, which improves the time domain resolution of the original signal. There are many mature methods for 4 times interpolation, and will not be described here.

Step 103: Calculate the PDP ( n ) value, and the PDP ( n ) value is the square of the modulus of the complex DPinterp ( n ) value:

PDP(n) = (rea/(DPinterp(«))) ² + (imag(OVmterp(n))f ( ₂ )

The DPinterp ( n ) value is a complex form, including the real part and the imaginary part. In (2), real means the real part, imag means the imaginary part, and the PDP ( n ) value has a total of 512 samples.

Step 2. Perform IIR filtering on the PDP value of each subframe, and save the filtered PDP value. Here, the specific filtering process is: IRP filtering the PDP(n) value calculated in the nth subframe and the PDP(n-1) value stored in the register in the previous subframe, and the filter coefficient α=0.125, the filtering result The PDP ( η ) value is then stored back in the corresponding location of the register:

PDP(n) = (1— ) * PDP(n - \) + a * PDP(n) ( 3 ) where n=l, since there is no previous sub-frame, no filtering is required, and the calculation is saved directly in the register. The PDP (1) value.

Step 3. Find the peak value of the PDP value of each subframe and output the peak position.

The result of the downlink synchronization tracking is to find the peak position of each subframe, and output the peak position to the measurement module, the joint detection module, etc., so that the measurement module, the joint detection module, and the like perform subsequent operations.

The above is to filter the PDP value with a fixed filter coefficient α. This method can meet the requirements of the UE mobile environment change under normal circumstances, but when the UE mobile environment is drastically varied, the synchronous tracking result using the fixed filter coefficient is not Ideally, for this reason, the present invention can also add the following steps after step 3:

Step 4: Comparing the peak position of the PDP value of each subframe with the ideal peak position, and determining and storing the peak identification value of each subframe according to the comparison result. The peak value of the PDP ( n ) value is represented by the PDP ( k ) value, the natural number in [1, 512], since there are 512 samples per subframe, according to the probability statistics, the ideal peak should appear at the 257th sample. Position, compare k and 257, the comparison result indicates whether the actual peak coincides with the ideal peak, and the peak identification flag is used to record the comparison result of k and 257, as shown in equation (4):

Flag = sign(k - 251) ( 4 ) where sign ( X ) is a symbol function, when X is greater than 0, sign ( x ) = 1 , when x is equal to 0, sign ( X ) =0 , X is less than 0, Sign ( x ) = _ 1.

The comparison of the actual peak PDP(k) value position k of each subframe with the ideal peak position 257 results in a flag value, and the flag value of each subframe is saved to the buffer, which is a first in first out of depth of 128. (FIFO, First Input First Output) buffer.

Step 5. Adjust the filter coefficient α according to the statistical result of the peak identification value in the buffer.

The number of 1, 0, and -1 of the flag value in the statistical FIFO is recorded as the peak advance N- early, the peak coincidence N-on, and the peak delay N-delay, respectively, and the filter coefficient α is adjusted according to the following conditions: — οη=128, that is, N—earth=0, and N−delay=0, the filter coefficient α is decreased.

Here, Ν— οη=128 , indicating that the actual peak value of PDP ( η ) completely coincides with the ideal peak position, and the filter coefficient is reduced to track the signal more smoothly. For example: If the current filter coefficient α value is 0.25, the filter coefficient α is reduced to 0.125. If the current filter coefficient α is 0.125, the filter coefficient α is reduced to 0.06.

When N- early > peak advance threshold 6, or N - delay > peak delay threshold 6, the filter coefficient α is increased.

Here, the peak advance or delay exceeds the set threshold, indicating that the current UE may have a fast move, and the filter coefficient needs to be increased to track the signal in time. For example: If the current filter coefficient α value is 0.06, the filter coefficient α is increased to 0.125; when the current filter coefficient α value is 0.125, the filter coefficient α is increased to 0.25.

At the same time, in order to eliminate the influence of the existing flag value in the FIFO on the subsequent tracking, the data in the FIFO is cleared, and in the subsequent 20 subframes, the flag value in the equation (3) is 0.

Except for the above two cases, the filter coefficient α does not change.

In the above method, it is also possible to use more than 2 times the sampling rate as needed to obtain more accurate Data. In step 102, in addition to 4 times interpolation of the DP ( n ) value, n times interpolation may be performed as needed; the real number of the filter coefficient α ζ [0, 1] may be set by the user as needed; the peak early threshold and The peak delay threshold can also be set according to the user's needs; in the second case of step 5, in order to eliminate the influence of the existing flag value on subsequent tracking, the flag value of the subsequent 20 subframes is cleared, the method is for subsequent The flag value forms a guard interval, and the number of cleared subframes can also be increased or decreased according to user needs. According to the above method, the present invention also provides a corresponding downlink synchronization tracking device, an implementation of the device is shown in FIG. 4, the device includes a correlator, an interpolation module, an energy delay function calculation module, a register, a filter, and a peak. Comparator and output module, wherein

a correlator, configured to acquire a downlink pilot time slot DwPTS in each subframe of the TD-SCDMA

SYNC-DL code data segment, correlating the obtained SYNC-DL code data segment with the local SYNC-DL code of the UE to obtain a DP value of each subframe; wherein, the SYNC- in the downlink pilot time slot DwPTS The DL data segment contains a sequence of SYNC-DL codes and a GP that determines the number of chips before and after.

An interpolation module, configured to perform n times interpolation on the DP value of each subframe to obtain a DP value interpolation value; and an energy delay function calculation module, configured to calculate an energy delay function PDP value of each subframe according to the DP value interpolation value ;

a register for storing a PDP value of each subframe;

a filter, configured to perform IIR filtering on the PDP value of each subframe, and store the filtered PDP value back to the corresponding position of the register; a peak comparator for finding the peak value of the PDP value of each subframe, and each subframe The peak position of the PDP value is sent to the output module;

An output module, configured to output a peak position of a PDP value of each subframe.

In order to adapt to the variable channel environment of the UE, the above embodiment may be improved. As shown in FIG. 5, the apparatus may add a buffer and a filter coefficient adjustment module based on the foregoing apparatus. The peak comparator is further configured to compare the peak position and the ideal peak position of the PDP value of each subframe to obtain a peak identification value of each subframe;

a buffer, configured to store a peak identification value of each subframe;

a filter coefficient adjustment module, configured to count the peak identification value in the buffer, and according to the set condition The filter coefficient is adjusted, and the adjusted filter coefficient is sent to the filter, and the filter performs infinite impulse response IIR filtering according to the adjusted filter coefficient.

The buffer is a FIFO buffer, so that the peak identification value changes according to the order of the subframes. The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Any modifications and variations made by those skilled in the art in light of the present invention are intended to be within the scope of the appended claims.

Industrial applicability

The SYNC-DL code in the subframe is used as the object of downlink synchronization tracking, and the SYNC-DL code data segment of the far end is correlated with the local SYNC-DL code, and the time domain of the original signal is improved by interpolation. Resolution, and filtering the interference signal through the IIR filter to obtain the correlation peak. According to the comparison result of the correlation peak and the ideal peak, the filter coefficient α of the IIR filter is adjusted to ensure the UE moving speed is changed between static, slow and high speed. When the frame head position can be accurately captured to meet the downlink synchronization requirements, it has strong industrial applicability.

Claims

1. A downlink synchronization tracking method, the method comprising:

A. Obtain a downlink synchronization SYNC-DL code in the downlink pilot time slot DwPTS in each subframe, and correlate the obtained SYNC-DL code data segment with a downlink synchronization SYNC-DL code locally of the user equipment UE to obtain a delay function. a DP value, and calculating an energy delay function PDP value according to the delay function DP value; wherein, the SYNC-DL data segment in the downlink pilot time slot DwPTS includes a SYNC-DL code sequence and a guard interval of a predetermined number of chips before and after GP;

B. The energy delay function PDP value of each sub-frame is subjected to infinite impulse response IIR filtering, and the filtered energy delay function PDP value is saved;

2. The downlink synchronization tracking method according to claim 1, wherein the method further comprises:

The downlink synchronization tracking method according to claim 1, wherein the step A is specifically:

Al. Obtaining Time Division Synchronous Code Division Multiple Access TD-SCDMA determines the number of GPs, downlink synchronization SYNC-DL codes, and downlink synchronization SYNC-DL codes of a certain number of chips before downlink synchronization SYNC-DL code. Data of the GP of the chip, the data is correlated with the downlink synchronization SYNC-DL code of the user equipment UE by using at least 2 times sampling rate, and the delay function DP value is obtained; A2, the DP function of the delay function is performed. n times interpolation, the delay function DP is interpolated, and n is a natural number;

A3. Calculating an energy delay function PDP value, the energy delay function PDP value is a square of a modulus of a delay function DP interpolation value.

The downlink synchronization tracking method according to claim 1, wherein the calculation formula of the energy delay function PDP value in step B is: ^» = (l -«) * ^ -l) + « * ^» , wherein , PDP ( n ) is the energy delay function PDP value calculated for the nth subframe, and PDP ( n-1 ) is the energy delay function PDP value of the previous subframe of the nth subframe for infinite impulse response IIR filtering The energy delay function PDP value after the wave, α is the filter coefficient; when η=1, the energy delay function PDP ( 1 ) value is directly saved.

The downlink synchronization tracking method according to claim 2, wherein the determining rule of the peak identification value of the subframe in step D is:

If the peak position of the energy delay function PDP value of the current subframe is less than the ideal peak position, the peak identification value of the subframe is -1;

If the peak position of the energy delay function PDP value of the current subframe is equal to the ideal peak position, the peak identification value of the subframe is 0.

The downlink synchronization tracking method according to claim 2, wherein the rule of adjusting the filter coefficient in step Ε is:

51. If the peak position of each subframe completely coincides with the ideal peak position, reduce the filter coefficient;

52. If the peak position of the subframe is smaller than the ideal peak position exceeds the set threshold, or the peak position of the subframe is greater than the ideal peak position exceeds the set threshold, the filter coefficient is increased; The identification value is cleared, and the peak identification value of the subsequent subframes is 0;

53. If it is not the case in S1 or S2, keep the filter coefficients unchanged.

A downlink synchronization tracking device, wherein the device comprises: a correlator, an interpolation module, an energy delay function calculation module, a register, a filter, a peak comparator, and an output module, wherein the correlator is configured to acquire a time division The synchronous code division multiple access accesses the downlink synchronous SYNC-DL code data segment in the downlink pilot time slot DwPTS in each subframe of the TD-SCDMA, and synchronizes the obtained SYNC-DL code data segment with the local downlink of the user equipment UE. The DL code performs a correlation operation to obtain a delay function DP value of each subframe; wherein, the SYNC-DL data segment in the downlink pilot time slot DwPTS includes a SYNC-DL code sequence and a GP of a predetermined number of chips before and after;

The energy delay function calculation module is configured to calculate an energy delay function PDP value of each subframe according to the DP value interpolation value; The register is configured to store an energy delay function PDP value of each subframe;

The downlink synchronization tracking device according to claim 7, wherein the device further comprises a buffer and a filter coefficient adjustment module, wherein

The peak comparator is further configured to compare a peak position and an ideal peak position of a PDP value of each subframe to obtain a peak identification value of each subframe;

The buffer is configured to store a peak identification value of each subframe;

The downlink synchronization tracking device according to claim 8, wherein the buffer is a first-in first-out buffer.