WO2009155864A1 - Procédé et dispositif de suivi de synchronisation de liaison descendante - Google Patents

Procédé et dispositif de suivi de synchronisation de liaison descendante Download PDF

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Publication number
WO2009155864A1
WO2009155864A1 PCT/CN2009/072435 CN2009072435W WO2009155864A1 WO 2009155864 A1 WO2009155864 A1 WO 2009155864A1 CN 2009072435 W CN2009072435 W CN 2009072435W WO 2009155864 A1 WO2009155864 A1 WO 2009155864A1
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WO
WIPO (PCT)
Prior art keywords
value
subframe
delay function
pdp
peak
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PCT/CN2009/072435
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English (en)
Chinese (zh)
Inventor
梁立宏
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中兴通讯股份有限公司
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Publication of WO2009155864A1 publication Critical patent/WO2009155864A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7085—Synchronisation aspects using a code tracking loop, e.g. a delay-locked loop

Definitions

  • the present invention relates to the field of code division multiple access (CDMA), and more particularly to a downlink synchronization tracking method and apparatus.
  • CDMA code division multiple access
  • the uplink channel and the downlink channel operate at the same frequency and different time slots.
  • the uplink channel and the downlink channel may interfere with each other.
  • the UE may be in a scene of stationary, slow moving, or high-speed movement.
  • the downlink synchronization tracking at the UE side can provide stable frame header information, and when the UE moves at high speed, such as in an intercity train or a maglev train scenario, the UE The position of the frame header caused by the fast movement changes rapidly, which brings difficulty to the downlink synchronization tracking of the UE.
  • the synchronization method in a CDMA system is: Using a pseudo-random code based on pseudo-random number (PN), the frame header information is captured by determining the correlation peak position, that is, the PN code generated locally for the UE The received PN code performs correlation operation to detect the identity of the two signals. If the two signal waveforms are the same, the peak appearing at the advance and the lag is the correlation peak, and the position of the correlation peak is the position of the frame header.
  • PN pseudo-random code based on pseudo-random number
  • the TD-SCDMA system is also a CDMA system.
  • the frame structure of the TD-SCDMA system is shown in Figure 1, each frame length is 10 ms.
  • each sub-frame is further divided into 7 regular time slots and 3 special times with a length of 675 ⁇ ⁇ Gap.
  • the seven regular time slots are TS0 to TS6, respectively, and the three special time slots are the downlink pilot time slot (DwPTS, Downlink Piloting Time Slot) of length 96 chips, and the guard interval of length 96chip (GP, Guard).
  • DwPTS downlink pilot time slot
  • GP Guard
  • UpPTS Uplink Piloting Time Slot
  • TS0 is always assigned to the downlink
  • TS1 is always assigned to the uplink.
  • the uplink time slot and the downlink time slot are separated by a transition point.
  • the DwPTS has a length of 75 ⁇ s and is structured as shown in Figure 2. It includes a 32-chip GP and a 64-chip downlink synchronization (SYNC-DL, Downlink Synchronize) code.
  • SYNC-DL Downlink Synchronize
  • the SYNC-DL code of one subframe of the TD-SCDMA transmitted from the far end is related to the local SYNC-DL code of the UE, and the relevant correlation is searched. Peak to achieve.
  • the simple SYNC of the sub-frame The DL code is associated with the local SYNC-DL code of the UE, and the method of searching for the correlation peak can obtain relatively accurate downlink synchronization information.
  • AWGN Additive White Gaussian Noise
  • the SYNC-DL code length of the TD-SCDMA system is only 64 chips, which is difficult to capture, especially when the UE moves quickly.
  • the main object of the present invention is to provide a downlink synchronization tracking method and apparatus, which filter information between subframes and improve downlink synchronization tracking performance.
  • a downlink synchronization tracking method comprising:
  • A. Obtain a downlink synchronization SYNC-DL code in the downlink pilot time slot DwPTS in each subframe, and correlate the obtained SYNC-DL code data segment with a downlink synchronization SYNC-DL code locally of the user equipment UE to obtain a delay function. a DP value, and calculating an energy delay function PDP value according to the delay function DP value; wherein, the SYNC-DL data segment in the downlink pilot time slot DwPTS includes a SYNC-DL code sequence and a guard interval of a predetermined number of chips before and after GP; B. Perform an infinite impulse response IIR filtering on the energy delay function PDP value of each subframe, and save the filtered energy delay function PDP value;
  • the method further includes:
  • step A is specifically:
  • Time Division Synchronous Code Division Multiple Access TD-SCDMA determines the number of GPs, downlink synchronization SYNC-DL codes, and downlink synchronization SYNC-DL codes of a certain number of chips before downlink synchronization SYNC-DL code.
  • Data of the GP of the chip, the data is correlated with the downlink synchronization SYNC-DL code of the user equipment UE by using at least 2 times the sampling rate, and the delay function DP value is obtained;
  • A2 Perform a n-time interpolation on the DP function of the delay function to obtain a delay function DP interpolation value, where n is a natural number;
  • the energy delay function PDP value is a delay function
  • the determining rule of the peak identification value of the subframe in step D is:
  • the peak identification value of the subframe is 1;
  • the peak identification value of the subframe is -1; If the peak position of the energy delay function PDP value of the current subframe is equal to the ideal peak position, the peak identification value of the subframe is zero.
  • step E the rule for adjusting the filter coefficient in step E is:
  • a downlink synchronization tracking device wherein the device includes: a correlator, an interpolation module, an energy delay function calculation module, a register, a filter, a peak comparator, and an output module, where
  • the correlator is configured to acquire a downlink synchronous SYNC-DL code data segment in a downlink pilot time slot DwPTS in each subframe of the TD-SCDMA by time division synchronization code division multiple access, and obtain the obtained SYNC-DL code data segment and the user.
  • the downlink synchronization SYNC-DL code of the local UE of the device performs a correlation operation to obtain a delay function DP value of each subframe.
  • the SYNC-DL data segment in the downlink pilot time slot DwPTS includes a SYNC-DL code sequence and before and after. Determining the number of chips of the GP;
  • the interpolation module is configured to perform n-time interpolation on the DP function of the delay function of each subframe to obtain an interpolation value of the delay function DP value;
  • the energy delay function calculation module is configured to calculate an energy delay function PDP value of each subframe according to the interpolated value of the DP value;
  • the register is configured to store an energy delay function PDP value of each subframe
  • the filter is configured to perform an infinite impulse response IIR filtering on the energy delay function PDP value of each subframe, and store the filtered energy delay function PDP value back to the corresponding position of the register;
  • the peak comparator is configured to find a peak value of a PDP value of each subframe, and send a peak position of a PDP value of each subframe to an output module;
  • the output module is configured to output a peak position of a PDP value of each subframe.
  • the apparatus further includes a buffer and a filter coefficient adjustment module, where The peak comparator is further configured to compare a peak position and an ideal peak position of a PDP value of each subframe to obtain a peak identification value of each subframe;
  • the buffer is configured to store a peak identification value of each subframe
  • the filter coefficient adjustment module is configured to count the peak identification value in the buffer, adjust the filter coefficient according to the set condition, and send the adjusted filter coefficient to the filter, and the filter performs an infinite impulse response IIR according to the adjusted filter coefficient. Filtering.
  • the buffer is a first in first out buffer.
  • the SYNC-DL code in the subframe is used as the object of downlink synchronization tracking, and the far-end SYNC-DL code is correlated with the local SYNC-DL code, and the time domain resolution of the original signal is improved by interpolation. And filtering the interference signal through the Infinite Impulse Response (IIR) filter to obtain the correlation peak, and adjusting the filter coefficient ⁇ of the IIR filter according to the comparison result of the correlation peak and the ideal peak, thereby ensuring that the UE moving speed is static, When changing between slow speed and high speed, the position of the frame header can be accurately captured to meet the downlink synchronization requirement.
  • IIR Infinite Impulse Response
  • FIG. 1 is a schematic diagram of a frame structure of a TD-SCDMA system
  • FIG. 2 is a schematic structural diagram of a downlink pilot time slot DwPTS
  • FIG. 3 is a flowchart of a downlink synchronization tracking method according to the present invention.
  • FIG. 4 is a structural diagram of an embodiment of a downlink synchronization tracking device according to the present invention.
  • FIG. 5 is a partially improved structural diagram of an embodiment of a downlink synchronization tracking device according to the present invention. Preferred embodiment of the invention
  • the basic idea of the present invention is to: use the SYNC-DL code in the subframe as the object of downlink synchronization tracking, correlate the far-end SYNC-DL code with the local SYNC-DL code, and use the interpolation method to improve the original signal.
  • the position of the frame header can be accurately captured to meet the downlink synchronization requirement.
  • the signal speed of the TD-SCDMA system is 350 km/h, and there are 128 sub-frames.
  • the filter coefficient ⁇ can be selected as 0.06, 0.125 or 0.25, the peak advance threshold is 6, and the peak delay threshold is 6, which is twice as large.
  • Rate, downlink synchronization tracking accuracy is l/8chip.
  • the sampling rate refers to the number of discrete signals extracted from consecutive signals of the same chip per second. The sampling rate is two samples per chip. The specific process of the downlink synchronization tracking method is shown in Figure 3:
  • Step 1 Acquire a SYNC-DL code data segment in a downlink pilot time slot DwPTS in each subframe of the TD-SCDMA, and correlate the SYNC-DL code data segment with a local SYNC-DL code of the UE to obtain a delay function (DP) And a delay profile value, the value of the power delay profile (PDP) of each subframe is calculated according to the DP value, where the SYNC-DL data segment in the downlink pilot time slot DwPTS includes the SYNC-DL code sequence and Determine the GP of the number of chips before and after.
  • DP delay function
  • PDP power delay profile
  • Step 1 specifically includes the following steps:
  • Step 101 Acquire a GP, a SYNC-DL code of a certain number of chips and a GP of a determined number of chips after the SYNC-DL code before the SYNC-DL code of the TD-SCDMA transmitted from the remote end,
  • the number of chips of the GP before the SYNC-DL code and the number of chips of the GP after the SYNC-DL code are determined according to specific conditions, and are generally determined according to the performance of the terminal and the complexity of the hardware.
  • the number of chips of the GP before the SYNC-DL code is 32 chips, and the number of chips of the GP after the SYNC-DL code is also 32 chips.
  • the SYNC-DL code is 64chip to obtain a total of 128 chips, 256 samples of data r ( ⁇ ), and the data r ( ⁇ ) is related to the UE's local SYNC-DL code sync:
  • DP(n) r(n) ® conj(sync) ( i )
  • 2 represents the convolution operation
  • r ( n ) represents the data of the received nth subframe
  • sync is the local SYNC-DL code of the UE
  • sync For 64 chips, 128 samples
  • conj represents the conjugate function
  • DP ( n ) value is the correlation result of the nth subframe
  • DP ( n ) value is 128 samples
  • n is a natural number.
  • the 32chip data before and after the SYNC-DL code is the information between the TD-SCDMA sub-frames. In the subsequent steps, the information is filtered together to eliminate the signal interference between the sub-frames.
  • Step 102 Perform 4 times interpolation on the DP value to obtain DP interpolated DPinterp with l/8 chip precision. value.
  • the so-called 4x interpolation is performed between every two DP(n) values.
  • three DPinter values are inserted at equal intervals, and the obtained DPinterp(n) value is 512 samples.
  • the DPinterp ( n ) value spectrum is the data of the DP ( n ) value spectrum which is compressed by 4 times, which improves the time domain resolution of the original signal. There are many mature methods for 4 times interpolation, and will not be described here.
  • Step 103 Calculate the PDP ( n ) value, and the PDP ( n ) value is the square of the modulus of the complex DPinterp ( n ) value:
  • the DPinterp ( n ) value is a complex form, including the real part and the imaginary part.
  • real means the real part
  • imag means the imaginary part
  • the PDP ( n ) value has a total of 512 samples.
  • Step 2 Perform IIR filtering on the PDP value of each subframe, and save the filtered PDP value.
  • the PDP ( ⁇ ) value is then stored back in the corresponding location of the register:
  • the PDP (1) value
  • Step 3 Find the peak value of the PDP value of each subframe and output the peak position.
  • the result of the downlink synchronization tracking is to find the peak position of each subframe, and output the peak position to the measurement module, the joint detection module, etc., so that the measurement module, the joint detection module, and the like perform subsequent operations.
  • step 3 The above is to filter the PDP value with a fixed filter coefficient ⁇ .
  • This method can meet the requirements of the UE mobile environment change under normal circumstances, but when the UE mobile environment is drastically varied, the synchronous tracking result using the fixed filter coefficient is not Ideally, for this reason, the present invention can also add the following steps after step 3:
  • Step 4 Comparing the peak position of the PDP value of each subframe with the ideal peak position, and determining and storing the peak identification value of each subframe according to the comparison result.
  • the peak value of the PDP ( n ) value is represented by the PDP ( k ) value, the natural number in [1, 512], since there are 512 samples per subframe, according to the probability statistics, the ideal peak should appear at the 257th sample.
  • Position, compare k and 257 the comparison result indicates whether the actual peak coincides with the ideal peak, and the peak identification flag is used to record the comparison result of k and 257, as shown in equation (4):
  • Step 5 Adjust the filter coefficient ⁇ according to the statistical result of the peak identification value in the buffer.
  • ⁇ — ⁇ 128 , indicating that the actual peak value of PDP ( ⁇ ) completely coincides with the ideal peak position, and the filter coefficient is reduced to track the signal more smoothly. For example: If the current filter coefficient ⁇ value is 0.25, the filter coefficient ⁇ is reduced to 0.125. If the current filter coefficient ⁇ is 0.125, the filter coefficient ⁇ is reduced to 0.06.
  • the filter coefficient needs to be increased to track the signal in time. For example: If the current filter coefficient ⁇ value is 0.06, the filter coefficient ⁇ is increased to 0.125; when the current filter coefficient ⁇ value is 0.125, the filter coefficient ⁇ is increased to 0.25.
  • the data in the FIFO is cleared, and in the subsequent 20 subframes, the flag value in the equation (3) is 0.
  • step 102 in addition to 4 times interpolation of the DP ( n ) value, n times interpolation may be performed as needed; the real number of the filter coefficient ⁇ ⁇ [0, 1] may be set by the user as needed; the peak early threshold and The peak delay threshold can also be set according to the user's needs; in the second case of step 5, in order to eliminate the influence of the existing flag value on subsequent tracking, the flag value of the subsequent 20 subframes is cleared, the method is for subsequent The flag value forms a guard interval, and the number of cleared subframes can also be increased or decreased according to user needs.
  • the present invention also provides a corresponding downlink synchronization tracking device, an implementation of the device is shown in FIG. 4, the device includes a correlator, an interpolation module, an energy delay function calculation module, a register, a filter, and a peak. Comparator and output module, wherein
  • a correlator configured to acquire a downlink pilot time slot DwPTS in each subframe of the TD-SCDMA
  • the DL data segment contains a sequence of SYNC-DL codes and a GP that determines the number of chips before and after.
  • An interpolation module configured to perform n times interpolation on the DP value of each subframe to obtain a DP value interpolation value
  • an energy delay function calculation module configured to calculate an energy delay function PDP value of each subframe according to the DP value interpolation value
  • a register for storing a PDP value of each subframe
  • a filter configured to perform IIR filtering on the PDP value of each subframe, and store the filtered PDP value back to the corresponding position of the register; a peak comparator for finding the peak value of the PDP value of each subframe, and each subframe The peak position of the PDP value is sent to the output module;
  • An output module configured to output a peak position of a PDP value of each subframe.
  • the apparatus may add a buffer and a filter coefficient adjustment module based on the foregoing apparatus.
  • the peak comparator is further configured to compare the peak position and the ideal peak position of the PDP value of each subframe to obtain a peak identification value of each subframe;
  • a buffer configured to store a peak identification value of each subframe
  • a filter coefficient adjustment module configured to count the peak identification value in the buffer, and according to the set condition The filter coefficient is adjusted, and the adjusted filter coefficient is sent to the filter, and the filter performs infinite impulse response IIR filtering according to the adjusted filter coefficient.
  • the buffer is a FIFO buffer, so that the peak identification value changes according to the order of the subframes.
  • the SYNC-DL code in the subframe is used as the object of downlink synchronization tracking, and the SYNC-DL code data segment of the far end is correlated with the local SYNC-DL code, and the time domain of the original signal is improved by interpolation. Resolution, and filtering the interference signal through the IIR filter to obtain the correlation peak. According to the comparison result of the correlation peak and the ideal peak, the filter coefficient ⁇ of the IIR filter is adjusted to ensure the UE moving speed is changed between static, slow and high speed. When the frame head position can be accurately captured to meet the downlink synchronization requirements, it has strong industrial applicability.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Cette invention se rapporte à un procédé et à un dispositif de suivi de synchronisation de liaison descendante. Le procédé comprend les étapes suivantes : le code de synchronisation de liaison descendante (SYNC-DL) dans l’intervalle de temps de pilotage de liaison descendante (DwPTS) de chaque sous-trame est obtenu, et le segment de données de code obtenu SYNC-DL est corrélé avec le code SYNC-DL local vis-à-vis de l'équipement utilisateur (UE) de manière à obtenir les valeurs de profil de retard (DP); les valeurs de profil de retard de puissance (PDP) sont calculées selon les valeurs DP; un filtrage à réponse impulsionnelle infinie (IIR) est exécuté sur les valeurs PDP de chaque sous-trame et les valeurs PDP filtrées sont stockées; la valeur de crête des valeurs PDP de chaque sous-trame est recherchée et la position de la valeur de crête est délivrée en sortie. La présente invention peut garantir que la position de l'en-tête de trame peut être capturée exactement lorsque la vitesse de déplacement de l'UE change entre l'état statique, une vitesse faible et une vitesse élevée; ainsi l'exigence de synchronisation de liaison descendante est satisfaite.
PCT/CN2009/072435 2008-06-24 2009-06-24 Procédé et dispositif de suivi de synchronisation de liaison descendante WO2009155864A1 (fr)

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CN 200810126320 CN101615922B (zh) 2008-06-24 2008-06-24 一种下行同步跟踪方法及装置
CN200810126320.6 2008-06-24

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CN102447506A (zh) * 2010-10-11 2012-05-09 中兴通讯股份有限公司 提高下行同步可靠性的方法及装置
CN104518786B (zh) * 2013-09-30 2017-12-15 华为技术有限公司 一种自动频率控制方法、自动频率控制装置及用户设备
CN107403441B (zh) * 2016-05-19 2020-11-27 视辰信息科技(上海)有限公司 增强现实系统的跟踪方法和终端设备

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