CN1286587A - Time slot synchronizer in regional search for WCDMA system - Google Patents
Time slot synchronizer in regional search for WCDMA system Download PDFInfo
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- CN1286587A CN1286587A CN 99117207 CN99117207A CN1286587A CN 1286587 A CN1286587 A CN 1286587A CN 99117207 CN99117207 CN 99117207 CN 99117207 A CN99117207 A CN 99117207A CN 1286587 A CN1286587 A CN 1286587A
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Abstract
A time slot synchronizer in region search of WCDMA is composed of A/D converter module, match filter module, energy detector module, threshold comparator and judge module, delay locking module and clock restoration module. The analog base-band signals go through A/D converter, match filter, energy detector and threshold comparator and judge to output time slot synchronizing signals. The main path associated peak signal from the threshold comparator and judge is processed by delay locking and clock restoration modules to generate system clock. Its advantages are high capture speed, less loss of hardware resource and high sensitivity.
Description
The present invention relates to WCDMA (Wideband Code Division Multiple Access (WCDMA)) system of FDD in the 3G (Third Generation) Moblie (Frequency Division Duplexing (FDD)) pattern, relate in particular to the Cell searching technology of MS in the WCDMA system (portable terminal).
In general, cellular system needs two kinds of Cell searchings, promptly recognizes the search of initial zone of initial cell of travelling carriage and the search adjacent cell search when switching adjacent cell.DS-CDMA (Direct-Spread code division multiple access) cellular system can be divided into two classes, promptly carries out strict instant synchronous inter-base station synchronizing system between all base stations, and does not carry out instant synchronous inter base station asynchronous system.Inter-base station synchronizing system use other system such as GPS (global positioning system) realize between the base station synchronously.WCDMA is inter base station asynchronous system.Travelling carriage can directly receive the transmission delay information from neighbor base station like this, so the adjacent cell that can higher speed is used to switch search.But, in search of initial zone,, make Cell searching become relative complex and difficulty because the base station adopts long scrambler as spreading code.
In the WCDMA system, the general three step search methods that adopt of the realization of Cell searching.The first step is caught the basic synchronization channel, finishes slot synchronization, identifies strong basis station; Second step, catch auxiliary synchronization channel, finish frame synchronization, identify scrambler group information; The 3rd step, basic Common Control Physical Channel is asked relevant, identify the scrambler that adopt this sub-district.Slot synchronization is the first step of Cell searching, is the first step that travelling carriage is finished initial synchronisation, also be subsequent frame synchronously, the basis of superframe-synchronized, so be crucial to the accurate extraction of slot synchronization.Slot synchronization is the synchronous capture technology of taking at a kind of specific coded system, this specific coding is meant basic synchronization channel code Cp, and its coded format is from the regulation of 3GPP TS25.213 V2.30 (3GPP is one and is called as the international organization of " 3G (Third Generation) Moblie partner plan ").But, also do not having to find special Technology of Time Slot in disclosed document and the various data at present at this kind coding.
It is fast to the objective of the invention is to propose a kind of acquisition speed, the little and slot synchronization device that is used for the WCDMA Cell searching that still can correctly catch under the situation that big frequency deviation is arranged of hardware resource consumption.
Slot synchronization device in a kind of WCDMA Cell searching comprises the A/D modular converter, matched filter module, and energy detection module, thresholding is judging module relatively, delay locked module and clock recovery module; Described energy detection module comprises a square module, time slot accumulator module and adder; Described delay locked module comprises error energy extraction module, thresholding comparison module and loop filtering module; Base-band analog signal is converted to digital signal behind the A/D modular converter, the digital signal after the conversion is exported correlated peak signal after matched filter module, compares judging module processing back output time solt synchronizing signal through energy detection module and thresholding again; Delay locked module obtains main footpath correlated peak signal from thresholding comparison judging module, handles back output phase error control signal, produces clock signal of system again after clock recovery module is handled, and as A/D sampling clock input A/D modular converter.
Matched filter module described in the scheme is a correlator in the height; Correlator comprises 8 delay units in the height, 8 weighted factors, 13 adders and 8 multipliers; The input serial digital signal is divided into two-way, and one the tunnel enters delay unit, and another road is done plus and minus calculation respectively with the signal of delay unit output after multiply by weighted factor, finishes the one-level computing; Do the signal input time delay unit after the add operation, do signal times behind the subtraction with weighted factor, process before repeating is carried out the next stage computing; Carry out altogether exporting after 8 grades of computings; Wherein the the 4th, the 6th and the 8th grade of computing only carried out add operation and do not carried out subtraction.
The sampling rate of the modular converter of A/D described in the scheme is 1～2 times of spreading rate, and width is got 6～8 bits.
The time slot accumulative frequency of the accumulator module of time slot described in the scheme is generally 4～16 times.
The present invention is described in further detail below in conjunction with accompanying drawing.
Fig. 1 is the general structure block diagram of apparatus of the present invention;
Fig. 2 is the detailed structure schematic diagram of apparatus of the present invention;
Fig. 3 is the relatively workflow diagram of judging module of thresholding;
Fig. 4 is the structural representation of correlator in the height.
Paper is basic synchronization channel code Cp once. Synchronization codes Cp is by code sequence in the general classification height (generalised hierarchical Golay sequence.) consists of. Adopt this coding to be because it has very Good autocorrelation performance aperiodic. Its make-up formula is as follows:
If a=＜X1，X
2，X
3，…，X
16>=<0，0，0，0，0，0，1，1，0，1，0，1，0，1，1，0>
The basic synchronization channel code be by the sequence " a " of complement code modulation in the quilt height repeat produce;
y=<a，a，a，ā，ā，a，ā，ā，a，a，a，ā，a，ā，a，a>
The basic synchronization channel code is defined as follows:
Cp=<y(0)，y(1)，y(2)，…，y(255)>
Wherein leftmost chip y (0) will be the chip that sends at first in the time slot.
The basic synchronization channel is to send signal like this: the modulation that will be the data process basic synchronization channel code of " 1 " entirely becomes I/Q two-way baseband signal, through the QPSK modulation of intermediate frequency carrier, sends through radio frequency again.In the WCDMA of fdd mode system, all sub-districts all send identical, fixing basic synchronization channel.Any travelling carriage always at first detects the basic synchronization channel in when start, just can carry out later work later on obtaining this sub-district slot synchronization.At receiving terminal, radiofrequency signal is at first passed through the QPSK demodulation, removes carrier wave, recovers I/Q two-way baseband signal and handles.Slot synchronization device of the present invention is handled this baseband signal.
Fig. 1 is the general structure block diagram of apparatus of the present invention.As shown in Figure 1, the present invention includes A/D modular converter 11, matched filter module 12, energy detection module 13, thresholding is judging module 14 relatively, delay locked module 15 and clock recovery module 16; Described energy detection module 13 comprises a square module, time slot accumulator module and adder; Described delay locked module 15 comprises error energy extraction module, thresholding comparison module and loop filtering module;
Fig. 2 is the detailed structure schematic diagram of apparatus of the present invention.As shown in Figure 2, wherein A/D modular converter 11 is transformed to digital signal with the base-band analog signal that receives, and generally adopts the sampling rate of 4 * chip or 8 * chip, and width is generally got 6-8bit; 12 pairs of basic synchronization channel code of matched filter module Cp carries out matched filtering, and its output can be exported peak value in corresponding position, and very little at other local correlations; The squaring circuit module is in order to obtain the energy through the filtered signal of matched filter; The multi-slot accumulator module is finished the energy stack of a plurality of time slots; Adder is with the energy summation of I, Q two paths of signals; The signals that thresholding comparison judging module 14 is responsible for obtaining compare with the thresholding of setting, and the slot synchronization that obtains strong basis station most powerful path is indicated; The error energy extraction module compares a previous sampling and a back sampling, and carries out normalization with the energy detection value of current sampling, obtains the phase error voltage signal; Thresholding comparison module 14 is set thresholding relatively, obtains the phase error control signal; The loop filtering module is carried out signal smoothing; Clock recovery module 16 produces clock signal of system, and as A/D sampling clock input A/D modular converter 11.Its signal processing flow is: be divided into I, Q two-way through the later baseband signal of intermediate frequency demodulation, through the A/D conversion, become two ways of digital signals and enter matched filter again, its output meeting produces a plurality of peak values because a plurality of base stations are arranged; In order to guarantee higher acquisition probability, so the several slots that need add up is carried out thresholding relatively then, exceed thresholding continuously several times, think that then slot synchronization catches; Send out synchronous indicating signal and give CPU this moment, starts tracking circuit simultaneously, to guarantee the accurate tracking of clock circuit to main footpath.
In actual applications, the signal more complicated that receives.Because all base stations are all at the basic synchronization channel of sending out identical, so travelling carriage may receive several signal of base station, just signal has the branch of power; In addition, because the influence of multipath also can cause the reception matched filter to export several peak values.This just relates to the problem of mode decision scheme.When not having soft handover, promptly do not have under the situation of upper strata participation, the detected signal to noise ratio of travelling carriage is only depended in choosing of thresholding, generally adopts adaptive threshold, to guarantee acquisition probability.When having soft handover, owing to there is the upper strata to participate in switching between many base stations, the target BS of measurable switching just makes travelling carriage adjudicate at optional several peak by the upper strata notice, can accomplish the slot synchronization with target BS equally.Do not carrying out under the situation of soft handover, travelling carriage can be chosen a base station of energy maximum and carry out initial synchronisation.
Fig. 3 is the relatively workflow diagram of judging module 14 of thresholding, and Fig. 3 has specifically described threshold setting and process relatively.Usually, adaptive threshold is provided with several different methods, and this programme adopts the method for segmentation fixed threshold and adaptive threshold combination, can guarantee accurately to finish slot synchronization.Its concrete workflow is as follows: (1) detection peak energy; (2) judge whether detected peak value surpasses low threshold; (3) if do not surpass low threshold, then think not have the base station that to set up accurate synchronization, restart the detection peak energy; (4), then further judge whether to exceed high threshold if exceed low threshold; (5) if do not exceed high threshold, then at first calculate current signal to noise ratio, judge that then can the signal to noise ratio that calculate reach minimum requirements; (6), then restart the detection peak energy if signal to noise ratio does not meet the demands; (7), then further judge whether to exceed adaptive threshold if signal to noise ratio meets the demands; (8) if exceed adaptive threshold, then obtain peak, the output time solt synchronizing signal, otherwise restart the detection peak energy again after according to the signal to noise ratio that calculates new adaptive threshold being set; (9), then obtain peak, directly the output time solt synchronizing signal if peak signal exceeds high threshold.
After starting tracking circuit, tracking circuit obtains main footpath correlated peak signal from thresholding comparison judging module 14, can obtain time-delay by a simple time-delay sampler, in advance, three relevant outputs of current time, by previous sampling is asked poor with a back relevant output energy of sampling, and carry out normalization with the energy detection value of current sampling, obtain the phase error voltage signal, send into the thresholding comparison then and the loop filtering module obtains the phase error control signal, after handling, clock recovery module 16 produces clock signal of system again, and as A/D sampling clock input A/D modular converter 11, make sampling phase change, be able to accurate tracking master footpath correlated peak signal.The present invention adopts the tracking module of independently delaying time to carry out accurate tracking, has very high precision to guarantee the slot synchronization signal that extracts.
Fig. 4 is the structural representation of correlator in the height, and correlator is the core component of this device in the height.Because the basic synchronization channel code is exactly sign indicating number in a kind of height of deletion (Pruned Golay Code is called for short sign indicating number in the height), so can be with correlator in the height as matched filter at receiving terminal, the basic synchronization channel code that receives is carried out relevant treatment, obtain relevant output.
The iteration of sign indicating number generation formula is in the height:
a
0(k)=δ(k)and?b
0(k)=δ(k)
a
n(k)=a
n-1(k)+W
(j) n·b
n-1(k-D
(j) n)，
b
n(k)=a
n-1(k)-W
(j)n·b
n-1(k-D
(j) n)，
k=0，1，2，…，2
**N
(j)-1，
n=1，2，…，N
(j).
Utilize above-mentioned formula, according to following specified criteria, can obtain basic synchronization channel code sequence generator, it also is to receive correlator in the used height of basic synchronization channel code sequence:
(a)Let?j=0，N
(0)=8
(b)[D
1 0，D
2 0，D
3 0，D
4 0，D
5 0，D
6 0，D
7 0，D
8 0]=[128，64，16，32，8，1，4，2]
(c)[W
1 0，W
2 0，W
3 0，W
4 0，W
5 0，W
6 0，W
7 0，W
8 0]=[1，-1，1，1，1，1，1，1]
(d)For?n=4，6，set?b
4(k)=a
4(k)，b
6(k)=a
6(k)
Correlator comprises D in the height
1～D
8Totally 8 delay units, 8 weighted factor W
1～W
8, 13 adders (comprising subtracter) and 8 multipliers; The input serial digital signal is divided into two-way, and one the tunnel enters delay unit, and another road is done plus and minus calculation respectively with the signal of delay unit output after multiply by weighted factor, finishes the one-level computing; Do the signal input time delay unit after the add operation, do signal times behind the subtraction with weighted factor, process before repeating is carried out the next stage computing; Carry out altogether exporting after 8 grades of computings; Wherein the the 4th, the 6th and the 8th grade of computing only carried out add operation and do not carried out subtraction.Be to have utilized b in the above-mentioned formula only with 13 adders
4(k)=a
4(k), b
6(k)=a
6(k) characteristics, and,,, implement very simple so multiplying is one a symbolic operation because its mould value is 1 for weighted factor.Correlator configuration is simple in the height, made full use of the characteristic of sign indicating number in the height, when sampling rate is 1 times of spreading rate, whole coupling related operation only needs 13 sub-additions just can finish (and adopting general matched filter structure to need 255 sub-additions), significantly reduce operand, thereby reduced the consumption of hardware resource.
Because the present invention has made full use of the characteristic of sign indicating number in the height, correlator is as matched filter in the employing height, so acquisition speed is fast, hardware resource consumption is little; Owing to adopted the tracking module of independently delaying time to carry out accurate tracking, make under the bigger situation of frequency deviation, still to obtain correct slot synchronization signal, make MS (portable terminal) have higher sensitivity.
Claims (4)
1. the slot synchronization device in the WCDMA Cell searching, it is characterized in that: comprise A/D modular converter (11), matched filter module (12), energy detection module (13), thresholding is judging module (14) relatively, delay locked module (15) and clock recovery module (16); Described energy detection module (13) comprises a square module, time slot accumulator module and adder; Described delay locked module (15) comprises error energy extraction module, thresholding comparison module and loop filtering module; Base-band analog signal is converted to digital signal behind A/D modular converter (11), digital signal after the conversion is exported correlated peak signal after matched filter module (12), pass through relatively judging module (14) processing back output time solt synchronizing signal of energy detection module (13) and thresholding again; Delay locked module (15) compares judging module (14) from thresholding and obtains main footpath correlated peak signal, handle back output phase error control signal, after handling, clock recovery module (16) produces clock signal of system again, and as A/D sampling clock input A/D modular converter (11).
2. the slot synchronization device in a kind of WCDMA Cell searching as claimed in claim 1 is characterized in that: described matched filter module (12) is a correlator in the height; Correlator comprises 8 delay units in the height, 8 weighted factors, 13 adders and 8 multipliers; The input serial digital signal is divided into two-way, and one the tunnel enters delay unit, and another road is done plus and minus calculation respectively with the signal of delay unit output after multiply by weighted factor, finishes the one-level computing; Do the signal input time delay unit after the add operation, do signal times behind the subtraction with weighted factor, process before repeating is carried out the next stage computing; Carry out altogether exporting after 8 grades of computings; Wherein the the 4th, the 6th and the 8th grade of computing only carried out add operation and do not carried out subtraction.
3. the slot synchronization device in a kind of WCDMA Cell searching as claimed in claim 1 is characterized in that: the sampling rate of described A/D modular converter (11) is 1～2 times of spreading rate, and width is got 6～8 bits.
4. the slot synchronization device in a kind of WCDMA Cell searching as claimed in claim 1 is characterized in that: the time slot accumulative frequency of described time slot accumulator module is generally 4～16 times.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99117207 CN1133351C (en) | 1999-11-12 | 1999-11-12 | Time slot synchronizer in regional search for WCDMA system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99117207 CN1133351C (en) | 1999-11-12 | 1999-11-12 | Time slot synchronizer in regional search for WCDMA system |
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| CN1286587A true CN1286587A (en) | 2001-03-07 |
| CN1133351C CN1133351C (en) | 2003-12-31 |
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| CN 99117207 Expired - Fee Related CN1133351C (en) | 1999-11-12 | 1999-11-12 | Time slot synchronizer in regional search for WCDMA system |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004066531A1 (en) * | 2003-01-23 | 2004-08-05 | Linkair Communications, Inc. | A method and apparatus for detecting original frame boundary based on a las-cdma system |
| WO2005013524A1 (en) * | 2003-08-04 | 2005-02-10 | Da Tang Mobile Communications Equipment Co., Ltd. | A method and device of the estimating carrier frequency offset of subscriber terminal |
| CN1307810C (en) * | 2003-06-17 | 2007-03-28 | 明基电通股份有限公司 | Slot synchronization for a wcdma system |
| CN100341375C (en) * | 2004-05-31 | 2007-10-03 | 华为技术有限公司 | Device and method for measuring time delay of cell RF transmission channel |
| CN101854219A (en) * | 2010-06-18 | 2010-10-06 | 上海交通大学 | Stochastic resonance based energy detection device and detection method thereof |
| CN101562517B (en) * | 2009-05-22 | 2011-05-11 | 清华大学 | Method and system for non-data-aided synchronization of wireless burst communication all-digital receiver |
| CN101488845B (en) * | 2009-02-24 | 2011-06-15 | 豪威国际控股有限公司 | Multiple phases matching system applied to receiver |
| CN103023529A (en) * | 2012-12-05 | 2013-04-03 | 天津光电通信技术有限公司 | Field programmable gate array (FPGA) based method for achieving synchronous detection of oversampling Golay sequence |
| CN103152075A (en) * | 2013-02-04 | 2013-06-12 | 太原理工大学 | Digital matching filter for WCDMA (wideband code division multiple access) communication |
| CN103596260A (en) * | 2012-08-17 | 2014-02-19 | 京信通信系统（中国）有限公司 | Time slot synchronization method and system of multicarrier GSM system |
| CN105984474A (en) * | 2015-02-10 | 2016-10-05 | 昆明耐维科技有限公司 | Detection method for broken rail based on broadband coding electric signal |
-
1999
- 1999-11-12 CN CN 99117207 patent/CN1133351C/en not_active Expired - Fee Related
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004066531A1 (en) * | 2003-01-23 | 2004-08-05 | Linkair Communications, Inc. | A method and apparatus for detecting original frame boundary based on a las-cdma system |
| CN1307810C (en) * | 2003-06-17 | 2007-03-28 | 明基电通股份有限公司 | Slot synchronization for a wcdma system |
| WO2005013524A1 (en) * | 2003-08-04 | 2005-02-10 | Da Tang Mobile Communications Equipment Co., Ltd. | A method and device of the estimating carrier frequency offset of subscriber terminal |
| US7672277B2 (en) | 2003-08-04 | 2010-03-02 | Datang Mobile Communications Co. Ltd. | Method and device for estimating carrier frequency offset of subscriber terminal |
| CN100341375C (en) * | 2004-05-31 | 2007-10-03 | 华为技术有限公司 | Device and method for measuring time delay of cell RF transmission channel |
| CN101488845B (en) * | 2009-02-24 | 2011-06-15 | 豪威国际控股有限公司 | Multiple phases matching system applied to receiver |
| CN101562517B (en) * | 2009-05-22 | 2011-05-11 | 清华大学 | Method and system for non-data-aided synchronization of wireless burst communication all-digital receiver |
| CN101854219A (en) * | 2010-06-18 | 2010-10-06 | 上海交通大学 | Stochastic resonance based energy detection device and detection method thereof |
| CN101854219B (en) * | 2010-06-18 | 2013-06-19 | 上海交通大学 | Stochastic resonance based energy detection device and detection method thereof |
| CN103596260A (en) * | 2012-08-17 | 2014-02-19 | 京信通信系统（中国）有限公司 | Time slot synchronization method and system of multicarrier GSM system |
| CN103596260B (en) * | 2012-08-17 | 2017-06-16 | 京信通信系统（中国）有限公司 | The slotted synchronous method and system of multicarrier gsm system |
| CN103023529A (en) * | 2012-12-05 | 2013-04-03 | 天津光电通信技术有限公司 | Field programmable gate array (FPGA) based method for achieving synchronous detection of oversampling Golay sequence |
| CN103023529B (en) * | 2012-12-05 | 2014-08-20 | 天津光电通信技术有限公司 | Field programmable gate array (FPGA) based method for achieving synchronous detection of oversampling Golay sequence |
| CN103152075A (en) * | 2013-02-04 | 2013-06-12 | 太原理工大学 | Digital matching filter for WCDMA (wideband code division multiple access) communication |
| CN105984474A (en) * | 2015-02-10 | 2016-10-05 | 昆明耐维科技有限公司 | Detection method for broken rail based on broadband coding electric signal |
| CN105984474B (en) * | 2015-02-10 | 2018-06-22 | 昆明耐维科技有限公司 | A kind of broken rail detection method based on wideband encoding electric signal |
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