CN103151364A - CMOS (Complementary Metal-Oxide-Semiconductor) image sensor and forming method thereof - Google Patents
CMOS (Complementary Metal-Oxide-Semiconductor) image sensor and forming method thereof Download PDFInfo
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Abstract
The invention provides a CMOS (Complementary Metal-Oxide-Semiconductor) image sensor and a forming method thereof. The forming method comprises the following steps of: providing a substrate, wherein the substrate comprises a first pixel region and a second pixel region adjacent to the first pixel region; forming a shallow groove in the substrate, wherein the shallow groove is positioned between the first pixel region and the second pixel region; forming an isolation layer which covers the bottom part and side walls of the shallow groove; after the isolation layer is formed, forming a conductive layer in the shallow groove; and forming a dielectric layer which covers the conductive layer, wherein the dielectric layer and the isolation layer wrap the conductive layer together. The formed CMOS image sensor has the advantages that the performance is stable, the aperture opening ratio of interlinked metal wires is increased, and the sensitivity to light rays is increased.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly cmos image sensor and forming method thereof.
Background technology
The effect of imageing sensor is that optical imagery is converted into the corresponding signal of telecommunication.Imageing sensor is divided into CMOS (Complementary Metal Oxide Semiconductor) (CMOS) imageing sensor and charge-coupled device (CCD) imageing sensor.The advantage of ccd image sensor is higher to the image susceptibility, and noise is little, but ccd image sensor and other devices is integrated more difficult, and the power consumption of ccd image sensor is higher.By contrast, to have technique simple, easily and other devices are integrated, volume is little, lightweight, power consumption is little, low cost and other advantages for cmos image sensor.Cmos image sensor has been widely used in static digital camera, camera cell phone, Digital Video, medical camera head (such as gastroscope), automobile-used camera head etc. at present.
Fig. 1 is the cross section structure schematic diagram of the cmos image sensor of prior art, please refer to Fig. 1, the imageing sensor of prior art comprises: a plurality of photosensitive units 101 that are positioned at substrate 100, a plurality of photosensitive units form the photosensitive unit array, be positioned at the interconnection layer 102 on photosensitive unit 101 surfaces and the metal level 103 that is positioned at interconnection layer 102, be positioned at second flatness layer 104 on interconnection layer 102 surfaces, be positioned at the colored filter 105 on the second flatness layer 104 surfaces, be positioned at first flatness layer 106 on colored filter 105 surfaces, and the lenticule 107 that is positioned at the first flatness layer 106 surfaces.
The formation method of the cmos image sensor of prior art comprises:
Please refer to Fig. 2, substrate 200 is provided, be formed with photosensitive unit 201 in described substrate 200; Formation is positioned at first interlayer dielectric layer 203 on described substrate 200 surfaces; Formation is positioned at the first conductive plunger 204 of described the first interlayer dielectric layer 203;
Please refer to Fig. 3, form the first metal layer 205 be positioned at described the first interlayer dielectric layer 203 surfaces, be connected with described the first conductive plunger 204;
Please refer to Fig. 4-Fig. 5, form the second interlayer dielectric layer 206 that covers described the first interlayer dielectric layer 203 and the first metal layer 205, described the second interlayer dielectric layer 206 of planarization.
The formation method of the cmos image sensor of prior art except above-mentioned steps, also comprises numerous subsequent steps, forms the second flatness layer shown in Figure 1, colored filter, the first flatness layer and lenticule, to form cmos image sensor.
Yet performance, especially its susceptibility to light of the cmos image sensor that prior art forms remains further to be improved.
More formation methods about cmos image sensor please refer to publication number and are the Chinese patent of " CN1787223A ".
Summary of the invention
The problem that the present invention solves is to provide a kind of superior performance, to higher cmos image sensor of the susceptibility of light and forming method thereof.
For addressing the above problem, embodiments of the invention provide a kind of formation method of cmos image sensor, comprising:
Substrate is provided, and described substrate comprises the first pixel region and adjacent the second pixel region with it;
Form shallow trench in described substrate, described shallow trench is between the first pixel region and the second pixel region;
Form the bottom of the described shallow trench of covering and the separator of sidewall;
After forming described separator, form conductive layer in described shallow trench;
Form the dielectric layer that covers described conductive layer, the described conductive layer of the common parcel of described dielectric layer and separator.
Alternatively, also comprise: form conductive pole in described dielectric layer, described conductive pole is electrically connected to conductive layer.
Alternatively, also comprise: form the conducting element or the circuit that are positioned at substrate surface, described conducting element or circuit are electrically connected to conductive layer by conductive pole.
Alternatively, also comprise: the interlayer dielectric layer that form to cover described substrate, dielectric layer surface; Formation is positioned at the conductive plunger of described interlayer dielectric layer, and described conductive plunger is electrically connected to conductive pole.
Alternatively, the forming process of described conductive plunger is: the described interlayer dielectric layer of etching forms the 3rd opening, and described the 3rd opening exposes the partially conductive post; The filled conductive material forms conductive plunger in described the 3rd opening.
Alternatively, described conductive plunger and conductive pole form in same processing step.
Alternatively, also comprise: before forming described interlayer dielectric layer, at the substrate surface formation transistor of described the first pixel region or the second pixel region, described conductive plunger is electrically connected to transistorized grid.
Alternatively, also comprise: after forming conductive plunger, in described interlayer dielectric layer surface formation interconnect metallization lines, described interconnect metallization lines is electrically connected to described conductive plunger.
Alternatively, also comprise: when being formed with active area in the substrate of described the first pixel region or the second pixel region, described active area is electrically connected to described conductive plunger.
Alternatively, the formation technique of described separator is oxidation technology or chemical vapor deposition method.
Alternatively, the material of described separator is silica, silicon nitride or silicon oxynitride.
Alternatively, the formation technique of described conductive layer is depositing operation.
Alternatively, the material of described conductive layer is polysilicon, tungsten, copper, titanium or titanium nitride.
Accordingly, embodiments of the invention also provide a kind of cmos image sensor, comprising:
Substrate, described substrate comprise the first pixel region and adjacent the second pixel region with it;
Be positioned at described intrabasement shallow trench, described shallow trench is between the first pixel region and the second pixel region;
Cover the bottom of described shallow trench and the separator of sidewall;
Be positioned at the conductive layer of the insulation surface of described shallow trench;
Cover the dielectric layer of described conductive layer, the described conductive layer of the common parcel of described dielectric layer and separator.
Alternatively, also comprise: be positioned at the conductive pole of described dielectric layer, described conductive pole is electrically connected to conductive layer.
Alternatively, also comprise: be positioned at conducting element or the circuit of described substrate surface, described conducting element or circuit are electrically connected to conductive layer by conductive pole.
Alternatively, also comprise: the interlayer dielectric layer that covers described substrate, dielectric layer surface; Be positioned at the conductive plunger of described interlayer dielectric layer, described conductive plunger is electrically connected to conductive pole.
Alternatively, also comprise: be positioned at the transistor of the substrate surface of described the first pixel region or the second pixel region, described conductive plunger is electrically connected to transistorized grid.
Alternatively, also comprise: be positioned at the interconnect metallization lines on described interlayer dielectric layer surface, described interconnect metallization lines is electrically connected to described conductive plunger.
Alternatively, also comprise: be positioned at the intrabasement active area of described the first pixel region or the second pixel region, described active area is electrically connected to described conductive plunger.
Alternatively, the material of described separator is silica, silicon nitride or silicon oxynitride.
Alternatively, the material of described conductive layer is polysilicon, tungsten, copper, titanium or titanium nitride.
Compared with prior art, technical scheme of the present invention has the following advantages:
When forming cmos image sensor, after forming separator in the shallow trench between adjacent pixel regions, continuation forms conductive layer in shallow trench, and formation dielectric layer, make the described conductive layer of the common parcel of described dielectric layer and separator, effectively avoid described conductive layer oxidized in the subsequent technique process, make the stable performance of the cmos image sensor of follow-up formation.
Further, the follow-up conductive pole that is electrically connected to described conductive layer that forms in described dielectric layer makes follow-up conducting element or the circuit that is formed on substrate surface be electrically connected to conductive layer by conductive pole.In embodiments of the invention, described conductive layer can substitute part interconnect metallization lines in the cmos image sensor of formation, the aperture opening ratio of the interconnect metallization lines of cmos image sensor increases, make light more easily see through the photosensitive unit that cmos image sensor arrives each pixel cell zone, being the cmos image sensing increases the susceptibility of light, has further improved the performance of cmos image sensor.
Because dielectric layer and separator wrap up conductive layer jointly, described conductive layer is difficult for oxidized, the stable performance of described cmos image sensor, and its structure is simpler.
Further, also comprise: the conductive pole that is positioned at described dielectric layer, described conductive pole is electrically connected to conductive layer, the conducting element or the circuit that are positioned at substrate surface are electrically connected to conductive layer by conductive pole, described conductive layer has substituted the part interconnect metallization lines, the aperture opening ratio of the interconnect metallization lines of cmos image sensor increases, make light more easily see through the photosensitive unit that cmos image sensor arrives each pixel cell zone, being the cmos image sensing increases the susceptibility of light, has further improved the performance of cmos image sensor.
Description of drawings
Fig. 1 is the cross-sectional view of the cmos image sensing of prior art;
Fig. 2-Fig. 5 is the cross-sectional view of forming process of the cmos image sensing of prior art;
Fig. 6-Figure 20 is the cross-sectional view of forming process of the cmos image sensing of the embodiment of the present invention.
Embodiment
Just as stated in the Background Art, the performance of the cmos image sensor of prior art has much room for improvement, and cmos image sensor is lower to the susceptibility of light.
Through research, the inventor finds, the cmos image sensor that prior art forms, fill full isolated material in the shallow trench of adjacent pixel regions, form fleet plough groove isolation structure, and forming the crisscross interconnect metallization lines of multilayer in interconnection layer, corresponding conducting element electrical connection in described each layer interconnect metallization lines and respective pixel unit is transmitted to realize signal.Yet, along with integrated further developing, in prior art, interconnect metallization lines in interconnection layer is more, its structure is comparatively complicated, for example comprise multiple layer metal layer 103 in Fig. 1 in interconnection layer, wherein the structure of the metal level 103 of the bottom is the most complicated, when light is injected by lenticule, be subject to stopping of each layer metal level 103 during through interconnection layer, the restriction of especially the most complicated that layer metal level 103, the light of the actual photosensitive unit that shines pixel region is limited, so cmos image sensor reduces the susceptibility of light.
Through research, the inventor provides a kind of cmos image sensor and forming method thereof, by form the conductive layer isolated with pixel region in shallow trench, make described conductive layer in the part interconnect metallization lines of follow-up alternative cmos image sensor, reach the structure of simplifying cmos image sensor, improve cmos image sensor to the purpose of the susceptibility of light.And, in the cmos image sensor that the inventor provides, also comprise the separator and the dielectric layer that wrap up described conductive layer, conductive layer is difficult for oxidized in subsequent technique, improve the performance of cmos image sensor.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, each embodiment of the present invention is described in detail.
The first embodiment
Please refer to Fig. 6, substrate 300 is provided, described substrate 300 comprises the first pixel region I and adjacent the second pixel region II with it; At the interior formation shallow trench 301 of described substrate 300, described shallow trench 301 is between the first pixel region I and the second pixel region II.
Described substrate 300 is used to subsequent technique that platform is provided.The material of described substrate 300 is semi-conducting material, for example monocrystalline silicon, monocrystalline germanium; Perhaps described substrate 300 can for silicon-on-insulator (SOI) etc., not repeat them here yet.Described substrate 300 comprises a plurality of adjacent pixel regions, comprises photosensitive unit in each pixel region, and described photosensitive unit is used for receiving extraneous light signal, and described light signal is converted to the signal of telecommunication.In embodiments of the invention, carry out exemplary illustrated as an example of the first pixel region I and the second pixel region II example.Described the first pixel region I comprises the first photosensitive unit 300a, and described the second pixel region II comprises the second photosensitive unit 300b.Because the formation technique of described the first photosensitive unit 300a and the second photosensitive unit 300b is well known to those skilled in the art, do not repeat them here.
Described shallow trench 301 is used for follow-up filling isolated material and electric conducting material, forms separator and conductive layer, to isolate the first adjacent pixel region I and the second pixel region II.The formation technique of described shallow trench 301 is etching technics, its concrete forming process comprises: form the first mask layer (not shown) that is positioned at described substrate 300 surfaces, have the first opening (not shown) that defines described shallow trench 301 in described the first mask layer; Take described the first mask layer as mask, along the described substrate 300 formation shallow trenchs 301 of described the first opening sidewalls etched portions thickness.
Please refer to Fig. 7, form to cover described shallow trench 301(as shown in Figure 6) the bottom and the separator 303 of sidewall; After forming described separator 303, at the interior formation conductive layer 305 of described shallow trench 301.
Inventor's discovery, if directly form fleet plough groove isolation structure at the interior filling isolated material of described shallow trench 301, although can play the effect of isolation adjacent pixel regions, its buffer action is comparatively limited.For example, the first photosensitive unit 300a in the first pixel region I receives more light signal, produced more photo-generated carrier, some photo-generated carrier can be spilled in the second pixel region II that is adjacent by the first pixel region I, thereby has affected the stability of cmos image sensor.
after further research, the inventor finds, if with the interior formation of shallow trench 301 and the isolated conductive layer of each pixel region, the follow-up control signal that applies on conductive layer, the interior unnecessary photo-generated carrier of pixel region is exported by conductive layer, and do not affect the image quality of adjacent pixel regions, and described conductive layer can also the Substitute For Partial interconnect metallization lines be connected with other conducting elements or the circuit of cmos image sensor, simplified the structure of interconnect metallization lines in the interconnection layer, it is easier that extraneous light shines into photosensitive unit, cmos image sensor increases the susceptibility of light.
Described separator 303 is used for adjacent the first pixel region I and the second pixel region II of follow-up isolation, and is used for isolation adjacent pixel regions and conductive layer 305.The formation technique of described separator 303 is oxidation technology or chemical vapor deposition method.In embodiments of the invention, the formation technique of described separator 303 is oxidation technology, i.e. obtain after the part substrate 300 of described separator 303 by the bottom of oxidation shallow trench 301 and sidewall, and the material of described separator 303 is silica.
Need to prove, in other embodiments of the invention, when adopting chemical vapor deposition method, the material of described separator can also for silicon nitride or silicon oxynitride etc., not repeat them here except being silica.
Described conductive layer 305 is positioned at shallow trench 301, be used for the performance of follow-up raising cmos image sensor, prevent the generation of crosstalk phenomenon, and follow-up also alternative part interconnect metallization lines, simplify the structure of interconnect metallization lines in interconnection layer, improve the light sensitive degree of cmos image sensor.The formation technique of described conductive layer 305 is depositing operation, for example physical gas-phase deposition or chemical vapor deposition method.The material of described conductive layer 305 is polysilicon, tungsten, copper, titanium or titanium nitride.Its forming process comprises: form to cover the conductive film on substrate 300 surfaces of described separator 303, the first pixel region I and the second pixel region II, described conductive film is filled full described shallow trench 301; Remove to cover the partially conductive film on substrate 300 surfaces of the first pixel region I and the second pixel region II.
In an example of the present invention, adopt the separator 303 surface deposition polycrystalline silicon materials of chemical vapor deposition method in described shallow trench 301, forming material is the conductive layer 305 of polysilicon.And, be the electric conductivity of enhancing conductive layer 305, and reduce the follow-up current potential that is input to the control signal of conductive layer 305, can also at the interior doped N-type ion of described conductive layer 305, not repeat them here.
In another example of the present invention, the material of described conductive layer 305 is tungsten, and the contact resistance between the conductive pole of tungsten and follow-up formation is little, can further reduce the current potential of the control signal of follow-up input, and can effectively improve the performance of cmos image sensor.
In embodiments of the invention, also comprise: the conductive film of removing the segment thickness in shallow trench 301 forms conductive layer 305, described conductive layer 305 surfaces are a little less than substrate 300 surfaces of described the first pixel region I and the second pixel region II, be beneficial to substrate 300 flush of dielectric layer and the first pixel region I and the second pixel region II of follow-up formation, the more compact structure of the cmos image sensor of formation.
Need to prove, in other embodiments of the invention, described conductive layer 305 surfaces also can be higher than substrate 300 surfaces of described the first pixel region I and the second pixel region II, perhaps with substrate 300 flush of described the first pixel region I and the second pixel region II, do not repeat them here.
Please refer to Fig. 8, form the dielectric layer 307 that covers described conductive layer 305, described dielectric layer 307 and the separator 303 described conductive layers 305 of common parcel.
The inventor finds, usually after executing above-mentioned steps, also can longer a period of time of interval carry out again some subsequent steps, form other structures etc. such as substrate 300 surface at the first pixel region I and the second pixel region II, if the said structure that directly will form after conductive layer 305 is exposed in air, conductive layer 305 is very easily oxidized, and is second-rate, the performance of the cmos image sensor of the follow-up formation of impact.And if at described conductive layer 305 surface coverage dielectric layers 307, make described dielectric layer 307 with described separator 303 jointly with described conductive layer 305 parcels, effectively avoided the generation of the problems referred to above, the superior performance of the cmos image sensor of formation.
Described dielectric layer 307 is used for preventing that conductive layer 305 is oxidized, improves the performance of cmos image sensor.The formation technique of described dielectric layer 307 is depositing operation, and the material of described dielectric layer 307 is silica, silicon nitride or silicon oxynitride etc.In an embodiment of the present invention, the material of described dielectric layer 307 is identical with the material of separator 303, is silica, and dielectric layer 307 is better with separator 303 combinations, parcel conductive layer 305 is more tight, is conducive to further improve the performance of cmos image sensor.
Please continue with reference to figure 8, after above-mentioned steps, the cmos image sensor of formation comprises:
Be positioned at the shallow trench 301(of described substrate 300 as shown in Figure 6), described shallow trench 301 is between the first pixel region I and the second pixel region II;
Cover the bottom of described shallow trench 301 and the separator 303 of sidewall;
Be positioned at the conductive layer 305 on separator 303 surfaces of described shallow trench 301;
Cover the dielectric layer 307 of described conductive layer 305, described dielectric layer 307 and the separator 303 described conductive layers 305 of common parcel.
The conductive layer 305 of described cmos image sensor is wrapped up jointly by dielectric layer 307 and separator 303, effectively avoided described conductive layer 305 oxidized in the subsequent technique process, the stable performance of described cmos image sensor, and the follow-up alternative part interconnect metallization lines of described conductive layer 305, the aperture opening ratio of the interconnect metallization lines of cmos image sensor is increased, the structure of interconnect metallization lines is simpler, and the light sensitive degree increases.
Consider that the structure of cmos image sensor is different when adopting said method to form cmos image sensor, its formation method is also slightly different, and the below's minute Multi-instance carries out exemplary illustrated.
Example 1
In example 1 of the present invention, described conductive layer 305 is follow-up to be electrically connected to the interconnect metallization lines on interlayer dielectric layer surface, and its concrete forming process is as follows:
Please refer to Fig. 9, form to cover the interlayer dielectric layer 309 on described substrate 300, dielectric layer 307 surfaces; Formation is positioned at second mask layer 311 on described interlayer dielectric layer 309 surfaces, and described the second mask layer 311 has the second opening 313, and described the second opening 313 defines position and the size of conductive plunger.
Described interlayer dielectric layer 309 is used for isolation substrate 300 and the follow-up interconnect metallization lines that is formed on interlayer dielectric layer 309 surfaces.The material of described interlayer dielectric layer 309 is dielectric material, such as silica, silicon nitride or silicon oxynitride etc.The formation technique of described interlayer dielectric layer 309 is depositing operation, does not repeat them here.In the first embodiment of the present invention, the material of described interlayer dielectric layer 309 is silicon oxynitride, adopts chemical vapor deposition method to form.
The material of described the second mask layer 311 is photoresist, and it forms technique is exposure, development etc., does not repeat them here.The second opening 313 in described the second mask layer 311 defines position and the size of conductive plunger.
Please refer to Figure 10, take described the second mask layer 311 as mask, form the 3rd opening 315 along described the second opening 313 described interlayer dielectric layers 309 of etching, the described dielectric layer 307 of etching forms the 4th opening 317 that exposes conductive layer 305.
Described the 3rd opening 315 is used for follow-up filled conductive material and forms conductive plunger.The formation technique of described the 3rd opening 315 is anisotropic dry etch process, and the size of described the 3rd opening 315 is big or small identical with described the second opening 313; Described the 4th opening 317 is used for follow-up filled conductive material and forms conductive pole, and the formation technique of described the 4th opening 317 is anisotropic dry etch process.In embodiments of the invention, described the 3rd opening 315 and the 4th opening 317 form in same etching technics, the 3rd opening 315 of formation and the 4th opening 317 big or small identical.
Please refer to Figure 11, to described the 4th opening 317 and the interior filled conductive material of the 3rd opening 315, form the conductive pole 319 that is positioned at described dielectric layer 307 and the conductive plunger 321 that is positioned at interlayer dielectric layer 309; Remove described the second mask layer 311(as shown in figure 10).
Described conductive pole 319 is formed in described dielectric layer 307, and is electrically connected to described conductive layer 305.Described conductive plunger 321 is formed in interlayer dielectric layer 309, and is electrically connected to described conductive pole 319.
Need to prove, in other embodiments of the invention, also can: before forming interlayer dielectric layer 309, expose the 4th opening 317 of conductive layer 305 in the interior formation of dielectric layer 307, and form conductive pole 319 at described the 4th interior filled conductive material of opening 317; The 3rd opening 315 of described interlayer dielectric layer 309 interior formation exposes the described conductive pole 319 of part; Form conductive plunger 321 at described the 3rd interior filled conductive material of opening 315.
The technique of removing described the second mask layer 311 is etching technics or cineration technics.Removing the technique of described the second mask layer 311 can carry out after forming conductive plunger 321, also can carry out before forming conductive plunger 321, does not repeat them here.
Please refer to Figure 12, form the interconnect metallization lines 323 that is positioned at described interlayer dielectric layer 309 surfaces, described interconnect metallization lines 323 is electrically connected to described conductive plunger 321.
Described interconnect metallization lines 323 is used for transmission of electric signals, and the material of described interconnect metallization lines 323 is tungsten, aluminium, copper or other metal materials, does not repeat them here.In embodiments of the invention, the material of interconnect metallization lines 323 is tungsten, and described interconnect metallization lines 323 has finally realized and being electrically connected to of conductive layer 305 by conductive plunger 321, conductive pole 319.Therefore, part interconnect metallization lines 323 in the alternative interconnection layer of described conductive layer 305, transmission of electric signals, effectively simplified the structure of cmos image sensor, the aperture opening ratio of the interconnect metallization lines of cmos image sensor increases, make light more easily see through the interconnect metallization lines 323 of the cmos image sensor of the present embodiment, arrive the photosensitive region of pixel cell, the light sensitive degree increases.
In example 1 of the present invention, the cmos image sensor of formation also comprises: be positioned at the conductive pole 319 of described dielectric layer 307, described conductive pole 319 is electrically connected to conductive layer 305; Cover the interlayer dielectric layer 309 on described substrate 300, dielectric layer 307 surfaces; Be positioned at the conductive plunger 321 of described interlayer dielectric layer 309, described conductive plunger 321 is electrically connected to described conductive pole 319; Be positioned at the interconnect metallization lines 323 on described interlayer dielectric layer surface 309, described interconnect metallization lines 323 is electrically connected to described conductive plunger 321.
in the example 1 of the embodiment of the present invention, the conductive layer 305 of described cmos image sensor is except being isolated layer 303 and dielectric layer 307 parcels, also be electrically connected to the interconnect metallization lines 323 on interlayer dielectric layer 309 surfaces by conductive pole 319 and conductive plunger 321, therefore, part interconnect metallization lines 323 in the alternative former cmos image sensor of described conductive layer 305 in interconnection layer, especially the most complicated that layer interconnect metallization lines 323 of alternative part-structure, in the example 1 of the embodiment of the present invention, the aperture opening ratio of the interconnect metallization lines of cmos image sensor increases, interconnect metallization lines 323 simple in structure, susceptibility to light increases, and the superior performance of cmos image sensor.
Example 2
Different from example 1, the first pixel region of example 2 or the substrate surface of the second pixel region form transistor, realize being electrically connected to of above-mentioned transistorized grid and conductive layer, and it specifically forms step and comprises:
Please refer to Figure 13, at the substrate 300 surface formation transistors of described the first pixel region I or the second pixel region II.
The photosensitive unit of described each pixel cell of transistor AND gate staggers mutually, enters photosensitive unit to avoid transistor to obstruct the light.Described transistor comprises the gate insulation layer 401 that is positioned at described substrate 300 surfaces, covers the gate electrode layer 403 on described gate insulation layer 401 surfaces, is positioned at the side wall 405 on substrate 300 surfaces of described gate electrode layer 403 and gate insulation layer 401 both sides.
Wherein, described gate insulation layer 401 is used for isolated transistor and substrate 300, and the material of described gate insulation layer 401 is insulating material, for example silica or high K dielectric material; Described gate electrode layer 403 is used for as transistorized grid, and the material of described gate electrode layer 403 is polysilicon or metal; Described side wall 405 is not damaged in subsequent technique for the protection of gate electrode layer 403 and gate insulation layer 401, and the material of described side wall 405 is silicon nitride or silicon oxynitride etc., does not repeat them here.
Please refer to Figure 14, form to cover the interlayer dielectric layer 409 on described substrate 300, dielectric layer 307 and transistor surface; Formation is positioned at second mask layer 411 on described interlayer dielectric layer 409 surfaces, and described the second mask layer 411 has the second opening 413, and described the second opening 413 defines position and the size of conductive plunger.
Described interlayer dielectric layer 409 is used for isolation substrate 300 and follow-up conducting element or the circuit that is formed on interlayer dielectric layer 409 surfaces.The material of described interlayer dielectric layer 409 is dielectric material, such as silica, silicon nitride or silicon oxynitride etc.
The material of described the second mask layer 411 is photoresist, and it forms technique is exposure, development etc., does not repeat them here.The second opening 413 in described the second mask layer 411 defines position and the size of conductive plunger.Consider that follow-up conductive plunger both was electrically connected to conductive layer 305, be electrically connected to transistorized grid again, the second opening 413 in example 2 be positioned at partially conductive layer 305 and transistorized part of grid pole directly over.
More details please refer to the associated description in example 1, do not repeat them here.
Please refer to Figure 15, take described the second mask layer 411 as mask, form the 3rd opening 415 along described the second opening 413 described interlayer dielectric layers 409 of etching, the described dielectric layer 307 of etching forms the 4th opening 417 that exposes conductive layer 305.
Described the 3rd opening 415 is used for follow-up filled conductive material and forms conductive plunger, and described the 4th opening 417 is used for follow-up filled conductive material and forms conductive pole.Different from example 1 is that described the 3rd opening 415 also exposes the side wall 405 of transistorized part gate electrode layer 403 and close conductive layer 305 1 sides, is beneficial to the conductive plunger that follow-up formation is electrically connected to described transistorized grid.More heterogeneous pass is described and be please refer to example 1, does not repeat them here.
Please refer to Figure 16, to described the 4th opening 417 and the interior filled conductive material of the 3rd opening 415, form the conductive pole 419 that is positioned at described dielectric layer 307 and the conductive plunger 421 that is positioned at interlayer dielectric layer 409; Remove described the second mask layer 411(as shown in figure 15).
Described conductive pole 419 is formed in described dielectric layer 307, and is electrically connected to described conductive layer 305.Described conductive plunger 421 is formed in interlayer dielectric layer 409, and described conductive plunger 421 also is electrically connected to transistorized grid (being gate electrode layer 403) except with described conductive pole 419 is electrically connected to.Be that described conductive layer 305 is electrically connected to described transistorized grid, this moment, described conductive layer 305 served as the interconnect metallization lines use of the former cmos image sensor of part, effectively simplify the structure of the cmos image sensor of example 2, improved the susceptibility of cmos image sensor to light.
After above-mentioned steps, the cmos image sensor in example 2 structure in having Fig. 8, also comprises: be positioned at the conductive pole 419 of described dielectric layer 307, described conductive pole 419 is electrically connected to conductive layer 305; Be positioned at the transistor on substrate 300 surfaces of described the first pixel region I or the second pixel region II; Cover the interlayer dielectric layer 409 on described substrate 300, dielectric layer 307 and transistor surface; Be positioned at the conductive plunger 421 of described interlayer dielectric layer 409, described conductive plunger 421 is electrically connected to conductive pole 419, and is electrically connected to transistorized grid (being gate electrode layer 403).
The cmos image sensor that example 2 provides, described conductive layer 305 is electrically connected to transistorized grid by conductive pole 419 and conductive plunger 421, make the interconnect metallization lines of the part-structure complexity of described conductive layer 305 alternative former cmos image sensors, the aperture opening ratio of the interconnect metallization lines of the cmos image sensor in example 2 increases, interconnect metallization lines simple in structure, susceptibility to light increases, and the quality of the conductive layer 305 of cmos image sensor is good, be difficult for oxidized, the stable performance of cmos image sensor.
Example 3
Different from example 1, example 2, the substrate 300 of the second pixel region of example 3 is active area, realize being electrically connected to of conductive layer and active area, and it forms step and comprises:
Please refer to Figure 17, form the conductive pole 519 that is positioned at described dielectric layer 307; Form to cover the interlayer dielectric layer 509 on described substrate 300, dielectric layer 307 surfaces; Formation is positioned at the conductive plunger 521 of described interlayer dielectric layer 509, and described conductive plunger 521 is electrically connected to described conductive pole 519.
Described interlayer dielectric layer 509 is used for isolation substrate 300 and the follow-up interconnect metallization lines that is formed on interlayer dielectric layer 509 surfaces.The material of described interlayer dielectric layer 509 is dielectric material, such as silica, silicon nitride or silicon oxynitride etc.
Described conductive pole 519 is used for being electrically connected to conductive plunger 521 and conductive layer 305, and the material of described conductive pole 519 is electric conducting material, and it is formed in dielectric layer 307; Described conductive plunger 521 is used for being electrically connected to conductive pole 519 and substrate 300(is active area), to realize being electrically connected to of conductive layer 305 and substrate 300.Described conductive pole 519 can form in same processing step, also can form step by step.Formation step and the technique of described conductive pole 519 and conductive plunger 521 please refer to previous embodiment, do not repeat them here.
Need to prove, in other embodiments of the invention, all right: etching directly is electrically connected to the conductive pole 519 of formation, and does not need to form conductive plunger 521 again near the part separator of the second pixel region II with the substrate 300 of the second pixel region II.This kind formation method is simpler.
The formation method of example 3 is simple, by forming conductive plunger 521 and conductive pole 519, make the conductive layer 305 of mutual isolation originally and the substrate 300(active area of the second pixel region II) be electrically connected to, make described conductive layer 305 effectively serve as part interconnect metallization lines in former cmos image sensor, simplified the structure of cmos image sensor, increased the aperture opening ratio of the interconnect metallization lines of cmos image sensor, improved the susceptibility of cmos image sensor to light, and the stable performance of cmos image sensor.
After above-mentioned steps, the cmos image sensor of formation also comprises: be positioned at the conductive pole 519 of described dielectric layer 307, described conductive pole 519 is electrically connected to conductive layer 305; Cover the interlayer dielectric layer 509 on described substrate 300, dielectric layer 307 surfaces; Be positioned at the conductive plunger 521 of described interlayer dielectric layer 509, described conductive plunger 521 is electrically connected to conductive pole 519, and is electrically connected to the substrate 300 of the second pixel region II.
Need to prove, in other embodiments of the invention, described conductive plunger 521 can also be electrically connected to the substrate 300 of the first pixel region I, does not repeat them here.
In the cmos image sensor of example 3 of the present invention, described conductive layer is electrically connected to active area by conductive pole and conductive plunger, realized the purpose of conductive layer as the interconnect metallization lines of the part-structure complexity of cmos image sensor, simplified the structure of cmos image sensor, increase the aperture opening ratio of the interconnect metallization lines of cmos image sensor, improved the susceptibility of cmos image sensor to light.And the conductive layer of cmos image sensor is difficult for oxidized, the stable performance of cmos image sensor.
Example 4
Different from above-mentioned example 1-3, in example 4 of the present invention, described substrate surface is formed with conducting element or circuit, and described conducting element or circuit can directly be electrically connected to conductive layer by conductive pole, and it specifically forms step and comprises:
Please refer to Figure 18, form the 4th opening 617 that is positioned at described dielectric layer 307, described the 4th opening 617 exposes partially conductive layer 305.
Described the 4th opening 617 is used for follow-up filled conductive material and forms conductive pole.The formation step of described the 4th opening 617 comprises: form the mask layer (not shown) be positioned at described dielectric layer 307 and substrate 300 surfaces, be formed with the 5th opening (not shown) in described mask layer; Along described the 5th described dielectric layer 307 of opening etching, form the 4th opening 617 that is positioned at described dielectric layer 307.
Please refer to Figure 19, form the conductive pole 619 that is positioned at described dielectric layer 307 and conducting element or the circuit 630 that is positioned at described substrate 300 surfaces.
Described conductive pole 619 is used for follow-up electrical connection conducting element or circuit 630.The material of described conductive pole 619 is electric conducting material, such as tungsten, polysilicon etc.; The material of described conducting element or circuit 630 is electric conducting material, and such as tungsten, polysilicon etc. do not repeat them here.
In embodiments of the invention, described conductive pole 619 is identical with the material of described conducting element or circuit 630, is tungsten, and the contact resistance that conductive pole 619 and conductive layer are 305 is little.Described conductive pole 619 and described conducting element or circuit 630 form in same processing step, be specially: filled conductive material of tungsten in described the 5th opening and the 4th opening, form described conductive pole 619 and described conducting element or circuit 630, effectively saved processing step.
Need to prove, in example 4 of the present invention, after forming described conductive pole 619 and described conducting element or circuit 630, also comprise: remove described mask layer, until expose substrate 300 surfaces.
Need to prove, in other embodiments of the invention, can also divide a plurality of steps first to form conductive pole 619, and then form described conducting element or circuit 630, do not repeat them here.
Example 4 passes through directly filled conductive material in the 5th opening of mask layer, form conductive pole 619 and described conducting element or circuit 630 in same step, formation technique is simple, and effectively realized the electrical connection of conductive layer 305 and described conducting element or circuit 630, make the part interconnect metallization lines in the alternative cmos image sensor of conductive layer 305, simplified the structure of cmos image sensor, increase the aperture opening ratio of the interconnect metallization lines of cmos image sensor, improved its susceptibility to light.And the quality of the conductive layer 305 of the cmos image sensor that forms is good, the stable performance of cmos image sensor.
The cmos image sensor that above-mentioned example 4 provides except comprising structure shown in Figure 8, also comprises: be positioned at the conductive pole 619 of described dielectric layer 307, described conductive pole 619 is electrically connected to conductive layer 305; Be positioned at conducting element or the circuit 630 on described substrate 300 surfaces, described conducting element or circuit 630 are electrically connected to conductive layer 305 by conductive pole 619.
The conductive layer 305 of described cmos image sensor only can realization and being electrically connected to of conducting element or circuit 630 by conductive pole 619, and can realize the purpose with conductive layer 305 Substitute For Partial interconnect metallization lines, its structure is further simplified, the aperture opening ratio of interconnect metallization lines increases, and cmos image sensor is high to the susceptibility of light.And the quality of the conductive layer 305 of described cmos image sensor is good, is difficult for oxidation, the stable performance of cmos image sensor.
Figure 20 shows in embodiments of the invention (in conjunction with above-mentioned each example), the cross-sectional view of the cmos image sensor after in interconnection layer, the interconnect metallization lines of part-structure complexity is substituted by conductive layer, as we know from the figure, the cmos image sensor of formation comprises:
Be positioned at a plurality of photosensitive units 701 of substrate 700, above-mentioned a plurality of photosensitive unit 701 belongs to respectively different pixel regions (not shown), in the substrate 700 of shallow trench between photosensitive unit 701, be formed with separator (not shown), conductive layer (not shown) and dielectric layer (not shown) etc. (to please refer to preamble described about the concrete structure of separator, conductive layer and dielectric layer, formation method etc., do not repeat them here) in described shallow trench; Be positioned at the interconnection layer 702 on substrate 700 surfaces and the interconnect metallization lines 703 that is positioned at interconnection layer 702, wherein the most complicated (describing by example so that the structure of the bottom is the most complicated in the present embodiment) part interconnect metallization lines is substituted by conductive layer, and it is simple that the structure of the interconnect metallization lines of this layer becomes; Be positioned at second flatness layer 704 on interconnection layer 702 surfaces, be positioned at the colored filter 705 on the second flatness layer 704 surfaces, be positioned at first flatness layer 706 on colored filter 705 surfaces, and the lenticule 707 that is positioned at the first flatness layer 706 surfaces.
With respect to the cmos image sensor in Fig. 1, part interconnect metallization lines the most complicated in the cmos image sensor of the embodiment of the present invention is substituted by conductive layer, it is more simple that the structure of the interconnect metallization lines of this layer becomes, and the aperture opening ratio of the interconnect metallization lines of cmos image sensor increases.When light is throwed by lenticule 707, when the first flatness layer 706, colored filter 705, the second flatness layer 704 and interconnection layer 702 arrive photosensitive unit 701, suffered obstruction obviously reduces, light more easily arrives photosensitive unit 701, cmos image sensor increases the susceptibility of light, has further improved the performance of cmos image sensor.Need to prove, as for how realizing conductive layer Substitute For Partial interconnect metallization lines, please refer to previous examples, do not repeat them here.
To sum up, when the embodiment of the present invention forms cmos image sensor, after forming separator in the shallow trench between adjacent pixel regions, continuation forms conductive layer in shallow trench, and formation dielectric layer, make the described conductive layer of the common parcel of described dielectric layer and separator, effectively avoid described conductive layer oxidized in the subsequent technique process, make the stable performance of the cmos image sensor of follow-up formation.
Further, form the conductive pole that is electrically connected to described conductive layer in follow-up described dielectric layer again, follow-up conducting element or the circuit that is formed on substrate surface is electrically connected to conductive layer by conductive pole.In embodiments of the invention, described conductive layer can substitute part interconnect metallization lines in the cmos image sensor of formation, increased the aperture opening ratio of the interconnect metallization lines of cmos image sensor, make light more easily see through the photosensitive unit that cmos image sensor arrives each pixel cell zone, being cmos image sensor increases the susceptibility of light, has further improved the performance of cmos image sensor.
Because dielectric layer and separator wrap up conductive layer jointly, described conductive layer is difficult for oxidized, the stable performance of described cmos image sensor, and its structure is simpler.
Further, also comprise: the conductive pole that is positioned at described dielectric layer, described conductive pole is electrically connected to conductive layer, the conducting element or the circuit that are positioned at substrate surface are electrically connected to conductive layer by conductive pole, described conductive layer has substituted the part interconnect metallization lines, the aperture opening ratio of its interconnect metallization lines increases, make light more easily see through the photosensitive unit that cmos image sensor arrives each pixel cell zone, being the cmos image sensing increases the susceptibility of light, has further improved the performance of cmos image sensor.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (22)
1. the formation method of a cmos image sensor, is characterized in that, comprising:
Substrate is provided, and described substrate comprises the first pixel region and adjacent the second pixel region with it;
Form shallow trench in described substrate, described shallow trench is between the first pixel region and the second pixel region;
Form the bottom of the described shallow trench of covering and the separator of sidewall;
After forming described separator, form conductive layer in described shallow trench;
Form the dielectric layer that covers described conductive layer, the described conductive layer of the common parcel of described dielectric layer and separator.
2. the formation method of cmos image sensor as claimed in claim 1, is characterized in that, also comprises: form conductive pole in described dielectric layer, described conductive pole is electrically connected to conductive layer.
3. the formation method of cmos image sensor as claimed in claim 2, is characterized in that, also comprises: form the conducting element or the circuit that are positioned at substrate surface, described conducting element or circuit are electrically connected to conductive layer by conductive pole.
4. the formation method of cmos image sensor as claimed in claim 2, is characterized in that, also comprises: the interlayer dielectric layer that form to cover described substrate, dielectric layer surface; Formation is positioned at the conductive plunger of described interlayer dielectric layer, and described conductive plunger is electrically connected to conductive pole.
5. the formation method of cmos image sensor as claimed in claim 4, is characterized in that, the forming process of described conductive plunger is: the described interlayer dielectric layer of etching forms the 3rd opening, and described the 3rd opening exposes the partially conductive post; The filled conductive material forms conductive plunger in described the 3rd opening.
6. the formation method of cmos image sensor as claimed in claim 5, is characterized in that, described conductive plunger and conductive pole form in same processing step.
7. the formation method of cmos image sensor as claimed in claim 4, it is characterized in that, also comprise: before forming described interlayer dielectric layer, at the substrate surface formation transistor of described the first pixel region or the second pixel region, described conductive plunger is electrically connected to transistorized grid.
8. the formation method of cmos image sensor as claimed in claim 4, is characterized in that, also comprises: after forming conductive plunger, in described interlayer dielectric layer surface formation interconnect metallization lines, described interconnect metallization lines is electrically connected to described conductive plunger.
9. the formation method of cmos image sensor as claimed in claim 4, is characterized in that, also comprises: when being formed with active area in the substrate of described the first pixel region or the second pixel region, described active area is electrically connected to described conductive plunger.
10. the formation method of cmos image sensor as claimed in claim 1, is characterized in that, the formation technique of described separator is oxidation technology or chemical vapor deposition method.
11. the formation method of cmos image sensor as claimed in claim 1 is characterized in that, the material of described separator is silica, silicon nitride or silicon oxynitride.
12. the formation method of cmos image sensor as claimed in claim 1 is characterized in that, the formation technique of described conductive layer is depositing operation.
13. the formation method of cmos image sensor as claimed in claim 1 is characterized in that, the material of described conductive layer is polysilicon, tungsten, copper, titanium or titanium nitride.
14. a cmos image sensor is characterized in that, comprising:
Substrate, described substrate comprise the first pixel region and adjacent the second pixel region with it;
Be positioned at described intrabasement shallow trench, described shallow trench is between the first pixel region and the second pixel region;
Cover the bottom of described shallow trench and the separator of sidewall;
Be positioned at the conductive layer of the insulation surface of described shallow trench;
Cover the dielectric layer of described conductive layer, the described conductive layer of the common parcel of described dielectric layer and separator.
15. cmos image sensor as claimed in claim 14 is characterized in that, also comprises: be positioned at the conductive pole of described dielectric layer, described conductive pole is electrically connected to conductive layer.
16. cmos image sensor as claimed in claim 15 is characterized in that, also comprises: be positioned at conducting element or the circuit of described substrate surface, described conducting element or circuit are electrically connected to conductive layer by conductive pole.
17. cmos image sensor as claimed in claim 15 is characterized in that, also comprises: the interlayer dielectric layer that covers described substrate, dielectric layer surface; Be positioned at the conductive plunger of described interlayer dielectric layer, described conductive plunger is electrically connected to conductive pole.
18. cmos image sensor as claimed in claim 17 is characterized in that, also comprises: be positioned at the transistor of the substrate surface of described the first pixel region or the second pixel region, described conductive plunger is electrically connected to transistorized grid.
19. cmos image sensor as claimed in claim 17 is characterized in that, also comprises: be positioned at the interconnect metallization lines on described interlayer dielectric layer surface, described interconnect metallization lines is electrically connected to described conductive plunger.
20. cmos image sensor as claimed in claim 17 is characterized in that, also comprises: be positioned at the intrabasement active area of described the first pixel region or the second pixel region, described active area is electrically connected to described conductive plunger.
21. cmos image sensor as claimed in claim 14 is characterized in that, the material of described separator is silica, silicon nitride or silicon oxynitride.
22. cmos image sensor as claimed in claim 14 is characterized in that, the material of described conductive layer is polysilicon, tungsten, copper, titanium or titanium nitride.
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Application publication date: 20130612 |