CN107507842A - The method of optimizing CMOS imaging sensor transistor arrangement - Google Patents
The method of optimizing CMOS imaging sensor transistor arrangement Download PDFInfo
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- CN107507842A CN107507842A CN201610413706.XA CN201610413706A CN107507842A CN 107507842 A CN107507842 A CN 107507842A CN 201610413706 A CN201610413706 A CN 201610413706A CN 107507842 A CN107507842 A CN 107507842A
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- 238000003384 imaging method Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 63
- 229920005591 polysilicon Polymers 0.000 claims abstract description 60
- 238000002955 isolation Methods 0.000 claims abstract description 47
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 230000008859 change Effects 0.000 claims abstract description 8
- 230000005540 biological transmission Effects 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 description 18
- 238000009792 diffusion process Methods 0.000 description 8
- 238000007667 floating Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 5
- 238000010276 construction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- 230000003321 amplification Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 208000013469 light sensitivity Diseases 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- OGFXBIXJCWAUCH-UHFFFAOYSA-N meso-secoisolariciresinol Natural products C1=2C=C(O)C(OC)=CC=2CC(CO)C(CO)C1C1=CC=C(O)C(OC)=C1 OGFXBIXJCWAUCH-UHFFFAOYSA-N 0.000 description 1
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- 238000005549 size reduction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
Abstract
The present invention provides a kind of method of optimizing CMOS imaging sensor transistor arrangement, there is provided semiconductor base, defines pixel region, non-pixel region, fleet plough groove isolation structure is formed in pixel region；Bottom, top and the side wall of fleet plough groove isolation structure are formed with dielectric layer；Dielectric layer surface more than 1000 angstrom of the dielectric layer surface of the bottom less than top；Cover polysilicon layer;The polysilicon layer surface that the polysilicon layer surface for being covered in fleet plough groove isolation structure bottom isolates top with being covered in shallow trench has the first height；Photoresist is laid, photoresist is etched using gradual change thang-kng amount mode, the arc photoresist layer of projection is formed in polysilicon layer surface corresponding to fleet plough groove isolation structure；Using arc photoresist layer as mask etching polysilicon layer, the second polysilicon layer is formed in fleet plough groove isolation structure corresponding position, the second polysilicon layer upper surface tends to be smooth less than fleet plough groove isolation structure top.
Description
Technical field
The present invention relates to field of image sensors, more particularly to a kind of method of optimizing CMOS imaging sensor transistor arrangement.
Background technology
Imaging sensor is the semiconductor devices for converting optical signal into electric signal, and imaging sensor has photo-electric conversion element.
Imaging sensor by again can be divided into CMOS（CMOS）Imaging sensor and charge coupling device（CCD）Imaging sensor.The advantages of ccd image sensor is small compared with high and noise to image sensitivity, but ccd image sensor and other devices is integrated relatively difficult, and the power consumption of ccd image sensor is higher.By contrast, cmos image sensor have technique it is simple, easily with other devices are integrated, small volume, in light weight, small power consumption, low cost and other advantages.Therefore, as technology develops, cmos image sensor substitutes ccd image sensor to be applied in each electronic product more and more.Cmos image sensor has been widely used for static digital camera, camera cell phone, DV, medical camera device at present（Such as gastroscope）, automobile-used camera device etc..
The core parts of imaging sensor are pixel cells（Pixel）, pixel cell directly affects the size of imaging sensor, dark current levels, noise level, imaging permeability, color saturation of image and image deflects etc. factor.
All the time, the factor of conflict promotes imaging sensor to advance together：
1. economic factor：One wafer can output image sensor chip it is more, then the cost of image sensor chip is lower, and pixel cell occupies most of area of whole image sensor chip, therefore, in order to save cost, it is desirable to which being sized so as to for pixel cell is smaller, that is to say, that, consider for economic factor, it is desirable to the size reduction of pixel cell in imaging sensor.
2. image quality factors：In order to ensure picture quality, especially for indexs such as guarantee light sensitivity, color saturation and imaging permeabilities, it is necessary to there is the photo-electric conversion element that enough light incides pixel cell（Generally use photodiode）In, and larger pixel cell can have larger photosensitive area to receive light, therefore, larger pixel cell can provide preferable picture quality in principle；In addition, in pixel cell in addition to photo-electric conversion element, also substantial portion of switching device, such as reset transistor, transmission transistor and amplifying device（Such as follow transistor）, these devices equally decide dark current, noise and image deflects etc., consider that the electric property of big device is more preferable in principle, helps to form the image of better quality from picture quality angle；Understand for this, consider for image quality factors, it is desirable to the size increase of pixel cell in imaging sensor.
It obvious can must see how to coordinate above-mentioned contradiction to obtain the selection of optimization, be imaging sensor industry problems faced always.
In conventional images sensor, generally there is the pel array being made up of pixel cell one by one（array）, in terms of domain aspect, multiple pixel cells, which can be stitched together, is combined into a complete pel array, and the shape of pixel cell can be rectangle as needed, square, polygon（Triangle, pentagon, hexagon）Etc..
In conventional images sensor, the structure of pixel cell can be divided into photo-electric conversion element and add 3 transistor arrangements, and photo-electric conversion element adds 4 transistor arrangements or photo-electric conversion element to add 5 transistor arrangements.Photo-electric conversion element adds 3 transistor arrangements to be specifically that photo-electric conversion element directly electrically connects floating diffusion region, and caused light induced electron is stored in floating diffusion region in photo-electric conversion element, in reset transistor（RST）With row gating transistor（SEL）SECO under, light induced electron is passed through into source follower（SF）Conversion output.
Fig. 1 is refer to, shows that photo-electric conversion element adds the diagrammatic cross-section of 4 transistor arrangements.Photo-electric conversion element 115 is usually photodiode（Photo diode, PD）, photo-electric conversion element 115 pass through transfering transistor 114 electrically connect floating diffusion region 113（FD）, lead L3（Lead generally includes connector and interconnection line etc.）Electrically connect the grid of transfering transistor 114.Follow transistor 112 electrically connects floating diffusion region 113, and follow transistor 112 is used to amplify the electric potential signal formed in floating diffusion region 113, and lead L2 electrical connections source follows（Amplification）The grid of transistor 112.One end electric connection of power supply VDD of reset transistor 111, other end electrical connection floating diffusion region 113, is resetted, lead L1 electrically connects the grid of reset transistor 111 with the current potential to floating diffusion region 113.It can be seen that photo-electric conversion element adds 4 transistor arrangements to be that photo-electric conversion element is added on the basis of 3 transistor arrangements, increase transmission transistor 114 between photo-electric conversion element 115 and floating diffusion region 113.Transmission transistor 114 can effectively restrain noise, and photo-electric conversion element adds 4 transistor arrangements to obtain better image quality, be increasingly becoming the leading structure of industry.Furthermore, it is possible to which multiple photo-electric conversion elements share a set of 4 transistor device, to save chip area, this structure is also considered as 4 transistor arrangements.
In CMOS transistor arrangement, the surface of shallow trench isolation structure needed in certain area, which forms surface, tends to uniform polysilicon layer, by powering up pole in being controlled on polysilicon layer, the polysilicon layer that interface tends to be smooth is hardly formed in existing manufacturing process, often leads to the deficiency of control ability.
In summary, the defects of a kind of method of optimizing CMOS imaging sensor transistor arrangement is to overcome conventional images sensor is needed badly.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of method of optimizing CMOS imaging sensor transistor arrangement, positioned at the polysilicon layer surfacing of shallow trench insulation surfaces, to improve the performance of imaging sensor, while control the cost of imaging sensor by technique realization.
Therefore, the present invention provides a kind of method of optimizing CMOS imaging sensor transistor arrangement,
S100：Semiconductor base is provided, defines pixel region, non-pixel region, fleet plough groove isolation structure is formed in pixel region；Bottom, top and the side wall of fleet plough groove isolation structure are formed with dielectric layer；Dielectric layer surface more than 1000 angstrom of the dielectric layer surface of the bottom less than top；
S200：Cover polysilicon layer;The polysilicon layer surface that the polysilicon layer surface for being covered in fleet plough groove isolation structure bottom isolates top with being covered in shallow trench has the first height；
S300:Photoresist is laid, photoresist is etched using gradual change thang-kng amount mode, the arc photoresist layer of projection is formed in polysilicon layer surface corresponding to fleet plough groove isolation structure；
S400：Using arc photoresist layer as mask etching polysilicon layer, the second polysilicon layer is formed in fleet plough groove isolation structure corresponding position, the second polysilicon layer upper surface tends to be smooth less than fleet plough groove isolation structure top.
Preferably, it is described to tend to be smooth and refer in the step S400：The minimum point on the second polysilicon layer surface and the difference in height of peak have the second height, and second height is less than 1/3rd of the first height.
Preferably, in the S400, etching removes the arc photoresist layer outer peripheral areas of part and the polysilicon layer of outer peripheral areas contact.
Preferably, corresponding to photo-generated carrier collecting region of the semiconductor base inside points region as photodiode of fleet plough groove isolation structure bottom；Grid of second polysilicon layer as transmission transistor.
Preferably, the thickness of dielectric layers of the bottom of the fleet plough groove isolation structure is less than or equal to 100 angstroms.
Compared with prior art, technical scheme has advantages below：
1. by laying the photoresist layer on polysilicon layer, formed by the way of gradual change thang-kng amount corresponding to fleet plough groove isolation structure arc photoresist layer, and carry out etches polycrystalline silicon layer, guarantee forms the smooth of polysilicon layer interface.
2. technique is compatible with prior art, area image sensor structure or three-dimensional image sensor construction can be applied to.
Brief description of the drawings
Fig. 1 is the cross-sectional view of pixel cell in conventional images sensor；
Fig. 2 to Fig. 5 is the structural representation of each step of method for the optimizing CMOS imaging sensor transistor arrangement that first embodiment of the invention is provided；
Fig. 6 is the method and step schematic diagram of the optimizing CMOS imaging sensor transistor arrangement provided in the embodiment of the present invention.
Embodiment
In the forming process of existing cmos image sensor transistor, needing to form polysilicon layer in fleet plough groove isolation structure, typically directly laying polysilicon layer and perform etching, the structure to form surfacing is difficult in etching process, influences the control to transistor.
Therefore, the present invention proposes a kind of method of optimizing CMOS imaging sensor transistor arrangement, including：
S100：Semiconductor base is provided, defines pixel region, non-pixel region, fleet plough groove isolation structure is formed in pixel region；Bottom, top and the side wall of fleet plough groove isolation structure are formed with dielectric layer；Dielectric layer surface more than 1000 angstrom of the dielectric layer surface of the bottom less than top；
S200：Cover polysilicon layer;The polysilicon layer surface that the polysilicon layer surface for being covered in fleet plough groove isolation structure bottom isolates top with being covered in shallow trench has the first height；
S300:Photoresist is laid, photoresist is etched using gradual change thang-kng amount mode, the arc photoresist layer of projection is formed in polysilicon layer surface corresponding to fleet plough groove isolation structure；
S400：Using arc photoresist layer as mask etching polysilicon layer, the second polysilicon layer is formed in fleet plough groove isolation structure corresponding position, the second polysilicon layer upper surface tends to be smooth less than fleet plough groove isolation structure top.
Below, with reference to embodiment, the present invention will be described, refer to Fig. 2 to Fig. 5, is the structural representation of each step of method for the optimizing CMOS imaging sensor transistor arrangement that first embodiment of the invention is provided；In Fig. 2, semiconductor base 100 is provided, define pixel region, non-pixel region, the structure for pixel region shown in this example, non-pixel region can be designed specifically as the case may be, pixel region forms fleet plough groove isolation structure 110, and bottom, top and the side wall of fleet plough groove isolation structure 110 are formed with dielectric layer；The thickness of dielectric layer 200 of the bottom of fleet plough groove isolation structure 110 is less than or equal to 100 angstroms.Dielectric layer 220 surface more than 1000 angstrom of the surface of dielectric layer 200 of bottom less than top；The mode for forming fleet plough groove isolation structure 110 is existing process processing procedure, and typically semiconductor base 100 is performed etching using hard mask layer 300.Fig. 3 is refer to, the first polysilicon layer surface that the first polysilicon layer 400 of covering is covered in the bottom of fleet plough groove isolation structure 110 has the first height H1 with being covered in the first polysilicon layer surface that shallow trench isolates top；Photoresist is laid please continue to refer to Fig. 4, photoresist is etched using gradual change thang-kng amount mode, the arc photoresist layer 500 of projection is formed in polysilicon layer surface corresponding to fleet plough groove isolation structure；In Fig. 6, second polysilicon layer 600 is formed in the corresponding position of fleet plough groove isolation structure 110 using patterning process etches polycrystalline silicon layer 400 by arc photoresist layer 300, the arc photoresist layer outer peripheral areas of part and the first polysilicon layer of outer peripheral areas contact are removed in etching process, the upper surface of the second polysilicon layer 600 formed tends to be smooth less than fleet plough groove isolation structure top.Tend to be smooth to refer to：There is the second height H2, the second height H2 to be less than 1/3rd of the first height H1 for the minimum point on the surface of the second polysilicon layer 600 and the difference in height of peak.Corresponding to photo-generated carrier collecting region 700 of the inside points region of semiconductor base 110 as photodiode of fleet plough groove isolation structure bottom；Grid of second polysilicon layer 600 as transmission transistor.
Please continue to refer to Fig. 6, Fig. 6 is the method and step schematic diagram of the optimizing CMOS imaging sensor transistor arrangement provided in the embodiment of the present invention, including：S100：Semiconductor base is provided, defines pixel region, non-pixel region, fleet plough groove isolation structure is formed in pixel region；Bottom, top and the side wall of fleet plough groove isolation structure are formed with dielectric layer；Dielectric layer surface more than 1000 angstrom of the dielectric layer surface of the bottom less than top；
S200：Cover polysilicon layer;The polysilicon layer surface that the polysilicon layer surface for being covered in fleet plough groove isolation structure bottom isolates top with being covered in shallow trench has the first height；
S300:Photoresist is laid, photoresist is etched using gradual change thang-kng amount mode, the arc photoresist layer of projection is formed in polysilicon layer surface corresponding to fleet plough groove isolation structure；
S400：Using arc photoresist layer as mask etching polysilicon layer, the second polysilicon layer is formed in fleet plough groove isolation structure corresponding position, the second polysilicon layer upper surface tends to be smooth less than fleet plough groove isolation structure top.
In the present invention：
1. by laying the photoresist layer on polysilicon layer, formed by the way of gradual change thang-kng amount corresponding to fleet plough groove isolation structure arc photoresist layer, and carry out etches polycrystalline silicon layer, guarantee forms the smooth of polysilicon layer interface.
2. technique is compatible with prior art, area image sensor structure or three-dimensional image sensor construction can be applied to.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore protection scope of the present invention should be defined by claim limited range.
Claims (5)
- A kind of 1. method of optimizing CMOS imaging sensor transistor arrangement, it is characterised in that:S100：Semiconductor base is provided, defines pixel region, non-pixel region, fleet plough groove isolation structure is formed in pixel region；Bottom, top and the side wall of fleet plough groove isolation structure are formed with dielectric layer；Dielectric layer surface more than 1000 angstrom of the dielectric layer surface of the bottom less than top；S200：Cover polysilicon layer;The polysilicon layer surface that the polysilicon layer surface for being covered in fleet plough groove isolation structure bottom isolates top with being covered in shallow trench has the first height；S300:Photoresist is laid, photoresist is etched using gradual change thang-kng amount mode, the arc photoresist layer of projection is formed in polysilicon layer surface corresponding to fleet plough groove isolation structure；S400：Using arc photoresist layer as mask etching polysilicon layer, the second polysilicon layer is formed in fleet plough groove isolation structure corresponding position, the second polysilicon layer upper surface tends to be smooth less than fleet plough groove isolation structure top.
- 2. the method for optimizing CMOS imaging sensor transistor arrangement according to claim 1, it is characterised in that described to tend to be smooth and refer in the step S400：The minimum point on the second polysilicon layer surface and the difference in height of peak have the second height, and second height is less than 1/3rd of the first height.
- 3. the method for optimizing CMOS imaging sensor transistor arrangement according to claim 1, it is characterised in that in the S400, etching removes the arc photoresist layer outer peripheral areas of part and the polysilicon layer of outer peripheral areas contact.
- 4. the method for optimizing CMOS imaging sensor transistor arrangement according to claim 1, it is characterised in that corresponding to photo-generated carrier collecting region of the semiconductor base inside points region as photodiode of fleet plough groove isolation structure bottom；Grid of second polysilicon layer as transmission transistor.
- 5. the method for optimizing CMOS imaging sensor transistor arrangement according to claim 1, it is characterised in that the thickness of dielectric layers of the bottom of the fleet plough groove isolation structure is less than or equal to 100 angstroms.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3680936A1 (en) * | 2019-01-14 | 2020-07-15 | Commissariat à l'Energie Atomique et aux Energies Alternatives | Back-illuminated image sensor |
| US11031433B2 (en) | 2018-02-13 | 2021-06-08 | Stmicroelectronics (Crolles) Sas | Back-side illuminated image sensor |
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|---|---|---|---|---|
| US6177333B1 (en) * | 1999-01-14 | 2001-01-23 | Micron Technology, Inc. | Method for making a trench isolation for semiconductor devices |
| CN103151364A (en) * | 2013-03-15 | 2013-06-12 | 格科微电子（上海）有限公司 | CMOS (Complementary Metal-Oxide-Semiconductor) image sensor and forming method thereof |
| CN104280942A (en) * | 2014-10-31 | 2015-01-14 | 合肥京东方光电科技有限公司 | Mask plate |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6177333B1 (en) * | 1999-01-14 | 2001-01-23 | Micron Technology, Inc. | Method for making a trench isolation for semiconductor devices |
| CN103151364A (en) * | 2013-03-15 | 2013-06-12 | 格科微电子（上海）有限公司 | CMOS (Complementary Metal-Oxide-Semiconductor) image sensor and forming method thereof |
| CN104280942A (en) * | 2014-10-31 | 2015-01-14 | 合肥京东方光电科技有限公司 | Mask plate |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11031433B2 (en) | 2018-02-13 | 2021-06-08 | Stmicroelectronics (Crolles) Sas | Back-side illuminated image sensor |
| US11610933B2 (en) | 2018-02-13 | 2023-03-21 | Stmicroelectronics (Crolles 2) Sas | Back-side illuminated image sensor |
| EP3680936A1 (en) * | 2019-01-14 | 2020-07-15 | Commissariat à l'Energie Atomique et aux Energies Alternatives | Back-illuminated image sensor |
| FR3091787A1 (en) * | 2019-01-14 | 2020-07-17 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Rear-illuminated image sensor |
| US11398521B2 (en) | 2019-01-14 | 2022-07-26 | Stmicroelectronics (Crolles 2) Sas | Back-side illuminated image sensor |
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