KR100612423B1 - Cmos image sensor - Google Patents

Abstract

The CMOS image sensor of the present invention is to reduce the area of the interface between the device isolation film and the semiconductor substrate formed in the pixel portion for sensing the image. As a result, the amount of charge generated in the device isolation layer, which may cause deterioration of image characteristics, may be minimized. In addition, as a means for reducing the area of the interface between the device isolation film and the semiconductor substrate, a method of reducing the depth of the device isolation film is applied, so that the overall structure, such as the arrangement state between the elements, is kept the same.

Image Sensors, CMOS, Photodiodes

Description

CMOS image sensor

1 is an equivalent circuit diagram illustrating a unit pixel of a typical CMOS image sensor pixel portion;

2 is a plan view of a pixel portion of a typical CMOS image sensor;

3 is a cross-sectional view taken along the line AA ′ of FIG. 2,

4 is a cross-sectional view of the CMOS image sensor according to an embodiment of the present invention,

5A through 5D are cross-sectional views illustrating a method of manufacturing the CMOS image sensor of FIG. 4.

♧ description of symbols for the main parts of the drawing

100-semiconductor substrate 200-photodiode

400-Device isolation layer 401, 412-Trench

The present invention relates to an image sensor, and more particularly to a CMOS image sensor that prevents the accumulation of unnecessary charges in the pixel portion.

In general, an image sensor is a device that converts an optical image into an electrical signal using a property of a semiconductor that responds to light. Currently available image sensors are largely classified into a charge coupled device (CCD) and a complementary metal oxide semiconductor (CMOS) method. The CMOS image sensor adopts a method of making photodiodes and MOS transistors by the number of pixels and outputting an optical image as an electrical signal using the same. Compared to the charge coupled device (CCD), the driving method is simpler, and the signal processing circuit can be integrated on a single chip, thereby miniaturizing and lowering power consumption. Particularly, in the late 1990s, the disadvantages inherent in the existing products were overcome by the development of CMOS process technology and the improvement of signal processing algorithms, and recently, the demand is greatly increased as it is widely used in various products such as mobile phones and cameras.

Such CMOS image sensors are classified into 1-transistor structures, 3-transistor structures, and 4-transistor structures according to the number of transistors included in a unit pixel. The 1-transistor structure has a high fill-factor, but has a disadvantage of high noise. Accordingly, as a recent CMOS image sensor, a three-transistor structure or a four-transistor structure is generally used.

The CMOS image sensor is composed of various elements formed on a semiconductor substrate and an element isolation layer electrically separating the elements, which are divided into a pixel unit for sensing an image and a peripheral circuit unit for processing an output signal of the pixel unit. 1 is an equivalent circuit diagram illustrating a unit pixel of a CMOS image sensor pixel unit of a typical four-transistor structure.

Referring to FIG. 1, the pixel unit includes devices such as a photo diode, a transfer transistor Tx, a reset transistor Rx, a selection transistor Sx, and an access transistor Ax. The transfer transistor Tx and the reset transistor Rx are connected in series to the photodiode. An applied voltage Vdd is connected to the drain of the reset transistor Rx. The drain (source of the reset transistor) of the transfer transistor Tx corresponds to a floating diffusion layer (F / D), and the floating diffusion layer F / D is connected to a gate of the selection transistor Sx. The selection transistor Sx and the access transistor Ax are connected in series, and an applied voltage Vdd is connected to the drain of the selection transistor Sx.

The operation process for the unit pixel of the CMOS image sensor configured as described above is as follows.

First, the reset transistor Rx is turned on to apply a constant voltage Vdd to the floating diffusion layer F / D. Subsequently, after turning off the reset transistor Rx, when light is incident on the photodiode from the outside to generate an electron-hole pair (EHP), signal charges are accumulated in the photodiode. Thereafter, when the transfer transistor Tx is turned on, the accumulated signal charges are transferred to the floating diffusion layer F / D to change the potential of the floating diffusion layer F / D, and at the same time, the gate of the selection transistor Sx. The potential is changed. At this time, when the access transistor Ax is turned on by the selection signal Row, data is output to the output terminal Out.

2 is a plan view of a pixel portion of a typical CMOS image sensor.

Referring to FIG. 2, the CMOS image sensor includes a device isolation layer 40 pattern formed on the semiconductor substrate 10 to define a photodiode 20 region and an active region 30. Typically, the photodiode 20 region is formed wide to increase light efficiency, and the active region 30 extends from one side of the photodiode 20 region. The transfer gate 32, the reset gate 34, and the selection gate 36 are sequentially formed on the active region 30 at predetermined intervals. Although not shown, an access gate is formed in the active region 30 by a predetermined distance from the selection gate 36. The transfer gate 32 is adjacent to the photodiode 20 region, and the floating diffusion layer 50 is formed in the active region 30 between the transfer gate 32 and the reset gate 34.

3 is a cross-sectional view of a typical CMOS image sensor pixel portion taken along line AA ′ of FIG. 2.

Referring to FIG. 3, an isolation layer 40 is formed on a semiconductor substrate, and a photodiode 20, a transfer gate 32, a floating diffusion layer 50, and the like are formed in a region defined by the isolation layer 40. . However, the particles constituting the device isolation layer 40 may exist in an incomplete bonding state such as a weak bond or a dangling bond at the interface with the semiconductor substrate 10. Therefore, unnecessary charges are separated and accumulated due to the incomplete coupling. Such charge accumulation phenomenon is inevitably generated in the region where the device isolation film is formed in the peripheral circuit portion other than the pixel portion, but in the peripheral circuit portion, the charge generated in the vicinity of the device isolation film is not significantly affected by its operation characteristics. In that case it is not. That is, since the pixel unit senses an image according to the electron-hole pair generated in the photodiode 20 according to the incident light, the image characteristic is significantly degraded due to unnecessary accumulated charges. Therefore, it is necessary to reduce the unnecessary accumulation of charge in the pixel portion.

The present invention has been proposed to solve the above-described situation, and the technical problem to be achieved by the present invention is to provide a CMOS image sensor that can prevent the accumulation of unnecessary charges in the pixel portion.

The CMOS image sensor of the present invention for achieving the above technical problem comprises a pixel portion formed on a semiconductor substrate for sensing an optical image and a peripheral circuit portion for processing the output signal of the pixel portion; A semiconductor device and an isolation layer for separating the semiconductor devices are formed on the semiconductor substrate; The area of the interface formed by contacting the device isolation film and the semiconductor substrate of the pixel part may be smaller than the area of the interface formed by contacting the device isolation film and the semiconductor substrate of the peripheral circuit part. As described above, if the area of the interface between the device isolation layers in the pixel portion is reduced, the cause of unnecessary charges due to suspension bonding at the boundary between the device isolation layer and the semiconductor substrate may be reduced.

In order to reduce the boundary area between the device isolation film and the semiconductor substrate, only the device isolation film of the pixel portion may be formed to have a shallower depth than the device isolation film of the peripheral circuit portion. However, since the device isolation film serves to separate devices on the semiconductor substrate, there is a certain limit even if the depth thereof is shallow, and it is preferable that the device isolation film be selected in the range of about half the depth of the conventional art.

In the present invention, it is sufficient to reduce the boundary area between the device isolation film and the semiconductor substrate in the pixel portion, and thus there is no particular limitation on the method of forming the device isolation film, and LOCOS (LOCal Oxidation of Silicon) process shallow trench isolation ( Shallow Trench Isolation (STI) may be applied.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be applied and modified in various forms. Rather, the following embodiments are provided only to clarify the technical spirit disclosed by the present invention and furthermore, to sufficiently convey the technical spirit of the present invention to those skilled in the art having an average knowledge in the field to which the present invention belongs. The scope of should not be construed as limited by the embodiments described below. In addition, in the drawings presented in conjunction with the following examples, the size of layers and regions are simplified or somewhat exaggerated to emphasize clarity, and like reference numerals in the drawings indicate like elements.

4 is a cross-sectional view of the CMOS image sensor according to an embodiment of the present invention.

The CMOS image sensor includes a pixel unit for sensing an image and a peripheral circuit unit for processing an output signal of the pixel unit, and FIG. 4 simultaneously illustrates the pixel unit and the peripheral circuit unit to clarify the technical idea of the present invention. It was. 4, detailed configurations of the pixel portion and the peripheral circuit portion which are not directly related to the present invention are omitted.

Referring to FIG. 4, device isolation layers 400 and 410 are formed on a semiconductor substrate 100, and various semiconductor devices 200, 320 and 420 are formed on an area defined by the device isolation layers 400 and 410. . In the pixel portion, the photodiode 200 for generating an electron-hole pair according to the incident light and the photodiode 200 extend to one side of the region where the photodiode 200 is formed so that the transfer gate 320, the floating diffusion layer 500, and the like are sequentially formed. Is formed. Although not shown in FIG. 4, a reset gate, a selection gate, an access gate, and the like are formed in addition to the transfer gate 320, and they generate an electrical output signal for light incident to the photodiode 200. The peripheral circuit unit includes a correlated double sampling (CDS) unit for removing noise from an output signal of the pixel unit, an analog digital converter (ADC) for converting an analog signal into a digital signal, and the like.

As shown in FIG. 4, device isolation layers 400 and 410 are formed in the pixel portion and the peripheral circuit portion to electrically and physically isolate the semiconductor elements 200, 320, and 420. However, some of the particles constituting the device isolation layers 400 and 410 exist in an incompletely bonded state such as a weak bond or a dangling bond at the interface with the semiconductor substrate. Due to the incomplete coupling, the charges are separated and accumulated, which adversely affects the pixel portion. The present invention focuses on the source of generation of the accumulated charges as an interface between the device isolation layer 400 and the semiconductor substrate 100. That is, if the device isolation film 400 is formed such that the area of the interface between the device isolation film 400 and the semiconductor substrate 100 is reduced, the charges that are separated from the device isolation film 400 of the interface will also decrease. The amount of charge stored in the pixel portion can be minimized. In order to reduce the area of the interface between the device isolation layer 400 and the semiconductor substrate 100, various methods such as changing the shape of the device isolation layer 400 to reduce the surface area may be considered. In FIG. 4, the device isolation layer 400 may be considered. The technique of forming a deep depth of) is shown.

As shown in FIG. 4, the depths of the device isolation layers 400 and 410 of the pixel unit and the peripheral circuit unit are different from each other, and the device isolation layer 400 of the pixel unit is shallower than the device isolation layer 410 of the peripheral circuit unit. . As described above, when the depth of the device isolation layer 400 decreases, the area between the semiconductor substrate 100 and the device isolation layer decreases. Here, the depth of the device isolation layer 410 of the peripheral circuit portion is not changed as in the prior art, which is not particularly affected by the accumulation of charges in the peripheral circuit portion, but rather, the elements of the device isolation layer 410 are reduced in depth and physically, respectively. This may be because of the weakening of the electrical and electrical functions. In view of this, even in the pixel portion, the depth of the device isolation film 400 cannot be reduced indefinitely, and the shallower device isolation film 400 should be determined in a range of about half the depth of the peripheral circuit device isolation film 410. do. Since the depth of the peripheral circuit device isolation layer 410 is generally about 4000 GPa, the device isolation film 400 of the pixel unit is preferably about 1500 to 2500 GPa.

Since the present invention only needs to satisfy the condition of reducing the boundary area between the device isolation film and the semiconductor substrate in the pixel portion, there is no particular limitation on the method of forming the device isolation film. Therefore, any process such as LOCOS or shallow trench isolation may be applied. However, since a device isolation layer having a different depth for each region needs to be formed, a step for this may be added.

Hereinafter, a manufacturing process of the CMOS image sensor of the present invention will be described as an example of forming a device isolation layer by applying a shallow trench isolation process.

5A through 5D are cross-sectional views illustrating a method of manufacturing the CMOS image sensor of FIG. 4.

Referring to FIG. 5A, a pad insulating film 110 including an oxide film 111 and a nitride film 112 is sequentially formed on a semiconductor substrate, and then a photoresist is applied on the nitride film 112 to form a photoresist film 120. Form. The oxide layer 111 reduces stress between the semiconductor substrate 100 and the nitride layer 112, and the nitride layer 112 is used as an etching mask for the trench region in which the device isolation layer is to be formed.

Referring to FIG. 5B, after forming a photoresist pattern defining an active region, the pad insulating layer 110 is patterned by an etching method using the photoresist pattern as a mask to form a pad including an oxide layer pattern 111a and a nitride layer pattern 112a. The insulating film pattern 110a is formed. In this case, portions exposed to the pad insulating layer pattern 110a are not all regions in which trenches are to be formed, but are limited to regions other than the pixel portion. Subsequently, the semiconductor substrate 100 is etched according to the pad insulating layer pattern 110a, but the trench 411 is formed only about half the depth of the device isolation layer. For example, if a device isolation film having a depth of 4000 Å is formed, a trench 411 of approximately 1500 to 2500 Å is formed.

Referring to FIG. 5C, after the pad insulating layer pattern 110a is removed, the pad insulating layer pattern 115a including the oxide layer pattern 116a and the nitride layer pattern 117a is formed again using the photosensitive layer. To expose the semiconductor substrate 100 in the entire region where the trench 401 is to be formed. Subsequently, when the semiconductor substrate 100 is etched according to the pad insulating film pattern 115a formed again, trenches 401 and 412 having different depths are formed as shown in FIG. 4C.

Referring to FIG. 5D, trenches 401 and 412 having different depths are filled with an insulating film 450. The insulating layer 450 may include a USG (Undoped Silicate Glass) film, an HDP (High Density Plasma) oxide film, and the like. Among these, the HDP oxide film is a combination of CVD and sputtering etching methods. Since deposition and sputtering etching are performed at the same time for depositing the insulating film 450, when the trenches 401 and 412 having different depths are buried as in the present invention. Useful for preventing voids.

Subsequently, the insulating film 450 filling the trenches 401 and 412 is planarized to the same level as the upper surface of the pad insulating film pattern 115a by using chemical mechanical polishing (CMP) or the like. Removing 115a) forms an isolation layer. Thereafter, when a device such as a photodiode or a transistor is formed in a region defined by the device isolation layer, an image sensor as shown in FIG. 4 is completed.

In addition to the illustrated method, the CMOS image sensor of the present invention may be manufactured by forming trenches of the pixel portion and the peripheral circuit portion using separate masks. Other trenches may be formed.

As described above, according to the CMOS image sensor of the present invention, by reducing the boundary area between the device isolation layer and the semiconductor substrate in the pixel portion, the charge generated at the boundary is reduced, thereby preventing the charge from accumulating and deteriorating image characteristics. can do.

In addition, by applying a method of reducing the depth of the device isolation film, it is possible to simply reduce the boundary area between the device isolation film and the semiconductor substrate without changing the overall structure such as the conventional arrangement state between each device.

Claims (5)

A pixel portion formed on the semiconductor substrate, the pixel portion sensing an optical image, and a peripheral circuit portion processing an output signal of the pixel portion; A semiconductor device and an isolation layer for separating the semiconductor devices are formed on the semiconductor substrate; And the area of the interface formed by contacting the device isolation film and the semiconductor substrate of the pixel portion is smaller than the area of the interface formed by contacting the device isolation film and the semiconductor substrate of the peripheral circuit portion. The CMOS image sensor of claim 1, wherein the device isolation layer of the pixel unit has a shallower depth than that of the peripheral circuit unit. The CMOS image sensor of claim 2, wherein a depth of the device isolation layer of the pixel part is 1500 to 2500 μs. The CMOS image sensor according to any one of claims 1 to 3, wherein the device isolation layer is manufactured by a LOCOS process. The CMOS image sensor according to any one of claims 1 to 3, wherein the device isolation layer is manufactured by a shallow trench isolation process.

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