JPS61133660A - solid state image sensor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a solid-state image sensor in which a plurality of photoelectric conversion elements are two-dimensionally arranged.

Prior Art A normal solid-state image sensor consists of a plurality of photoelectric conversion elements such as photodiodes and phototransistors arranged two-dimensionally on the same chip, and photoelectric signals corresponding to incident light are sequentially extracted from these photoelectric conversion elements. The constituent pressure is used to obtain the image signal. In a solid-state image sensor with such a configuration, a photoelectric conversion element that receives light flows into a photoelectric conversion element that is not receiving light, and a phenomenon occurs as if the photoelectric conversion element that was supposed to receive light had received light. That is, when crosstalk occurs, the resolution decreases, and in severe cases, neutralization pluming and smear appear in the reproduced image. Therefore, in solid-state image sensors, in order to reduce the p-stalk, it is common to provide isolation regions between adjacent photoelectric conversion elements for isolation.

FIG. 1 shows the structure of a conventional solid-state image sensor, in which isolation is formed between photoelectric conversion elements in high impurity concentration regions.

+ That is, by forming a P type surface layer 2 on the surface of an N type substrate 1 and diffusing a needle-shaped separation region 3 from the surface of this P+ type surface layer, P+N 7 layers separated from each other by the separation region are formed. A diode 4°5 is formed. Note that an insulating film 6 is formed on the surfaces of the first surface layer 2 and the isolation region 3. Further, the r-type diffusion isolation region 3 is formed so as to completely surround the photodiode 4.5 in a dotted plane. In a solid-state image sensor having such a configuration, the photocharge 8 generated in the photodiode 5 by the incident light 7 is transferred to the adjacent photodiode 4 by the potential barrier created by the isolation region 3 doped with N-type impurities at a high concentration. I try not to let it flow.

However, in the conventional solid-state image sensor shown in FIG. 1, when forming the separation region 3, impurities are not boiled in the depth direction in order to thermally spread impurities from a predetermined position on the surface of the P+ type surface layer 2. , it will also spread laterally. Therefore, if it is attempted to form the separation region 3 deeply, the separation region occupies a large proportion of the total surface of the chip, resulting in a reduction in resolution. Furthermore, since the light incident on the separation band hardly contributes to the photoelectric conversion effect, there is also the drawback that a sufficiently high sensitivity cannot be obtained. On the other hand, if an attempt is made to reduce the ratio of the isolation region to the entire length of the chip, the isolation region will become shallower, resulting in a drawback that the isolation effect will not be sufficiently exhibited. Furthermore, when using a diffusion separation region with a high impurity concentration, the flow of photocharges is blocked only by a potential barrier, so when strong light is incident and a large amount of photocharge is generated, some of the photocharges are adjacent to each other. Problems such as leakage to photoelectric conversion elements have also arisen. Furthermore, if the separation area is made narrower, the light that is incident diagonally on the solid-state image sensor will pass through the separation area from the photoelectric conversion element and enter the adjacent photoelectric conversion element, resulting in a reduction in resolution. . Such drawbacks cause color mixture, especially in color solid-state image sensor buttons, resulting in a decrease in color reproducibility.

Purpose of the Invention The present invention suppresses leakage of photoelectric charges between photoelectric conversion elements,
The object of the present invention is to provide a solid-state image sensor that can reduce crosstalk, have high resolution, high sensitivity, and improve the degree of integration.

Another object of the present invention is to reduce crosstalk between adjacent photoelectric conversion elements by using an element isolation structure and an externally applied voltage, and to achieve high resolution (at the same time, diagonally incident light can simultaneously reach adjacent photoelectric conversion elements). The object of the present invention is to provide a solid-state image sensor that can particularly prevent color mixing by preventing light from entering.

Summary of the Invention The solid-state image sensor of the present invention is a solid-state image sensor in which a plurality of photoelectric conversion elements are two-dimensionally arranged on the same chip. The device is characterized by having a deep and narrow groove, the walls of the groove being covered with an insulating film, and an isolation region formed by burying a transparent conductor inside the groove. .

Further, in the solid-state image sensor of the present invention, in which a plurality of photoelectric conversion elements are two-dimensionally arranged on the same chip, a deep trench ( The walls of this groove are covered with an insulating film, and a light-shielding film is further coated on this insulating film, and a conductor is buried inside the groove or a light-shielding film is coated. The device is characterized by having a means for externally applying a voltage to the isolation region formed by embedding a light-retaining conductor without causing any damage.

The solid-state image sensor of the present invention includes a MOS type or (1?cD) type image sensor in which the 'h conversion element is a photodiode, and a J-type image sensor in which the photoelectric conversion element is a phototransistor.
FIT or static induction transistor (5tatic I
duction Tranaistor: Hereinafter referred to as SI
It can be constructed with an SIT image sensor using a 3D image sensor (referred to as T).

Embodiment gg2 FIG. 2 is a sectional view showing the structure of an embodiment of the solid-state image sensor of the present invention. In this example, the photoelectric conversion element is PIN
It is constructed using a silicon photodiode (hereinafter referred to as a PIN diode 5). A KN- epitaxial layer 21 is grown on a P+ silicon substrate 20, and a P+ type silicon surface layer 22 is further epitaxially grown to form a PIN diode 23,24.

A groove 25 having a V-shaped cross section and connected to each other is formed around each PIN diode so as to surround it. This groove 25 is formed deep inside the epitaxial layer 21 and has a narrow width. An insulating film 26 made of silicon oxide or nitride is deposited on the walls of this trench 25, and a conductor 27 is buried inside the trench by CVD or sputter deposition.

This conductor 27 is made of tin oxide (5r102) #
Deposit doped polysilicon, indium, tin, acid resistant film 28.

Further, a hole is made in a part of the insulating film 28 where the conductor 27 is embedded, and an electrode 29 is provided.

A pulse voltage is applied to this electrode 29 from the outside.

Although the isolation region is formed with the electric body 27, since the width of the groove 25 is narrow, the effective light receiving area of each PIN/diode 23 and 24 is large, and the light 30 incident on the isolation region also passes through this. Since photocharges 31 can be generated in the epitaxial layer 21 [311,], a solid-state image sensor with extremely high sensitivity can be obtained. That is, in this embodiment, if the separation region also serves as the light receiving region, it becomes busy, so the photoelectric conversion efficiency is improved and high sensitivity is obtained. on the other hand.

Lateral movement is prevented by the voltage applied across the fiK deposited #1 film 2 of the photocharges 31 and grooves 25 generated in the PIN diodes 23 and 24.

Therefore, even if the depth of the groove 25 does not completely reach the substrate 20, the ρ stalk between the PIN diodes 23 and 24 can be sufficiently reduced, and a high-resolution image signal can be obtained.

By embedding the surrounding body 27 around each photoelectric conversion element and applying a bias from the outside, it is possible to obtain a solid-state image sensor that is free from ρ stalk and has high light-receiving sensitivity. Such a structure of the separation region is suitable for fP when applied to a high-sensitivity black-and-white solid-state image sensor in which sensitivity is more important than N image resolution.

FIG. 3 is a sectional view showing another embodiment of the solid-state image sensor of the present invention. In this example, K on the N+ type silicon substrate 40
An N-epitaxial layer 41 is grown and then a P layer is formed.
A + type silicon surface layer 42 is grown epitaxially to form P.
IN diodes 43° and 44 are formed. An insulating film 4 of silicon oxide is applied to the wall of this groove 45 from the surface of the semiconductor chip consisting of the epitaxial layer 541 and the surface layer 42 to the inside.
6 and a light shielding film 47 is applied thereon.

This light shielding film can be formed by depositing a high melting point metal such as M6, Cr, W, or a silicide thereof using a thin film manufacturing method such as a C'VD method or a sputter deposition method. Furthermore, a conductor 48 having good adhesion to a high melting point metal, such as doped polysilicon, is buried inside the trench 45 to form an isolation region.

The P+-shaped part surface layer 42 and the surface layer of the isolation region are coated with an insulating film 49 of silicon oxide. Furthermore.

Similar to the first embodiment described above, a hole is made in a part of the insulating film 49 on the isolation region, and an electrode 50 is provided on the conductor 48 so that a voltage can be applied from the outside.

In the solid-state image sensor of this embodiment, a light shielding film 4 is provided in the separation region.
7, the light '50 obliquely incident on the PIN diode 44 is reflected at the interface between the insulating film 46 and the light shielding film 47, and does not enter the adjacent PIN diode 43. If this light shielding film 47 were not present, the one element 51 would also be incident on the adjacent PIN diode 43 as shown by the broken line, resulting in a decrease in resolution.

Red on the front in a color solid-state image sensor.

In devices with green and blue filters, the signal separation between adjacent photoelectric conversion elements must be performed more strictly than in black-and-white solid-state image sensors; otherwise, red.

a. Color mixture between blue colors will occur. Severe color mixing significantly deteriorates image color reproducibility, which is a fatal drawback for color solid-state image sensors. In the implementation shown in FIG. 3, it is possible to effectively prevent photocharges from circulating between adjacent photoelectric conversion elements by applying a voltage to the isolation region from the electrode 50 via the insulating film 49. In addition, the provision of a light-shielding film prevents obliquely incident light from simultaneously entering adjacent photoelectric conversion elements (
Therefore, the above-mentioned color mixture can be suppressed and a clear color image can be obtained. In addition, the third
In the illustrated embodiment, the conductor 48 may be transparent or opaque. In this example, a BIT image sensor is used as the photoelectric conversion element. This SIT has a vertical structure, the drain region is made of an N+ type substrate 60, and the source region is an N+ type region formed on the surface of an N- type epitaxial layer 61 which is deposited on the substrate 60 and constitutes a channel region. 62
It consists of

On the surface of the epitaxial layer 61, a wafer source region 62 is formed.
A P+ type signal storage gate region 63 is formed around the region 5 . A groove 64 having a V-shaped cross section is formed so as to surround each signal storage gate region. This groove 64 is formed deep inside the epitaxial layer 61 and has a narrow width. An insulating film 65 made of silicon oxide or nitride is coated on the wall of the groove 64, and the inner groove of the groove is coated with a conductor 6.
6 is buried by CVD or sputter deposition.

As the conductor 66, a transparent or opaque conductive material such as tin oxide (BnO2)*doped polysilicon, indium tin, or oxide is used.

An insulating film 6 is formed on the surface of the P+ type surface layer 63 and the conductor 66.
cover with f. Furthermore, a hole is made in the insulating film 67 on the conductor 66, an electrode 68A is provided, and a terminal 688 of the electrode 68A is provided.
5 so that a pulse voltage as shown in the figure can be applied.

Note that an electrode 70 is provided on the signal storage gate region 63 with an insulating film 69 interposed therebetween, and a so-called MIEI structure gate electrode is formed which radiates from the electrode/insulating film/gate region. . The impurity concentration of the n-type epitaxial layer 61 constituting the channel region is selected to be so low that the channel region is depleted even with the bias applied to the gate electrode or Ov, causing a high to 1 potential barrier and pinch-off. ing.

The operating principle of such 5ITI will be explained below.

Bias is not applied between drain and source -12
= When light enters the channel region 61 and the dart region 63 in a negative state, 5 of the electron-hole pairs generated here are
In other words, the holes are accumulated in the dirt region 63, and the electrons pass through the drain region 60 and leave the ground current.

The holes accumulated in the gate region 63 in response to optical input are
When the potential of the gate region 63 is raised and a forward voltage is applied to the channel region, a current flows between the drain and source according to the significant amount of holes in the gate region 63, and an output that is amplified with respect to optical input is obtained. It will be done.

Note that the photoelectrically converted current from the source region of each of the N pixel cells constituting the ST image sensor of this embodiment is taken out from the output terminal 73 via the readout line 72. Note that 74 is a load resistor connected in parallel to the readout line 72.

In this embodiment, the signal accumulation gate region 63 of the adjacent pixel cell
A P+N''-P+ structure shown in the schematic symbol is formed through the epitaxial layer 61 with a distance KN between adjacent signal accumulation dirt regions. When the distance of 8 I T (ParasitlcLateral
SIT) 90 may be considered. When this horizontal SIT operates, it may have a detrimental effect on the signal readout operation, such as crosstalk between pixel cells. Therefore, the inventors of the present invention have considered the width of the groove 640 for insulating and separating the pixel cells and the depth of the groove in the epitaxial layer 61 in the direction of the substrate 60.

FIG. 5 is a diagram schematically showing a circuit configuration for measuring leakage current between signal accumulation dirt regions (P+) of adjacent pixel cells when the present invention is applied to an SIT image sensor. Incidentally, members having the same functions as those in the above-mentioned embodiment l1g3 (see FIG. 4) are designated by the same reference numerals, and their explanations will be omitted. Further, FIG. 6 is a diagram showing the relationship between the voltage between the signal storage gate regions and the leakage current between the signal storage gate regions obtained by the measurement.

In FIG. 5, the grooves 64 for insulating and separating the pixel cells are narrowed with various configurations as described in 5 above, and an ammeter 80 and a variable A voltage source 81 (Vgg) is connected to measure the leakage current between the signal storage gate regions of adjacent pixel cells. A variable voltage source 82 (Vd) is connected to the N+ type substrate 60 forming the alternating voltage, drain region, and a predetermined drain voltage is applied thereto.

5 and 6, in this embodiment, the distance between the signal accumulation dirt region formed in one unit pixel cell and the adjacent gate region is the shortest, and the groove width is 1 μm, and the distance between the signal accumulation dirt region formed in one unit pixel cell and the adjacent gate region is the shortest. The measurement was performed on an insulation isolation region (groove 64) with a depth of 0.5 μm. Leakage current between the signal storage gate regions 63 and 63 of adjacent pixel cells across the groove 64! As a result of measuring g1-d at the Gl terminal, the drain voltage Vd≧2(V) Teha%Igl)iVgg-0 to -2
It has been found that in the range of 0 (V), lXl0 (constant and adjacent signal accumulation P-) regions are sufficiently separated.

- 10,000, when the drain voltage vd=t and 5 (V) or less, a Gutvintio7 voltage Vp exists, and when Vgsr>Vp, the gate current Igi increases exponentially.

What is clear from this example is that the distance between the signal storage gate regions, that is, the width of the region (groove 64) forming insulation isolation is short (if the gate current Igx is Igx = Igt
-d + Igt -g21g*-d; Gate G1-Drain PIN diode reverse leakage current Igx-g*: Represented by the current flowing through the parasitic horizontal BIT between G1-G2, and during SIT image sensor operation Igt
-d)> Igs -g*, it is possible to sufficiently pinch off the parasitic horizontal 8IT. In the signal readout of this embodiment, since a method of grounding via the load resistor 74 is adopted, the parasitic horizontal SI
T is enough to pinch off.

However, when using the drain side with grounding,
Since the substrate 60 is grounded, a bias cannot be applied and the parasitic horizontal SI'l' 90 cannot be pinched off. In this case, the terminal 68BVC and the horizontal type 5I
It is sufficient to apply a voltage polarity (in this example, a positive voltage polarity) pulse such that T90 turns off via 1. By changing the pulse height of this applied pulse, leakage between the gates similar to that shown in Fig. 6 can be avoided. Current can be easily controlled.

As a result, in the embodiment shown in FIG. 4, a voltage is applied to the groove 64, the insulating film 65 attached to the wall thereof, the conductor 66 embedded in the groove 64, and the conductor 66. A separation region is formed with the electrode 68A, but since the width of the groove 64 is narrow, S
When the effective light-receiving area of each pixel cell of an IT image sensor increases, the light incident on the cointegration region also passes through this and reaches the epitaxial layer 611C, and an effective Wako charge can be generated, resulting in an extremely sensitive solid-state image sensor. can get. That is, in this embodiment, the separation region also serves as the light receiving region, so that the photoelectric conversion efficiency is improved and high sensitivity can be obtained.

On the other hand, the photocharges generated in each pixel of the BIT image sensor can also be prevented from moving in the lateral direction by applying a voltage to the isolation region through the insulation #65 attached to the wall of the groove 64.

Therefore, it is possible to sufficiently reduce the p-stoke between adjacent signal accumulation dirt regions, and it is possible to obtain an image signal with a high degree of resolution. In this way, a deep and narrow groove 64 is formed around each pixel cell so as to surround it, the walls of this groove are covered with an insulating film 65, and a conductor 66 is buried inside the groove and wound. By forming a separate region and applying a voltage thereto, it is possible to obtain a solid-state image sensor that is free from rip-talk and has high light-receiving sensitivity. Such a configuration of the separation region is particularly suitable for application to a high-sensitivity black-and-white solid-state image sensor in which sensitivity is more important than resolution.

In this *m example, the BIT image sensor is
Although the embodiment has been described, the present invention is not limited thereto (it goes without saying that the second embodiment (see FIG. 3) can also be applied.

The invention is limited only to the embodiments described above. thing! Many modifications are possible. For example, in the above embodiment, a silicon semiconductor chip was used as the chip, but a chip made of a compound semiconductor or an amorphous material may also be used. However, it is not necessary to use phototransistors or to provide individual phototransistors.Also, in the above embodiment, the cross-sectional shape of the groove is V-shaped, but it is possible to use a deep and narrow groove. Of course, other shapes such as a U-shape are also possible.

Effects of the Invention In the solid-state image sensor of the present invention described above, a 5tC deep and narrow groove is formed to surround adjacent photoelectric conversion elements, and the walls of this groove are covered with an insulating film, and a transparent conductive film is formed inside the groove. By pushing the body into a separation region and applying a bias voltage to the separation region, there is no leakage of photocharges of =19- between adjacent photoelectric conversion elements, and it is possible to suppress rip-stalk. It is possible to obtain a clear image field without any blurring or smear, and because the width of the separation region is narrow, the pixel size can be reduced, and a solid-state image sensor with high density and high resolution can be obtained. Since the photoelectric conversion elements can be separated by a narrow separation region, it is possible to form a deep epitaxial layer.Also, since the conductor is transparent, the separation region can also be used as a light-receiving region. , the aperture ratio is increased, and a highly sensitive solid-state image sensor can be obtained.

Furthermore, if the separation area is made to have continuous light, it is possible to prevent light from leaking between the image areas, so when applied to a color solid-state image sensor, red and green can be used.

It is possible to obtain various effects such as obtaining a clear color image with less mixing of blue colors.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the configuration of a conventional solid-state image sensor, and FIG. 2 is a sectional view showing an m modification of an embodiment of the solid-state image sensor of the present invention. @3 Figure is a sectional view showing the configuration of another embodiment of the solid-state image sensor of the present invention. FIG. 4 is a sectional view showing the configuration of still another embodiment of the solid-state image sensor of the present invention, and FIG. 5 is a schematic diagram showing the circuit configuration for measuring leakage current in the solid-state image sensor of the present invention. 20.40.60--Substrate 22.42--Surface layer 2
3.24.43.44--PIN diode 25.4
5.64...Groove 26.46.65--Insulating film 27.48.66-Conductor 47--Light shielding film 28.4
9.67 - Insulating film 30.51 - Incident light 31 - Original charge Figure 5 Figure 6 Voltage between signal storage gate regions Vgg (V) Procedural correction (Written spontaneously)

Claims (1)

[Scope of Claims] 1. In a solid-state image sensor in which a plurality of photoelectric conversion elements are two-dimensionally arranged on the same chip, a deep trench is dug from the surface to the inside so as to surround each photoelectric conversion element. A solid-state image sensor having a narrow groove, the walls of the groove being covered with an insulating film, and an isolation region formed by burying a transparent conductor inside the groove. 2. In a solid-state image sensor in which a plurality of photoelectric conversion elements are two-dimensionally arranged on the same chip, a deep and narrow groove is formed around each photoelectric conversion element and excavated from the surface to the inside so as to surround each photoelectric conversion element. The walls of this groove are covered with an insulating film, and then a light-shielding film is coated on top of this insulating film, and a conductor is buried inside the groove, or a light-shielding conductor is buried without covering with a light-shielding film. A solid-state image sensor characterized by having a separated region formed therein. 3. The solid-state image sensor according to claim 1 or 2, further comprising means for externally applying a bias voltage to the conductor embedded in the groove.