CN103137659A - Memory element and manufacturing method thereof - Google Patents
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- CN103137659A CN103137659A CN2011103910058A CN201110391005A CN103137659A CN 103137659 A CN103137659 A CN 103137659A CN 2011103910058 A CN2011103910058 A CN 2011103910058A CN 201110391005 A CN201110391005 A CN 201110391005A CN 103137659 A CN103137659 A CN 103137659A
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Abstract
The invention relates to a memory element and a manufacturing method of the memory element. The memory element comprises grid electrodes, grid dielectric layers and two charge storage layers. The grid electrodes are arranged on a substrate. Each grid dielectric layer is arranged between each grid electrode and the substrate. The thickness of each grid dielectric layer is less than that of each grid electrode. Gaps are formed in two sides of each grid dielectric layer, below each grid electrode and above the substrate. Each charge storage layer comprises a main body portion, a first extension portion and a second extension portion. Each main body portion is arranged in each gap. Each first extension portion is connected with each main body portion and protrudes out of the side wall of each grid electrode. Each second extension portion is connected with each corresponding first extension portion and upward extends to the side wall of each grid electrode. An edge of each first extension portion protrudes out of the side wall of each corresponding second extension portion. The memory element and the manufacturing method of the memory element has the advantages of being capable of providing the located charge storage regions, enabling charge to be stored in a fully locating mode, reducing second bit effect and behavior of interference of programming, and reducing short channel effect. The invention further provides the manufacturing method of the memory element.
Description
Technical field
The present invention relates to a kind of integrated circuit and manufacture method thereof, particularly relate to a kind of memory cell and manufacture method thereof.
Background technology
Memory body is the semiconductor element that stores information or data.Along with the function of computer microprocessor is more and more strong, the program that software is carried out also increases with operation thereupon.Therefore, the demand for high capacity memory also increases gradually.
In various memory body products, non-volatility memory allow repeatedly program data, read and erase operation for use, even can also preserve the data that is stored in wherein after the power interruptions of memory body.Due to these advantages, non-volatility memory has become widely used memory body in PC and electronic equipment.
The electrically programmable of the application charge storing structure of knowing (charge storage structure) and (electrically programmable and erasable) the non-volatility memory technology of erasing, as electronics erasable programmable read-only memory (EEPROM) and fast flash memory bank (flash memory body), be used in various modernizations application.Fast flash memory bank is designed to have the form of memory cell, and it can be programmed and read independently.General fast flash memory bank memory cell with charge storage in floating grid.Another kind of fast flash memory bank is to use non-conductive material to form charge-trapping structure (charge-trappingstructure), and silicon nitride for example is to replace the conductor material of floating grid.When the charge-trapping memory cell was programmed, electric charge was captured and can move through idioelectric charge-trapping structure.When not continuing the supply power supply, electric charge can remain in electric charge capture layer always, keeps its data state, until memory cell is erased.The charge-trapping memory cell can be become two end memory cells (two-sidedcell) by behaviour.That is to say, because electric charge can not move through the non-conductor electric charge capture layer, so electric charge can be positioned at different charge-trapping places.In other words, in the fast-flash memory body member of charge-trapping structural type, can store an information more than bit in each memory cell.
Arbitrary memory cell can be programmed, and stores two bits that separate fully (concentrating respectively the mode of close source area and drain region with electric charge) in the charge-trapping structure.The programming exploitable channel hot electron of memory cell injects, and it produces hot electron at channel region.Hot electron obtains energy and is captured in the charge-trapping structure.The bias voltage that source terminal and drain electrode end are applied exchanges, can be with charge-trapping to arbitrary part of charge-trapping structure (nearly source area, nearly drain region or both).
Usually, the memory cell with charge-trapping structure can store four kinds of different bit combinations (00,01,10 and 11), and each has corresponding start voltage.At during read operations, the electric current that flows through memory cell is different because of the start voltage of memory cell.Usually, this electric current can have four different values, and wherein each is corresponding to different start voltages.Therefore, by detecting this electric current, can judge the bit combination that is stored in memory cell.
All effectively ranges of charge or start voltage scope can classify as memory body operation window (memory operation window).In other words, the memory body operation window defines by the difference between program bit accurate (level) and erased bit standard.Separate because the good bit between the various states of memory cell action need is accurate, therefore need large memory body operation window.Yet the usefulness of two bit memory cells reduces along with so-called " second bit effect " usually.Under the second bit effect, the electric charge of localization affects each other in the charge-trapping structure.For example, during reverse read, apply to read and be biased into drain electrode end and the electric charge (i.e. the first bit) that is stored near source area detected.Yet the bit (being second bit) near the drain region produces the potential barrier that reads near the first bit of source area afterwards.This energy barrier can overcome by applying suitable bias voltage, uses the drain-induced energy barrier to reduce the effect that (DIBL) effect suppresses the second bit of close drain region, and allows to detect the storing state of the first bit.Yet, when being programmed paramount start voltage state near the second bit of drain region and near the first bit of source area during at programming state not, second bit has improved in fact energy barrier.Therefore, along with the start voltage about second bit increases, the bias voltage that reads of the first bit has not enough overcome the potential barrier that second bit produces.Therefore, due to the start voltage increase of second bit, the start voltage of the first bit improves, thereby has reduced the memory body operation window.The second bit effect has reduced the operation window of two bit memory bodys.
This shows, above-mentioned existing memory cell and manufacture method thereof obviously still have inconvenience and defective, and demand urgently further being improved in product structure, manufacture method and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but have no for a long time applicable design is completed by development always, and common product and method do not have appropriate structure and method to address the above problem, and this is obviously the problem that the anxious wish of relevant dealer solves.Therefore how to found a kind of new memory cell and manufacture method thereof, to suppress the second bit effect in memory cell, belong in fact one of current important research and development problem, also becoming the current industry utmost point needs improved target.
Summary of the invention
The object of the invention is to, overcome the defective that existing memory cell exists, and provide a kind of new memory cell, technical problem to be solved is to make it that charge storage region of location can be provided, so that electric charge localization storage fully reduces the second bit effect, reduce the behavior that programming is disturbed, and can reduce short-channel effect, be very suitable for practicality.
Another object of the present invention is to, overcome the defective of the manufacture method existence of existing memory cell, and provide a kind of manufacture method of new memory cell, technical problem to be solved is to make it make the memory cell of manufacturing that the charge storage region of location can be provided by simple technique, so that electric charge localization storage fully obtains better second bit, reduce the behavior that programming is disturbed, and can reduce short-channel effect, thereby more be suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of memory cell according to the present invention proposes comprises grid, gate dielectric layer and two electric charge storage layers.Grid is positioned in substrate.Gate dielectric layer is between above-mentioned grid and substrate.Has a space below above-mentioned gate dielectric layer both sides, grid and above substrate.Above-mentioned each electric charge storage layer comprises main part, one first extension and one second extension.Each main body section is in above-mentioned each space.Each first extension and aforementioned body section are connected and protrude from the sidewall of above-mentioned grid.Each second extension is connected with corresponding this first extension, and extends upwardly to the sidewall of this grid, and wherein respectively the fringe region of this first extension protrudes from the corresponding respectively sidewall of this second extension.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid memory cell, the material of wherein said main part, the first extension and the second extension is identical.
Aforesaid memory cell also comprises two doped regions, is arranged in the above-mentioned substrate of grid both sides, and wherein the first extension of above-mentioned each electric charge storage layer and the second extending part are in corresponding doped region top.
Aforesaid memory cell also comprises two linings and two clearance walls.Above-mentioned two linings lay respectively between the second extension of grid and each electric charge storage layer.Above-mentioned two clearance walls are positioned at above above-mentioned the first extension, and above-mentioned the second extension is sandwiched between corresponding lining and clearance wall.
Aforesaid memory cell, the ratio of the length of the length of wherein said main part and the first extension is 2: 1 to 5: 1.
The object of the invention to solve the technical problems also realizes by the following technical solutions.A kind of memory cell according to the present invention proposes comprises grid, gate dielectric layer, two electric charge storage layers and two linings.Grid is positioned in substrate.Gate dielectric layer is between grid and substrate.Has a space below above-mentioned gate dielectric layer both sides, grid and above substrate.Above-mentioned each electric charge storage layer comprises main part and extension.Each main body section is in above-mentioned space.Each extension and aforementioned body section are connected and protrude from the sidewall of grid.Each lining is positioned at the sidewall of grid, and the fringe region of the extension of each electric charge storage layer protrudes from the sidewall of lining.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid memory cell, the material of wherein said main part and extension is identical.
Aforesaid memory cell also comprises two doped regions, is arranged in the above-mentioned substrate of grid both sides, and wherein the above-mentioned extension of above-mentioned each electric charge storage layer extends to the top of corresponding above-mentioned doped region.
Aforesaid memory cell, the ratio of the length of wherein said main part and the length of extension is 2: 1 to 5: 1.
The object of the invention to solve the technical problems realizes by the following technical solutions again.A kind of memory cell according to the present invention proposes comprises grid, gate dielectric layer, two electric charge storage layers and two doped regions.Grid is positioned in substrate.Gate dielectric layer is between grid and substrate.Has a space below above-mentioned gate dielectric layer both sides, grid and above substrate.Above-mentioned each electric charge storage layer comprises main part and extension.Each main body section is in above-mentioned space.Each extension and aforementioned body section are connected and protrude from the sidewall of above-mentioned grid.Each doped region is arranged in the substrate of grid both sides, and the extension of each electric charge storage layer extends to corresponding doped region top.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid memory cell, the material of wherein said main part and extension is identical.
Aforesaid memory cell, the ratio of the length of wherein said main part and the length of extension is 2: 1 to 5: 1.
The object of the invention to solve the technical problems realizes again by the following technical solutions.The manufacture method of a kind of memory cell that proposes according to the present invention comprises: forming gate dielectric layer in substrate and be positioned at grid on gate dielectric layer, wherein below gate dielectric layer both sides, grid and form a space above substrate.Form afterwards two electric charge storage layers, each electric charge storage layer comprises main part and the first extension, and wherein each main body section is in above-mentioned space, and each first extension and each main part are connected and protrude from the sidewall of grid.Form two doped regions in the substrate of grid both sides, the first extension of each electric charge storage layer extends to above corresponding doped region.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid memory cell, wherein each electric charge storage layer more comprises the second extension, each second extension is connected with above-mentioned the first extension, and extends upwardly to the sidewall of grid, and wherein the fringe region of the first extension protrudes from the sidewall of the second corresponding extension.
The manufacture method of aforesaid memory cell, wherein above-mentioned first extension of each electric charge storage layer and above-mentioned the second extending part are in corresponding above-mentioned doped region top.
The manufacture method of aforesaid memory cell, wherein before forming above-mentioned electric charge storage layer, also comprise and form a lining material bed of material, cover the surface of above-mentioned substrate, the sidewall of gate dielectric layer, bottom, sidewall and the upper surface of grid, the fringe region of the first extension of above-mentioned each electric charge storage layer protrudes from the lining material bed of material that is positioned at gate lateral wall.
The manufacture method of aforesaid memory cell, the step of wherein said those electric charge storage layers of formation comprises: form the charge storage material layer and cover the above-mentioned lining material bed of material and fill up above-mentioned space, then form the spacer material layer and cover above-mentioned charge storage material layer.Afterwards, anisotropic etching removes the above-mentioned lining material bed of material, charge storage material layer and spacer material layer, to expose the surface of above-mentioned grid and substrate, stays above-mentioned lining, electric charge storage layer and two clearance walls.
The manufacture method of aforesaid memory cell, the sidewall that also is included in above-mentioned grid forms a lining, and wherein above-mentioned first extension of above-mentioned each electric charge storage layer protrudes from the sidewall of above-mentioned lining.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, memory cell of the present invention and manufacture method thereof have following advantages and beneficial effect at least:
Memory cell of the present invention can provide the charge storage region of location, so that electric charge localization storage fully reduces the second bit effect, reduces the behavior that programming is disturbed, and can reduce short-channel effect.
The manufacture method of memory cell of the present invention can make the memory cell of manufacturing that the charge storage region of location can be provided by simple technique, so that electric charge localization storage fully, obtain better second bit, reduce the behavior that programming is disturbed, and can reduce short-channel effect.
In sum, the invention relates to that this memory cell of a kind of memory cell and manufacture method thereof comprises grid, gate dielectric layer and two electric charge storage layers.Grid is positioned in substrate.Gate dielectric layer is between grid and substrate.The width of gate dielectric layer is less than grid, and below gate dielectric layer both sides, grid and form a space above substrate.Each electric charge storage layer comprises main part, the first extension and the second extension.Each main body section is in above-mentioned each space.Each first extension and each main part are connected and protrude from the sidewall of each grid.Each second extension is connected with corresponding each first extension, and extends upwardly to gate lateral wall, and wherein the fringe region of the first extension protrudes from the sidewall of corresponding the second extension.The present invention can provide the charge storage region of location by this, makes electric charge localization storage fully, reduces the second bit effect, reduces programming interference behavior, and can reduce short-channel effect.The present invention also provides a kind of manufacture method of memory cell.The present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above and other purpose of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and the cooperation accompanying drawing, be described in detail as follows.
Description of drawings
Fig. 1 to Fig. 7 is the generalized section of the manufacture method of a kind of memory cell of illustrating according to the embodiment of the present invention.
Fig. 8 be three kinds of different memory cells when programming program speed and the graph of a relation of drain bias.
Fig. 9 is the generalized section that has known a kind of memory cell now.
Figure 10 is the generalized section that has known another kind of memory cell now.
10: substrate 12: gate dielectric layer
14: gate conductor layer 14a: grid
16: the curtain layer of hard hood 18 of patterning: the cover curtain layer of patterning
20: groove 20a: space
22: lining material bed of material 22a: first/tunneling dielectric layer
22b: second portion/top dielectric layer 22c: third part/lining
24 ': charge storage material layer 24: electric charge storage layer
24a: main part 24b: the first extension
24c: the second extension 26: spacer material layer
26a: clearance wall 28,30: doped region
32: dielectric layer 34: the character line
L1, L2: length 100,200,300: curve
Embodiment
Reach for further setting forth the present invention technological means and the effect that predetermined goal of the invention is taked, below in conjunction with accompanying drawing and preferred embodiment, memory cell and its embodiment of manufacture method, structure, method, step, feature and effect thereof to foundation the present invention proposes are described in detail as follows.
Relevant aforementioned and other technology contents of the present invention, Characteristic can be known to present in the following detailed description that coordinates with reference to graphic preferred embodiment.Explanation by embodiment, should be to reach technological means and the effect that predetermined purpose takes to obtain one more deeply and concrete understanding to the present invention, yet appended graphic only be to provide with reference to the use of explanation, the present invention is limited.
Fig. 1 to Fig. 7 is the generalized section of the manufacture method of a kind of memory cell of illustrating according to the embodiment of the present invention.
See also shown in Figure 1ly, the manufacture method of memory cell of the present invention is to form gate dielectric layer 12 in substrate 10, then, forms gate conductor layer 14 on gate dielectric layer 12.The material of substrate 10 is for example semiconductor, is for example silicon, and silicon (SOI) is perhaps arranged on insulating barrier.The material of substrate 10 can be also other compound semiconductor.The material of gate dielectric layer 12 is for example silica, or other are fit to make the material of gate dielectric layer.The formation method of gate dielectric layer 12 is for example thermal oxidation method, or chemical vapour deposition technique, or other suitable methods.The material of gate conductor layer 14 is for example doped polycrystalline silicon.The formation method of gate conductor layer 14 is for example after utilizing chemical vapour deposition technique to form the undoped polycrystalline silicon layer, carries out the implanted ions step to form.The formation method of gate conductor layer 14 can be also to utilize chemical vapour deposition technique form polysilicon layer and adulterating when participating in the cintest.Afterwards, form the curtain layer of hard hood 16 of patterning and the cover curtain layer 18 of patterning on gate conductor layer 14.The material of the curtain layer of hard hood 16 of patterning is for example APF, and the method for formation is for example chemical vapour deposition technique.The material of the cover curtain layer 18 of patterning is for example photoresistance.The pattern of cover curtain layer 18 can form via exposure and the mode of developing.The pattern of curtain layer of hard hood 16 can form by the pattern downwards transfer of etch process with cover curtain layer 18.
Afterwards, see also shown in Figure 2, take cover curtain layer 18 with curtain layer of hard hood 16 for the cover curtain, substrate 10 is etch stop layer, carries out etch process, so that gate conductor layer 14 is patterned as grid 14a, and continuation patterned gate dielectric layer 12.The etch process that adopts is for example anisotropic etching technique.Anisotropic etch process is for example plasma etch process.Afterwards, cover curtain layer 18 and the curtain layer of hard hood 16 with patterning removes.
, see also shown in Figure 3, gate dielectric layer 12 is carried out isotropic etching technique thereafter, to remove the gate dielectric layer 12 of part, namely produce undercutting below grid 14a, and form groove 20, this groove 20 is as positioning storage space (local storage space).
Afterwards, see also shown in Figure 4ly, form the lining material bed of material 22, the sidewall of the upper surface of cover gate 14a, sidewall and bottom, gate dielectric layer 12 and the surface of substrate 10.In one embodiment, the surface of the sidewall of upper surface, sidewall and the bottom of the lining material bed of material 22 conformal cover gate 14a, gate dielectric layer 12 and substrate 10.The lining material bed of material 22 fills among groove shown in Figure 3 20, but does not fill up groove 20, and leaves space 20a (Fig. 4).The material of the lining material bed of material 22 is for example silica, and the method for formation is for example thermal oxidation method, steam produces (ISSG) oxidizing process, chemical vapour deposition technique (CVD), atomic layer deposition method or furnace oxidation method when participating in the cintest.
Afterwards, see also shown in Figure 5ly, form charge storage material layer 24 ', the surface of the lining material bed of material 22 of the upper surface of cover gate 14a, sidewall and substrate 10 tops and filling among the 20a of space.The material of charge storage material layer 24 ' is for example silicon nitride or doped polycrystalline silicon.The formation method of silicon nitride is for example boiler tube sedimentation, chemical vapour deposition technique or atomic layer deposition method.The formation method of doped polycrystalline silicon is for example to utilize chemical vapour deposition technique form polysilicon layer and adulterating when participating in the cintest.
Afterwards, at the upper spacer material layer 26 that forms of charge storage material layer 24 ', the charge storage material layer 24 ' of the upper surface of cover gate 14a, sidewall and substrate 10 tops.In one embodiment, the charge storage material layer 24 ' of the upper surface of the conformal grid 14a of spacer material layer 26, sidewall and substrate 10 tops.The material of spacer material layer 26 is for example silica, and the method for formation is for example furnace oxidation method, chemical vapour deposition technique or high-temperature thermal oxidation method (HTO).
Thereafter, see also shown in Figure 6ly, anisotropic etching spacer material layer 26, charge storage material layer 24 ' and the lining material bed of material 22 expose the surface of grid 14a and substrate 10.The charge storage material layer 24 ' that stays is as electric charge storage layer 24, and it comprises main part 24a, the first extension 24b and the second extension 24c.Each main part 24a is positioned among the 20a of space.The first extension 24b is connected with main part 24a and protrudes from grid 14a sidewall.The second extension 24c is positioned at the sidewall of grid 14a, and extends downward with the first extension 24b and be connected, and makes the fringe region of the first extension 24b protrude from the sidewall of corresponding the second extension 24c.
The lining material bed of material 22 that stays comprises three part 22a, 22b, 22c.The 22a of first of the lining material bed of material 22 is between electric charge storage layer 24 and substrate 10, as tunneling dielectric layer 22a.The second portion 22b of the lining material bed of material 22 is positioned at grid 14a below, is sandwiched between the main part 24a of grid 14a and electric charge storage layer 24, as top dielectric layer 22b.The third part 22c of the lining material bed of material 22 is positioned at the sidewall of grid 14a, is sandwiched between the second extension 24c of grid 14a and electric charge storage layer 24, as lining 22c.The spacer material layer that stays is positioned at the first extension 24b top of electric charge storage layer 24 and the sidewall of the second extension 24c as clearance wall 26a.
Carry out afterwards implanted ions, form doped region 28,30 in substrate 10.The conduction type of the admixture of implanting in doped region 28,30 is identical, and different from the conduction type of substrate 10.In one embodiment, substrate 10 is the doping of P type; Doped region 28,30 is the N-type doping.In another embodiment, substrate 10 is the N-type doping; Doped region 28,30 is the doping of P type.The N-type doping is for example phosphorus or arsenic; The doping of P type is for example boron or boron difluoride.Doped region 28,30 can be used as source area or the drain region of memory body.Doped region 28,30 is arranged in the substrate 10 of grid 14a both sides, and wherein the first extension 24b of each electric charge storage layer 24 and the second extension 24c are positioned at corresponding doped region 28,30 tops.
Then, see also shown in Figure 7ly, form dielectric layer 32 in substrate 10.Dielectric layer 32 is inserted the space between adjacent two grid 14a and is had smooth surface, exposes the surface of grid 14a.The material of dielectric layer 32 is for example silica, and the method for formation is for example to utilize chemical vapour deposition technique to form dielectric materials layer, afterwards, then carries out flatening process.Flatening process is for example etch back process or chemical mechanical milling tech (CMP).
See also shown in Figure 7ly, the memory cell of the embodiment of the present invention comprises grid 14a, gate dielectric layer 12, two electric charge storage layers 24, doped region 28,30 and character line 34.
Electric charge storage layer 24 is not identical with the material of gate dielectric layer 12.Each electric charge storage layer 24 comprises main part 24a, the first extension 24b and the second extension 24c.Each main part 24a is arranged in space 20a.Each first extension 24b and each main part 24a are connected and protrude from the sidewall of grid 14a.Each second extension 24c is connected with corresponding the first extension 24b, and extends upwardly to the sidewall of grid 14a.In other words, the fringe region of each first extension 24b protrudes from the sidewall of corresponding the second extension 24c, and it is anti-T-shaped that its section becomes.The too short restriction that will cause programming efficiency of the length L 1 of main part 24a.The length L 1 of main part 24a is longer, and the speed of its programming is faster, but the second bit effects is larger.The length of the first extension 24b is longer, more is not subjected to the control of grid, and therefore, the impact of second bit effect is less, still, still can improve the speed of programming.The length L 1 of main part 24a is for example 50 dust to 150 dusts; The length L 2 of the first extension 24b is for example 10 dust to 75 dusts.In one embodiment, the ratio of the length L 2 of the length L 1 of main part 24a and the first extension 24b is about 2: 1 to 5: 1.The material of main part 24a, the first extension 24b and the second extension 24c is identical.
Tunneling dielectric layer 22a is between electric charge storage layer 24 and substrate 10.Top dielectric layer 22b is positioned at grid 14a below, is sandwiched between the main part 24a of grid 14a and electric charge storage layer 24.Lining 22c is positioned at the sidewall of grid 14a, is sandwiched between the second extension 24c of grid 14a and electric charge storage layer 24.Clearance wall 26a is positioned at the first extension 24b top of electric charge storage layer 24 and the sidewall of the second extension 24c.In one embodiment, the material of tunneling dielectric layer 22a, top dielectric layer 22b, lining 22c and clearance wall 26a is different from the material of electric charge storage layer 24.
The conduction type of the admixture in doped region 28,30 is different from the conduction type of substrate 10.Doped region 28,30 is arranged in the substrate 10 of grid 14a both sides, and the first extension 24b of each electric charge storage layer 24 and the second extension 24c are positioned at corresponding doped region 28,30 tops.The conduction type of the admixture of implanting in doped region 28,30 is identical, and different from the conduction type of substrate 10.
Fig. 8 be three kinds of different memory cells when programming program speed and the graph of a relation of drain bias.
See also shown in Figure 8, curve 100 result for programming according to the memory cell of the electric charge storage layer 24 (comprising main part 24a, the first extension 24b and the second extension 24c, anti-T-shaped) of the above-mentioned Fig. 7 embodiment of the present invention.Curve 200 only comprises for existing known a kind of electric charge storage layer 24 of Fig. 9 the result that the memory cell of main part 24a is programmed.Curve 300 only comprises for existing known a kind of electric charge storage layer 24 of Figure 10 the result that the L-type memory cell of the first extension 24b and the second extension 24c is programmed.Shown by the result of Fig. 8, curve 100, when applying identical drain voltage and programme, electric charge storage layer is anti-T-shaped memory cell, has higher sequencing bit start voltage rate of change (dVt), i.e. the speed of programming.In sum, memory cell of the present invention can provide the charge storage region of location, so that electric charge localization storage fully reduces the second bit effect, reduces the behavior that programming is disturbed, and can reduce short-channel effect.In addition, the manufacture method of memory cell of the present invention, its technique is simple.
the above, it is only preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, although the present invention discloses as above with preferred embodiment, yet be not to limit the present invention, any those skilled in the art, within not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, any simple modification that foundation technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (13)
1. memory cell is characterized in that it comprises:
One grid is positioned in a substrate;
One gate dielectric layer is between this grid and this substrate, wherein below this gate dielectric layer both sides, this grid and have a space above this substrate; And
Two electric charge storage layers, respectively this electric charge storage layer comprises a main part, one first extension and one second extension, respectively this main body section is in this space respectively, respectively this first extension and this main part respectively are connected and protrude from the sidewall of this grid, each second extension is connected with corresponding this first extension, and extend upwardly to the sidewall of this grid, wherein respectively the fringe region of this first extension protrudes from the corresponding respectively sidewall of this second extension.
2. memory cell according to claim 1, characterized by further comprising two doped regions, is arranged in this substrate of this grid both sides, wherein respectively this first extension of this electric charge storage layer and this second extending part in corresponding this doped region top.
3. memory cell according to claim 1 characterized by further comprising: two linings lay respectively at this grid and respectively between this second extension of this electric charge storage layer; And two clearance walls, be positioned at this first extension top, this second extension is sandwiched between corresponding this lining and this clearance wall.
4. memory cell according to claim 1 is characterized in that the ratio of the length of the length of wherein said main part and this first extension is 2: 1 to 5: 1.
5. memory cell is characterized in that it comprises:
One grid is positioned in a substrate;
One gate dielectric layer is between this grid and this substrate, wherein below this gate dielectric layer both sides, this grid and form a space above this substrate;
Two electric charge storage layers, respectively this electric charge storage layer comprises a main part and an extension, and respectively this main body section is in this space respectively, and respectively this extension and this main part respectively are connected and protrude from the sidewall of this grid; And
Two linings are positioned at the sidewall of this grid, and respectively the fringe region of this extension of this electric charge storage layer protrudes from the sidewall of this lining.
6. memory cell according to claim 5, characterized by further comprising two doped regions, is arranged in this substrate of grid both sides, and wherein respectively this extension of this electric charge storage layer extends to above corresponding this doped region.
7. memory cell according to claim 5 is characterized in that the ratio of the length of the length of wherein said main part and this extension is 2: 1 to 5: 1.
8. the manufacture method of a memory cell is characterized in that it comprises the following steps:
Forming a gate dielectric layer in one substrate and be positioned at a grid on this gate dielectric layer, wherein below this gate dielectric layer both sides, this grid and form a space above this substrate;
Form two electric charge storage layers, respectively this electric charge storage layer comprises a main part and one first extension, and respectively this main body section is in this space respectively, and respectively this first extension and this main part respectively are connected and protrude from the sidewall of this grid; And
Form two doped regions in this substrate of this grid both sides, respectively this first extension of this electric charge storage layer extends to corresponding this doped region top.
9. the manufacture method of memory cell according to claim 8, it is characterized in that wherein respectively this electric charge storage layer also comprises one second extension, respectively this second extension is connected with this first extension, and extend upwardly to the sidewall of this grid, wherein respectively the fringe region of this first extension protrudes from the corresponding respectively sidewall of this second extension.
10. the manufacture method of memory cell according to claim 9 is characterized in that wherein this first extension of this electric charge storage layer respectively and this second extending part are in corresponding this doped region top.
11. the manufacture method of memory cell according to claim 8, it is characterized in that wherein before forming those electric charge storage layers, also comprise and form a lining material bed of material, cover the surface of this substrate, the sidewall of this gate dielectric layer, bottom, sidewall and the upper surface of this grid, respectively the fringe region of this first extension of this electric charge storage layer protrudes from this lining material bed of material that is positioned at this gate lateral wall.
12. the manufacture method of memory cell according to claim 11 is characterized in that the step that wherein forms those electric charge storage layers comprises:
Form a charge storage material layer, be covered on this lining material bed of material and fill up this space;
Form a spacer material layer, be covered on this charge storage material layer; And
Anisotropic etching removes this spacer material layer, this charge storage material layer and this lining material bed of material, to expose the surface of this grid and this substrate, stays two clearance walls, those electric charge storage layers and two linings.
13. the manufacture method of memory cell according to claim 8 characterized by further comprising at the sidewall of this grid and forms two linings, wherein respectively this first extension of this electric charge storage layer protrudes from the sidewall of this corresponding lining.
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| CN105304571A (en) * | 2014-06-27 | 2016-02-03 | 旺宏电子股份有限公司 | Manufacturing method of memory element |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040245564A1 (en) * | 2003-05-19 | 2004-12-09 | Takayuki Ogura | Semiconductor storage device, semiconductor device and their manufacturing methods, and portable electronic equipment, and IC card |
| US20050156227A1 (en) * | 2003-11-18 | 2005-07-21 | Applied Intellectual Properties Co., Ltd. | Nonvolatile memory with undercut trapping structure |
| CN1883046A (en) * | 2003-11-17 | 2006-12-20 | 英飞凌科技股份公司 | Charge-trapping memory device and methods for operating and manufacturing the cell |
-
2011
- 2011-11-25 CN CN201110391005.8A patent/CN103137659B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040245564A1 (en) * | 2003-05-19 | 2004-12-09 | Takayuki Ogura | Semiconductor storage device, semiconductor device and their manufacturing methods, and portable electronic equipment, and IC card |
| CN1883046A (en) * | 2003-11-17 | 2006-12-20 | 英飞凌科技股份公司 | Charge-trapping memory device and methods for operating and manufacturing the cell |
| US20050156227A1 (en) * | 2003-11-18 | 2005-07-21 | Applied Intellectual Properties Co., Ltd. | Nonvolatile memory with undercut trapping structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105304571A (en) * | 2014-06-27 | 2016-02-03 | 旺宏电子股份有限公司 | Manufacturing method of memory element |
| CN105304571B (en) * | 2014-06-27 | 2018-02-13 | 旺宏电子股份有限公司 | The manufacture method of memory cell |
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