CN103137641A - Array substrate and manufacturing method thereof and X ray flat plate detector - Google Patents
Array substrate and manufacturing method thereof and X ray flat plate detector Download PDFInfo
- Publication number
- CN103137641A CN103137641A CN2013100313815A CN201310031381A CN103137641A CN 103137641 A CN103137641 A CN 103137641A CN 2013100313815 A CN2013100313815 A CN 2013100313815A CN 201310031381 A CN201310031381 A CN 201310031381A CN 103137641 A CN103137641 A CN 103137641A
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- grid
- array base
- base palte
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses an array substrate and a manufacturing method of the array base plate and an X ray flat plate detector. The invention relates to the technical field of photoelectricity. Stability of a thin film transistor is strengthened. The array substrate comprises a base plate, a grid line layer, a grid insulating layer, a source layer and a data line layer. The grid line layer is formed on the substrate. The grid line layer comprises a grid electrode and a grid line connected with the grid electrode. The grid insulating layer is formed above the grid line layer. The source layer is formed above the insulating layer. The data line layer is formed above the source layer. The data line layer comprises a source electrode, a drain electrode and a data line connected with the source electrode. The data line crosses with the grid line. The source layer comprises a conductor layer and a semiconductor layer. The conductor layer is formed above the grid insulating layer. The conductor layer is packed by the semiconductor layer. The array substrate and a manufacturing method of the array substrate are mainly suitable for the X ray flat plate detector.
Description
Technical field
The present invention relates to field of photoelectric technology, relate in particular to a kind of array base palte and preparation method thereof, X ray flat panel detector.
Background technology
At present, common amorphous silicon X ray flat panel detector is a kind of X-ray detector take the amorphous silicon photodiodes array as core.X-ray detector comprises array base palte, this array base palte comprises thin-film transistor (TFT, Thin Flim Transistor) and photodiode, under the irradiation of X ray, scintillator layers or the luminescent coating of detector are converted to visible light with x-ray photon, then under the effect of photodiode, visible light is converted to the signal of telecommunication, thin-film transistor reads the signal of telecommunication and signal of telecommunication output is obtained showing image, wherein, in thin-film transistor, closing with conducting of raceway groove can be controlled thin-film transistor to the storage of the signal of telecommunication and read, therefore the performance of thin-film transistor is particularly important at this moment.
usually, raceway groove in thin-film transistor is positioned at semi-conductive active layer, particularly, as shown in Figure 1, substrate 1 in array base palte ' on deposit grid line layer 2 ', grid line layer 2 ' comprise grid 2a ' and grid line, and deposit on grid line layer gate insulation layer 3 ', gate insulation layer 3 ' top deposition active layer 4 ' (as amorphous silicon layer, also claim a-si), active layer 4 ' the top deposit ohmic contact layer (as doped amorphous silicon layer, also claim n+a-si), ohmic contact layer 5 ' top deposit data line layer 6 ', by composition technique, be formed with data wire, source electrode 6a ', drain electrode 6b ' and raceway groove.But when active layer adopted semi-conducting material, carrier mobility speed was low, is unfavorable for the conducting of raceway groove.In addition, semiconductor active layer contacts and forms the interface with gate insulation layer, charge carrier can be caught by the interface that is formed by semiconductor active layer and gate insulation layer, and capture effect is larger, will reduce like this quantity and the density of charge carrier, cause threshold voltage relatively large, so the stability that makes thin-film transistor relatively a little less than.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and preparation method thereof, X ray flat panel detector, can be beneficial to conducting and the transistorized stability of enhanced film of raceway groove.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of array base palte comprises:
Substrate;
Be formed at the grid line layer on described substrate, described grid line layer comprises grid and the grid line that is connected with described grid;
Be formed at the gate insulation layer of described grid line layer top;
Be formed at the active layer of described insulating barrier top;
Be formed at the data line layer of described active layer top, described data line layer comprises source electrode, drain electrode and the data wire that is connected with described source electrode, described data wire intersects with described grid line, wherein, described active layer comprises conductor layer and semiconductor layer, described conductor layer is formed at the top of described gate insulation layer, the described conductor layer of described semiconductor layer parcel.
Preferably, described conductor layer material is indium gallium zinc oxide conductor, and described semiconductor layer material is indium gallium zinc oxide semiconductor.
Further, be limited with pixel region in the zone that adjacent described grid line and described data wire intersect, be provided with photodiode in described pixel region, the lower end of described photodiode is electrically connected to described drain electrode, the upper end is electrically connected with the bias electrode layer.
Further, the upper end of described photodiode is provided with transparency conducting layer, the top of described transparency conducting layer is provided with the first passivation layer, described the first passivation layer is provided with via hole, and the top of described the first passivation layer is provided with the bias electrode layer, and described transparency conducting layer is electrically connected to the bias electrode layer by described via hole.
Further, the top of described bias electrode layer is provided with the second passivation layer.
A kind of manufacture method of above-mentioned array base palte comprises:
One substrate is provided;
The grid line that forms grid and be connected with described grid on described substrate;
Form gate insulation layer on the substrate that is formed with grid, grid line;
Being formed with the indium gallium zinc oxide film of deposited conductor on the substrate of gate insulation layer, by composition technique, form conductor layer;
Being formed with the indium gallium zinc oxide film of deposited semiconductor on the substrate of conductor layer, by composition technique, form semiconductor layer, the described conductor layer of described semiconductor layer parcel.
A kind of X-ray detector comprises x-ray source and sniffer, and described sniffer comprises above-mentioned array base palte.
array base palte that the embodiment of the present invention provides and preparation method thereof, the X ray flat panel detector, wherein, the active layer of described array base palte comprises conductor layer and semiconductor layer, described conductor layer is formed at the top of described gate insulation layer, the described conductor layer of described semiconductor layer parcel, make described semiconductor layer contact and form the interface with described conductor layer, can improve carrier mobility speed like this, be conducive to the conducting of raceway groove, and the contact layer defective at this interface is relatively less, make its capture effect to charge carrier reduce, thereby the quantity of charge carrier and concentration in the raising thin-film transistor, and then can reduce threshold voltage, improve the stability of thin-film transistor.
Description of drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or description of the Prior Art, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the schematic diagram of array base palte in prior art X ray flat panel detector;
The schematic diagram of the array base palte that Fig. 2 provides for the embodiment of the present invention;
The making flow chart of the array base palte that Fig. 3 provides for the embodiment of the present invention;
The making flow chart of array base palte in the X ray flat panel detector that Fig. 4 provides for the embodiment of the present invention;
Fig. 4 a-Fig. 4 g makes the schematic flow sheet of array base palte in the X ray flat panel detector in the embodiment of the present invention.
Reference numeral:
1,1 '-substrate, 2,2 '-grid line layer, 2a, 2a '-grid, 3,3 '-gate insulation layer, the 4-semiconductor layer, 4 '-active layer, the 5-conductor layer, 5 '-ohmic contact layer, 6,6 '-data line layer, 6a, 6a '-source electrode, 6b, 6b '-drain electrode, the 7-photodiode, 70-N type amorphous silicon tunic, 71-intrinsic amorphous silicon tunic, 72-P type amorphous silicon tunic, 8-transparency conducting layer, 9-the first passivation layer, 10-bias electrode layer, 11-the second passivation layer, 12-via hole
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skills obtain under the prerequisite of not making creative work belongs to the scope of protection of the invention.
As described in Figure 2, be a specific embodiment of array base palte of the present invention, described array base palte comprises:
Be formed at the grid line layer 2 on described substrate 1, described grid line layer 2 comprises grid 2a and the grid line (not shown) that is connected with described grid 2a;
Be formed at the gate insulation layer 3 of described grid line layer 2 tops;
Be formed at the active layer of described insulating barrier top;
Be formed at the data line layer 6 of described active layer top, described data line layer 6 comprises source electrode 6a, drain electrode 6b and the data wire that is connected with described source electrode 6a, and described data wire intersects with described grid line; Wherein, described active layer comprises conductor layer 5 and semiconductor layer 4, and described conductor layer 5 is formed at the top of described gate insulation layer 3, the described semiconductor layer 4 described conductor layers 5 of parcel.
in the array base palte that the embodiment of the present invention provides, the active layer of described array base palte is comprised of conductor layer 5 and semiconductor layer 4, described conductor layer 5 is formed at the top of described gate insulation layer 3, the described semiconductor layer 4 described conductor layers 5 of parcel, make described semiconductor layer 4 contact and form the interface with described conductor layer 5, can improve carrier mobility speed like this, be conducive to the conducting of raceway groove, and the contact layer defective at this interface is also relatively less, make its capture effect to charge carrier reduce, thereby the quantity of charge carrier and concentration in the raising thin-film transistor, and then can reduce threshold voltage, improve the stability of thin-film transistor.
The material of above-mentioned conductor layer 5 is indium gallium zinc oxide (being called for short IGZO, Indium Gallium Zinc Oxide) conductor, and the material of semiconductor layer 4 is also indium gallium zinc oxide semiconductor.Be not difficult to find out that semiconductor layer and conductor layer are same material, the Lattice Matching of semiconductor layer and conductor layer is capable better like this, can further reduce the defective of both contact interfaces, also more is conducive to the conducting of raceway groove and reduces capture effect to charge carrier.
Carrier mobility in indium gallium zinc oxide can reach 20～30 times of amorphous silicon, can improve like this charge-discharge velocity of thin-film transistor (TFT), and can reduce temperature to the impact of thin-film transistor stability.Certainly also be not limited to this scheme, it can also be other metal oxide known to other those skilled in the art, with the purpose that realizes that the present invention will reach, describe as indium gallium zinc oxide as preferred embodiment take conductor layer 5 and semiconductor layer 4 in the present invention.
Need to prove, indium gallium zinc oxide (IGZO) is usually by the magnetron sputtering film forming, as the O that passes into
2During quantity not sufficient, Rs value＜106 Ω form the IGZO film (namely corresponding above-mentioned conductor layer 5) of conductor; As the O that passes into
2Measure when moderate, Rs value＜1012 Ω form semi-conductive IGZO film (i.e. corresponding above-mentioned semiconductor layer 4); As the O that passes into
2Measure when more, Rs value＞1012 Ω form the IGZO film of insulator.
further be stressed that, it can also be seen that from Fig. 2 this array base palte forms two charge carrier passages, namely be respectively the IGZO layer of the semi-conductive IGZO layer+conductor of the semi-conductive IGZO layer on upper strata and lower floor+semi-conductive IGZO layer, can further reduce the distance of raceway groove like this, characteristic formula IDsat=W μ Cox/L* (VGS-Vth) 2 according to thin-film transistor, wherein, wherein L represents the distance of raceway groove, when other value is definite value, L reduces, IDsat (saturation current) increases, the thin-film transistor ratio is easier to reach ON state current value Ion like this, namely can make thin-film transistor reach high electric current by low-voltage, can reduce threshold voltage, save power consumption, and then can improve the characteristic of thin-film transistor.
Be limited with pixel region in the zone that adjacent described grid line and described data wire intersect, for embodiment of the present invention array base palte is applied on the X ray flat panel detector, also be provided with photodiode 7 in described pixel region, the lower end of described photodiode 7 is electrically connected to described drain electrode 6b, the upper end is electrically connected with bias electrode layer 10.Wherein bias electrode layer 10 can be accepted the biasing voltage signal that the outside provides, and then can apply bias voltage to photodiode 7, when having visible light to shine to photodiode 7, photodiode 7 can be converted to the signal of telecommunication with light signal, and the signal of telecommunication is stored in thin-film transistor.
Further, the upper end of described photodiode 7 can be provided with transparency conducting layer 8 (can be indium tin oxide, be called for short ITO, perhaps also can be IGZO), the top of described transparency conducting layer 8 is provided with the first passivation layer 9 (can be SiO2 or SiNx etc.), described the first passivation layer 9 is provided with via hole 12, and the top of described the first passivation layer 9 is provided with described bias electrode layer 10, described transparency conducting layer 8 is electrically connected to bias electrode layer 10 by described via hole, can realize like this being connected of bias electrode layer 10 and photodiode 7.
Further, the top of described bias electrode layer 10 is provided with the second passivation layer 11 (can be resin), and the second passivation layer 11 can be protected the bias electrode layer 10 that is positioned at its below.
As shown in Figure 3, the embodiment of the present invention also provides a kind of manufacture method of above-mentioned array base palte, comprising:
S300 provides a substrate;
S301, deposition grid line layer film on described substrate, by composition technique, the grid line that forms grid and be connected with described grid;
S302, deposition gate insulation layer film, form gate insulation layer 3 on the substrate that is formed with grid, grid line;
S303 being formed with the indium gallium zinc oxide film of deposited conductor on the substrate of gate insulation layer, by composition technique, forms conductor layer;
S304 being formed with the indium gallium zinc oxide film of deposited semiconductor on the substrate of conductor layer, by composition technique, forms semiconductor layer, the described conductor layer of described semiconductor layer parcel.
The manufacture method of this array base palte makes described semiconductor layer contact and form the interface with described conductor layer, can improve carrier mobility speed like this, be conducive to the conducting of raceway groove, and the contact layer defective at this interface is relatively less, make its capture effect to charge carrier reduce, thereby the quantity of charge carrier and concentration in the raising thin-film transistor, and then can reduce threshold voltage, improve the stability of thin-film transistor.
Describe the making of substrate in the X ray flat panel detector in conjunction with Fig. 2, Fig. 4 and Fig. 4 a-Fig. 4 g in detail, comprising:
S400 provides a substrate 1;
Wherein, described substrate 1 can be glass plate, quartz plate etc.
S401, deposition grid line layer film on described substrate 1, by composition technique, the grid line that forms grid 2a and be connected with described grid 2a;
Particularly, with reference to Fig. 4 a, at first can adopt the method for sputter or thermal evaporation to deposit one deck grid line tunic on substrate 1, the grid line layer film can use metal and the alloys thereof such as Cr, W, Ti, Ta, Mo, Al, Cu, then adopt common mask plate, by composition technique, the grid line layer film is carried out etching, the grid line that forms grid 2a and be connected with described grid 2a on substrate 1.
S402, deposition gate insulation layer film, form gate insulation layer 3 on the substrate that is formed with grid 2a, grid line;
Particularly, with reference to Fig. 4 b, can adopt plasma reinforced chemical vapour deposition method (PECVD) to deposit the gate insulation layer film on the substrate that is formed with grid 2a, grid line, form gate insulation layer 3.Wherein, the gate insulation layer film can be selected oxide, nitride or oxynitrides, the mist of the mist that corresponding reacting gas can become for SiH4, NH4, N2 or SiH2Cl4, NH3, N2.
S403, the indium gallium zinc oxide film of deposited conductor on the substrate that is formed with gate insulation layer 3 by composition technique, forms conductor layer 5;
Particularly, can adopt the method for sputter, and pass into sufficient O2, the indium gallium zinc oxide film of deposited conductor on the substrate that is formed with gate insulation layer 3, adopt mask plate, by composition technique, described indium gallium zinc oxide film is carried out etching, form the conductor layer 5 as shown in Fig. 4 c.
S404 being formed with the indium gallium zinc oxide film of deposited semiconductor on the substrate of conductor layer, by composition technique, forms semiconductor layer 4, the described semiconductor layer 4 described conductor layers 5 of parcel;
Again by Fig. 4 c as can be known, can adopt the method for sputter, and pass into appropriate O2, the indium gallium zinc oxide film of deposited semiconductor on the substrate that is formed with conductor layer 5, adopt mask plate, by composition technique, described indium gallium zinc oxide film is carried out etching, formation can be wrapped up the semiconductor layer 4 of described conductor layer 5.
Can find out that by step S403 and step S404 semiconductor layer and conductor layer are same material, make like this Lattice Matching of semiconductor layer and conductor layer capable better, can further reduce the defective of both contact interfaces, also more be conducive to the conducting of raceway groove and reduce capture effect to charge carrier.And can reach 20～30 times of amorphous silicon due to the carrier mobility in indium gallium zinc oxide, therefore the charge-discharge velocity of thin-film transistor (TFT) can be improved, and temperature can be reduced to the impact of thin-film transistor stability.
S405, deposition data wire layer film on the substrate that is formed with semiconductor layer 4, by composition technique, the data wire that forms raceway groove, drain electrode 6b, source electrode 6a and be connected with described source electrode 6a;
Particularly, as shown in Fig. 4 d, can adopt the method for sputter or thermal evaporation to deposit the data wire layer film on the substrate that is formed with semiconductor layer 4, the data line layer film can use metal and the alloys thereof such as Cr, W, Ti, Ta, Mo, Al, Cu, adopt mask plate, by composition technique, described data line layer film is carried out etching, form source electrode 6a, drain electrode 6b, data wire and raceway groove, wherein said data wire and the mutual square crossing of described grid line.
S406, deposition photodiode film on the substrate that is formed with source electrode 6a, drain electrode 6b, data wire and raceway groove by composition technique, forms photodiode 7 above described source electrode 6a;
Need to prove, in conjunction with Fig. 4 e, the manufacture method of described photodiode 7 specifically comprises:
S406a, adopt plasma reinforced chemical vapour deposition method (PECVD) successive sedimentation N-type amorphous silicon tunic 70, intrinsic amorphous silicon tunic 71, P type amorphous silicon tunic 72 on the substrate that is formed with source electrode 6a, drain electrode 6b, data wire and raceway groove, adopt mask plate, by composition technique, form the photodiode 7 as shown in Fig. 4 e.
S407, deposit transparent membrane of conducting layer on the substrate that is formed with photodiode 7 by composition technique, forms transparency conducting layer 8 in the upper end of described photodiode 7;
With reference to Fig. 4 f, can adopt method deposit transparent membrane of conducting layer on substrate of sputter, the electrically conducting transparent layer film can be ITO or IGZO, adopts mask plate, by composition technique, the electrically conducting transparent layer film is carried out etching, form transparency conducting layer 8 in the upper end of photodiode 7.
S408, deposition the first passivation layer film, form the first passivation layer 9 on the substrate that is formed with transparency conducting layer 8, and by composition technique, form via hole 12 above described photodiode 7;
Particularly, can adopt plasma reinforced chemical vapour deposition method (PECVD) to deposit the first passivation layer film on the substrate that is formed with transparency conducting layer 8, form the first passivation layer 9.Wherein, the first passivation layer film can be selected oxide, nitride or oxynitrides, the mist of the mist that corresponding reacting gas can become for SiH4, NH4, N2 or SiH2Cl4, NH3, N2, then can carry out etching to the first passivation layer film by composition technique, form the via hole 12 as shown in Fig. 4 f above photodiode 7.
S409, deposition bias electrode layer film, by composition technique, form bias electrode layer 10 on the substrate that is formed with the first passivation layer 9, and described bias electrode layer 10 is connected with transparency conducting layer 8 by described via hole 12;
As shown in Fig. 4 g, can adopt the method for sputter to deposit the bias electrode layer film on substrate, and the bias electrode layer film also can be ITO or IGZO, adopt mask plate, by composition technique, the bias electrode layer film is carried out etching, can form bias electrode layer 10, transparency conducting layer 8 is connected with bias electrode layer 10 by via hole 12, and then can realize being connected of bias electrode layer 10 and photodiode 7.
S410, deposition the second passivation layer film, form the second passivation layer 11 on the substrate that is formed with bias electrode layer 10;
With reference to Fig. 2, the second passivation layer 11 can be resin bed, and this resin bed can be protected the bias electrode layer 10 that is positioned at its below.
The embodiment of the present invention also provides a kind of X ray flat panel detector, comprises x-ray source and sniffer, and described sniffer comprises array base palte.Because array base palte can be above-mentioned any one form, therefore repeat no more here.
Thin-film transistor in above-mentioned array base palte has stability preferably, therefore can improve the display performance of X ray flat panel detector, in addition, can also adopt the photodiode of other type in the X ray flat panel detector that the embodiment of the present invention provides.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion by described protection range with claim.
Claims (9)
1. array base palte comprises:
Substrate;
Be formed at the grid line layer on described substrate, described grid line layer comprises grid and the grid line that is connected with described grid;
Be formed at the gate insulation layer of described grid line layer top;
Be formed at the active layer of described insulating barrier top;
Be formed at the data line layer of described active layer top, described data line layer comprises source electrode, drain electrode and the data wire that is connected with described source electrode, and described data wire intersects with described grid line, it is characterized in that,
Described active layer comprises conductor layer and semiconductor layer, and described conductor layer is formed at the top of described gate insulation layer, the described conductor layer of described semiconductor layer parcel.
2. array base palte according to claim 1, is characterized in that, described conductor layer material is indium gallium zinc oxide conductor, and described semiconductor layer material is indium gallium zinc oxide semiconductor.
3. array base palte according to claim 1 and 2, it is characterized in that, be limited with pixel region in the zone that adjacent described grid line and described data wire intersect, be provided with photodiode in described pixel region, the lower end of described photodiode is electrically connected to described drain electrode, the upper end is electrically connected with the bias electrode layer.
4. array base palte according to claim 3, it is characterized in that, the upper end of described photodiode is provided with transparency conducting layer, the top of described transparency conducting layer is provided with the first passivation layer, described the first passivation layer is provided with via hole, and the top of described the first passivation layer is provided with the bias electrode layer, and described transparency conducting layer is electrically connected to the bias electrode layer by described via hole.
5. array base palte according to claim 4, is characterized in that, the top of described bias electrode layer is provided with the second passivation layer.
6. the manufacture method as the described array base palte of claim 1-5 any one, is characterized in that, comprising:
One substrate is provided;
The grid line that forms grid and be connected with described grid on described substrate;
Form gate insulation layer on the substrate that is formed with grid, grid line;
Being formed with the indium gallium zinc oxide film of deposited conductor on the substrate of gate insulation layer, by composition technique, form conductor layer;
Being formed with the indium gallium zinc oxide film of deposited semiconductor on the substrate of conductor layer, by composition technique, form semiconductor layer, the described conductor layer of described semiconductor layer parcel.
7. the manufacture method of array base palte according to claim 6, is characterized in that, after forming described semiconductor layer, also comprises:
Being formed with deposition data wire layer film on the substrate of semiconductor layer, by composition technique, the data wire that forms raceway groove, drain electrode, source electrode and be connected with described source electrode;
Deposition photodiode film, by composition technique, form photodiode above described source electrode on the substrate that is formed with source electrode, drain electrode, data wire and raceway groove;
Being formed with deposit transparent membrane of conducting layer on the substrate of photodiode, by composition technique, form transparency conducting layer in the upper end of described photodiode.
8. the manufacture method of array base palte according to claim 7, is characterized in that, also comprises:
Being formed with deposition the first passivation layer film on the substrate of transparency conducting layer, form the first passivation layer, and by composition technique, form via hole above described photodiode;
Deposition bias electrode layer film, by composition technique, form the bias electrode layer on the substrate that is formed with the first passivation layer, and described bias electrode layer is connected with transparency conducting layer by described via hole;
Deposition the second passivation layer film, form the second passivation layer on the substrate that is formed with the bias electrode layer.
9. an X ray flat panel detector, comprise x-ray source and sniffer, it is characterized in that, described sniffer comprises the described array base palte of claim 1-5 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310031381.5A CN103137641B (en) | 2013-01-25 | 2013-01-25 | A kind of array base palte and preparation method thereof, X-ray flat panel detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310031381.5A CN103137641B (en) | 2013-01-25 | 2013-01-25 | A kind of array base palte and preparation method thereof, X-ray flat panel detector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103137641A true CN103137641A (en) | 2013-06-05 |
| CN103137641B CN103137641B (en) | 2015-10-21 |
Family
ID=48497237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310031381.5A Active CN103137641B (en) | 2013-01-25 | 2013-01-25 | A kind of array base palte and preparation method thereof, X-ray flat panel detector |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103137641B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103560135A (en) * | 2013-11-14 | 2014-02-05 | 北京京东方光电科技有限公司 | Array substrate of X-ray sensor and manufacturing method thereof |
| CN103681717A (en) * | 2013-09-24 | 2014-03-26 | 徐廷贵 | An image sensor of an alpha-IGZO film sensing array and a manufacturing method thereof |
| CN105552086A (en) * | 2015-11-17 | 2016-05-04 | 友达光电股份有限公司 | Light sensing device and manufacturing method thereof |
| CN105683993A (en) * | 2013-09-27 | 2016-06-15 | 硅显示技术有限公司 | Optical thin film transistor-type fingerprint sensor |
| CN107104108A (en) * | 2017-05-19 | 2017-08-29 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, flat panel detector and image documentation equipment |
| CN108767016A (en) * | 2018-05-21 | 2018-11-06 | 京东方科技集团股份有限公司 | A kind of thin film transistor and its manufacturing method, array substrate, display device |
| CN109671729A (en) * | 2017-10-17 | 2019-04-23 | 京东方科技集团股份有限公司 | Probe unit and preparation method thereof, flat panel detector |
| CN110047859A (en) * | 2019-04-24 | 2019-07-23 | 北京京东方传感技术有限公司 | Sensor and preparation method thereof |
| CN110277418A (en) * | 2019-06-21 | 2019-09-24 | 北京大学深圳研究生院 | A kind of pixel unit and preparation method thereof of perovskite imaging sensor |
| WO2020192194A1 (en) * | 2019-03-26 | 2020-10-01 | Boe Technology Group Co., Ltd. | Pin device and manufacturing method thereof, photosensitive device and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0354372A1 (en) * | 1988-07-19 | 1990-02-14 | Agency Of Industrial Science And Technology | Plurality of thin film field-effect transistors and method of manufacturing the same |
| CN102169907A (en) * | 2010-12-30 | 2011-08-31 | 友达光电股份有限公司 | Thin film transistor and method of manufacturing the same |
| CN102290440A (en) * | 2010-06-21 | 2011-12-21 | 财团法人工业技术研究院 | Transistor and manufacturing method thereof |
| CN102629610A (en) * | 2012-03-27 | 2012-08-08 | 北京京东方光电科技有限公司 | Array substrate of X-ray detection device and manufacturing method thereof |
| CN203055911U (en) * | 2013-01-25 | 2013-07-10 | 北京京东方光电科技有限公司 | Array substrate and X-ray flat plate detector |
-
2013
- 2013-01-25 CN CN201310031381.5A patent/CN103137641B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0354372A1 (en) * | 1988-07-19 | 1990-02-14 | Agency Of Industrial Science And Technology | Plurality of thin film field-effect transistors and method of manufacturing the same |
| CN102290440A (en) * | 2010-06-21 | 2011-12-21 | 财团法人工业技术研究院 | Transistor and manufacturing method thereof |
| CN102169907A (en) * | 2010-12-30 | 2011-08-31 | 友达光电股份有限公司 | Thin film transistor and method of manufacturing the same |
| CN102629610A (en) * | 2012-03-27 | 2012-08-08 | 北京京东方光电科技有限公司 | Array substrate of X-ray detection device and manufacturing method thereof |
| CN203055911U (en) * | 2013-01-25 | 2013-07-10 | 北京京东方光电科技有限公司 | Array substrate and X-ray flat plate detector |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681717A (en) * | 2013-09-24 | 2014-03-26 | 徐廷贵 | An image sensor of an alpha-IGZO film sensing array and a manufacturing method thereof |
| CN103681717B (en) * | 2013-09-24 | 2017-04-26 | 徐廷贵 | An image sensor of an alpha-IGZO film sensing array and a manufacturing method thereof |
| CN105683993A (en) * | 2013-09-27 | 2016-06-15 | 硅显示技术有限公司 | Optical thin film transistor-type fingerprint sensor |
| CN103560135A (en) * | 2013-11-14 | 2014-02-05 | 北京京东方光电科技有限公司 | Array substrate of X-ray sensor and manufacturing method thereof |
| CN103560135B (en) * | 2013-11-14 | 2015-12-02 | 北京京东方光电科技有限公司 | A kind of array base palte of X ray sensor and manufacture method thereof |
| CN105552086A (en) * | 2015-11-17 | 2016-05-04 | 友达光电股份有限公司 | Light sensing device and manufacturing method thereof |
| WO2018209947A1 (en) * | 2017-05-19 | 2018-11-22 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, flat panel detector, and imaging device |
| CN107104108A (en) * | 2017-05-19 | 2017-08-29 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, flat panel detector and image documentation equipment |
| CN107104108B (en) * | 2017-05-19 | 2020-08-21 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, flat panel detector and imaging equipment |
| CN109671729A (en) * | 2017-10-17 | 2019-04-23 | 京东方科技集团股份有限公司 | Probe unit and preparation method thereof, flat panel detector |
| US11355534B2 (en) | 2017-10-17 | 2022-06-07 | Beijing Boe Optoelectronics Technology Co., Ltd. | Detection element, manufacturing method thereof, flat panel detector |
| US11715746B2 (en) | 2017-10-17 | 2023-08-01 | Boe Technology Group Co., Ltd. | Detection element, manufacturing method thereof, flat panel detector |
| CN108767016A (en) * | 2018-05-21 | 2018-11-06 | 京东方科技集团股份有限公司 | A kind of thin film transistor and its manufacturing method, array substrate, display device |
| US11133367B2 (en) | 2018-05-21 | 2021-09-28 | Boe Technology Group Co., Ltd. | Thin film transistor and fabricating method thereof, array substrate and display device |
| WO2020192194A1 (en) * | 2019-03-26 | 2020-10-01 | Boe Technology Group Co., Ltd. | Pin device and manufacturing method thereof, photosensitive device and display device |
| CN110047859A (en) * | 2019-04-24 | 2019-07-23 | 北京京东方传感技术有限公司 | Sensor and preparation method thereof |
| CN110277418A (en) * | 2019-06-21 | 2019-09-24 | 北京大学深圳研究生院 | A kind of pixel unit and preparation method thereof of perovskite imaging sensor |
| CN110277418B (en) * | 2019-06-21 | 2021-03-30 | 北京大学深圳研究生院 | Pixel unit of perovskite image sensor and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103137641B (en) | 2015-10-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103137641B (en) | A kind of array base palte and preparation method thereof, X-ray flat panel detector | |
| US9490366B2 (en) | Thin film transistor, amorphous silicon flat detection substrate and manufacturing method | |
| Abliz et al. | Effects of yttrium doping on the electrical performances and stability of ZnO thin-film transistors | |
| CN102969361B (en) | Light durability amorphous metal oxide TFT device and display device | |
| CN101794819B (en) | Thin film transistor, method of manufacturing the thin film transistor and flat panel display device having the thin film transistor | |
| CN102969362B (en) | high stability amorphous metal oxide TFT device | |
| US20120181533A1 (en) | Thin film transistor array panel | |
| US20160358951A1 (en) | Tft driving backplane and method of manufacturing the same | |
| KR20100027377A (en) | Thin film transistor array substrate and method of fabricating the same | |
| TWI405335B (en) | Semiconductor structure and fabricating method thereof | |
| US8119465B1 (en) | Thin film transistor and method for fabricating the same | |
| CN102623459B (en) | Thin-film transistor memory and preparation method thereof | |
| CN101621076A (en) | Thin film transistor, method of manufacturing the same and flat panel display device having the same | |
| US9105730B2 (en) | Thin film transistor and fabrication method thereof | |
| TWI505476B (en) | Thin film transistor structure | |
| EP3703112A1 (en) | Method for manufacturing oled backplane | |
| US9818605B2 (en) | Oxide TFT, preparation method thereof, array substrate, and display device | |
| KR20100030068A (en) | Thin film transistor substrate and method of fabricating thereof | |
| KR101117727B1 (en) | Organic light emitting display and manufacturing method thereof | |
| CN104241392A (en) | Thin-film transistor, preparation method of thin-film transistor, display substrate and display device | |
| CN105576017B (en) | A kind of thin film transistor (TFT) based on zinc-oxide film | |
| US20180083142A1 (en) | Manufacture method of tft substrate and manufactured tft substrate | |
| KR20100057243A (en) | The thin film transistor and the manufacuring method thereof | |
| CN104124277A (en) | Thin film transistor and production method thereof and array substrate | |
| Park et al. | High-performance and stable transparent Hf–In–Zn–O thin-film transistors with a double-etch-stopper layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |