CN114639689A - Flat panel detector, manufacturing method thereof and X-ray imaging system - Google Patents

Flat panel detector, manufacturing method thereof and X-ray imaging system Download PDF

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Publication number
CN114639689A
CN114639689A CN202011481366.7A CN202011481366A CN114639689A CN 114639689 A CN114639689 A CN 114639689A CN 202011481366 A CN202011481366 A CN 202011481366A CN 114639689 A CN114639689 A CN 114639689A
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China
Prior art keywords
substrate
layer
flat panel
panel detector
orthographic projection
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夏会楠
侯学成
尚建兴
丁志
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BOE Technology Group Co Ltd
Beijing BOE Sensor Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Sensor Technology Co Ltd
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Priority to CN202011481366.7A priority Critical patent/CN114639689A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14643Photodiode arrays; MOS imagers
    • H01L27/14658X-ray, gamma-ray or corpuscular radiation imagers
    • H01L27/14663Indirect radiation imagers, e.g. using luminescent members
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14603Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14607Geometry of the photosensitive area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689MOS based technologies

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Health & Medical Sciences (AREA)
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Abstract

The embodiment of the application provides a flat panel detector, a manufacturing method thereof and an X-ray imaging system. The flat panel detector comprises a display area and a frame area surrounding the display area, wherein the display area comprises an area to be improved positioned at the edge of the display area; the heightening structure is positioned on one surface of the planarization layer, which is far away from the substrate, and the orthographic projection of the heightening structure on the substrate at least covers the area to be improved; the scintillator layer covers the elevation structure and the planarization layer, and includes a flat portion and a gradient portion located around the flat portion, wherein an orthographic projection of the gradient portion on the substrate does not overlap with an orthographic projection of the elevation structure on the substrate. This embodiment is through forming the bed hedgehopping structure on display substrate, utilizes the bed hedgehopping structure to reduce the shadow effect and treats the influence that improves the region to promote the homogeneity of treating the thickness of the scintillator layer in improving the region, promoted flat panel detector's display effect.

Description

Flat panel detector, manufacturing method thereof and X-ray imaging system
Technical Field
The application relates to the technical field of X-ray detection, in particular to a flat panel detector, a manufacturing method thereof and an X-ray imaging system.
Background
The flat panel detector can be applied to the fields of medical ray detection and industrial nondestructive detection, and can be used for detecting specific parts of a living body and detecting steel defects. Especially, the flat panel detector has a small radiation dose of X-rays, and has small influence on an operator and a person to be detected.
The flat panel detector may be classified into a direct conversion type flat panel detector and an indirect conversion type flat panel detector. The indirect conversion flat panel detector converts X-rays into visible light by using a scintillator coating, senses the visible light by using a photodiode to convert optical signals into electric signals, and generates an X-ray digital image according to the electric signals. The flat panel detector for indirect digital X-ray imaging has particularly strict requirements on image quality.
However, the inventor of the present application finds that, at present, the edge of the display area of the flat panel detector is prone to have a luminance abnormality, which affects the image quality of the flat panel detector.
Disclosure of Invention
Aiming at the defects of the prior art, the flat panel detector, the manufacturing method thereof and the X-ray imaging system are provided, and the flat panel detector, the manufacturing method and the X-ray imaging system are used for solving the problem that the edge brightness of a display area of the flat panel detector in the prior art is abnormal.
In a first aspect, an embodiment of the present application provides a flat panel detector, including a display area and a frame area surrounding the display area, where the display area includes an area to be improved located at an edge of the display area, and the flat panel detector includes:
the display substrate comprises a substrate, a device layer positioned on one side of the substrate and a planarization layer positioned on one side of the device layer far away from the substrate;
the heightening structure is positioned on one surface of the planarization layer, which is far away from the substrate, and the orthographic projection of the heightening structure on the substrate covers the area to be improved;
and the scintillator layer covers the elevation structure and the planarization layer and comprises a flat part and a gradient part positioned around the flat part, wherein the orthographic projection of the gradient part on the substrate is not overlapped with the orthographic projection of the elevation structure on the substrate.
In a second aspect, the present application provides an X-ray imaging system including the flat panel detector described above.
In a third aspect, an embodiment of the present application provides a method for manufacturing a flat panel detector, where the flat panel detector includes a display area and a frame area surrounding the display area, the display area includes an area to be improved located at an edge of the display area, and the method for manufacturing the flat panel detector includes:
providing a substrate, and sequentially manufacturing a device layer and a planarization layer on the substrate to form a display substrate;
forming a padding layer on the planarization layer and carrying out patterning treatment on the padding layer to form a padding structure, wherein the orthographic projection of the padding structure on the substrate covers the area to be improved;
forming a scintillator layer on the display substrate after the step-up structure is formed, wherein the scintillator layer comprises a flat part and a gradient part positioned around the flat part, and the orthographic projection of the gradient part on the substrate is not overlapped with the orthographic projection of the step-up structure on the substrate.
The technical scheme provided by the embodiment of the application has the following beneficial technical effects:
the flat panel detector, its manufacturing method and X ray imaging system that this application embodiment provided, set up the bed hedgehopping structure on display substrate, utilize the bed hedgehopping structure to reduce the influence that shadow effect treats in the improvement region, thereby promote the homogeneity of the thickness of the scintillation layer in treating in the improvement region, make the thickness of the scintillation layer in the region of being convenient for and except treating the thickness of the scintillation layer in the display area outside the improvement region basically the same, and then promote the luminance that makes the whole display area of flat panel detector basically the same, the display effect of flat panel detector has been promoted.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic diagram of a flat panel detector according to the prior art;
fig. 2 is a schematic structural diagram of a flat panel detector according to an embodiment of the present disclosure;
fig. 3 is a schematic top view of a flat panel detector according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram illustrating a cross-section of a pad-up structure in a flat panel detector according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a film structure of a flat panel detector according to an embodiment of the present disclosure;
FIG. 6 is a schematic structural diagram of another flat panel detector provided in an embodiment of the present application;
fig. 7 is a schematic top view of another flat panel detector provided in an embodiment of the present application;
FIG. 8 is a block diagram of an X-ray imaging system according to an embodiment of the present disclosure;
fig. 9 is a schematic flowchart of a method for manufacturing a flat panel detector according to an embodiment of the present disclosure;
fig. 10 is a schematic flowchart of step S1 in the method for manufacturing the flat panel detector shown in fig. 9.
Reference numerals:
1-a display substrate; 11-a substrate; 12-a device layer; 121-control circuit layer; 1211-gate; 1212 — active islands; 1213-source; 1214-a drain; 1215-a gate insulating layer; 122-a diode layer; 1221-a first electrode; 1222-PIN structure; 1223-a second electrode; 1224-bias line; 123-a light shielding portion; 124-a first insulating layer; 125-a resin layer; 126-a second insulating layer; 127-a third insulating layer; 13-a planarization layer; 14-a binding structure; 141-source signal binding structure; 142-gate signal bonding structure;
2-a scintillator layer;
3-an encapsulation layer;
4-packaging adhesive;
5-a raised structure;
10-a display area; 20-a frame area; 30-the region where the gradient portion is located; 40-area to be improved.
Detailed Description
Reference will now be made in detail to the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. In addition, if a detailed description of the known art is unnecessary for the features of the present application shown, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the singular forms "a", "an", "the" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The inventor of the present application finds that the problem of abnormal brightness is easy to occur at the edge of the display area of the prior art flat panel detector. The inventors of the present application have found that the above-described luminance abnormality does not occur due to the driving system.
Further research by the inventors of the present application has found that, as shown in fig. 1, the thickness of the edge of the scintillator layer 2 exhibits a gradual decrease phenomenon due to the manufacturing process of the scintillator layer 2, and the coverage area of the scintillator layer 2 is limited, so that the thickness of the scintillator layer 2 at the edge of the display area 10 exhibits a gradient change to cause a difference in the amount of sensitivity to X-rays, thereby causing a difference in the luminance of the area to be improved of a display image. This degrades the image quality of the flat panel detector.
Specifically, in the process of evaporation of the scintillator layer, because the mask plate adopted in the process of evaporation of the scintillator material cannot be tightly attached to the display substrate 1, but a gap exists, a shadow effect in the evaporation process can be caused, so that the edge of the scintillator layer 3 is diffused outwards, and the thickness of the edge of the scintillator layer 2 is intelligently formed and gradually reduced.
The application provides a flat panel detector, a manufacturing method thereof and an X-ray imaging system, which aim to solve the technical problems in the prior art.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.
The embodiment of the present application provides a flat panel detector, as shown in fig. 2 and fig. 3, the flat panel detector provided in this embodiment includes a display area 10 and a frame area 20 surrounding the display area 10, the display area 10 includes an area to be improved 40 located at an edge of the display area 10, and the flat panel detector includes a display substrate 1, an elevating structure 5 and a scintillator layer 2.
The display substrate 1 comprises a substrate 11, a device layer 12 positioned on one side of the substrate 11 and a planarization layer 13 positioned on one side of the device layer 12 far away from the substrate 11; the elevation structure 5 is positioned on one surface of the planarization layer 13, which is far away from the substrate 11, and the orthographic projection of the elevation structure 5 on the substrate 11 at least covers the area to be improved 40; the scintillator layer 2 covers the elevation structure 5 and the planarization layer 13 and includes a flat portion and a gradient portion surrounding the flat portion, wherein an orthographic projection of the gradient portion on the substrate 11 does not overlap with an orthographic projection of the elevation structure on the substrate.
It should be noted that the gradient portion refers to a portion where the thickness of the scintillator layer 2 gradually decreases at the edge, and specifically, as shown in fig. 1 and fig. 2, the thickness of the scintillator layer in the region 30 where the gradient portion is located gradually decreases in the direction from the display region 10 to the frame region 20.
It should be noted that the "region to be improved 40" mentioned in the present application refers to a range where a plurality of pixels at the boundary between the display area 10 and the frame area 20 are located, and when the padding structure 5 is not added, the region to be improved 40 overlaps the region 30 where the gradient portion is located, so that the brightness of the region to be improved 40 is low.
Specifically, the flat panel detector further includes an encapsulation layer 3 located on a side of the scintillator layer 2 away from the display substrate 1, and an encapsulation adhesive 4 for connecting the encapsulation layer 3 and the display substrate 1.
According to the flat panel detector provided by the embodiment, the heightening structure 5 is arranged on the display substrate 1, and the heightening structure 5 is utilized to reduce the influence of the shadow effect on the region to be improved 40, so that the uniformity of the thickness of the scintillator layer 2 in the region to be improved 40 is favorably improved, that is, the heightening structure 5 is utilized to push the initial position of the gradient part of the scintillator layer 2 to the frame region 20 from the display region 10, so that the initial position of the gradient part of the scintillator layer 2 is located outside the display region 10, the thickness of the scintillator layer 2 in the region to be improved 40 is basically the same as the thickness of the scintillator layer 2 in the display region 10 except the region to be improved 40, the brightness of the whole display region 10 of the flat panel detector is basically the same, and the display effect of the flat panel detector is improved.
Specifically, referring to fig. 2 and fig. 3, in the flat panel detector provided in this embodiment, the orthographic projection of the padding structure 5 on the substrate 1 also covers the frame region to be partially covered. This arrangement can further enhance the uniformity of the thickness of the scintillator layer 2 in the region to be improved 40.
Specifically, referring to fig. 2 and fig. 3, in the flat panel detector provided in this embodiment, the material of the scintillator includes cesium iodide or gadolinium oxysulfide.
Further, as shown in fig. 4, in the flat panel detector provided in this embodiment, the cross section of the bed height structure 5 is an arc shape. The curved elevation structure 5 can avoid the occurrence of a steep slope, thereby facilitating the uniformity of the thickness of the scintillator layer 2 located on the elevation structure 5.
Referring to fig. 4, in the flat panel detector provided in this embodiment, the width d of the padding structure 5 is 500 μm to 2000 μm. Specifically, the width of the region 40 to be improved is slightly different according to the influence of the size of the flat panel detector and other parameters, and in a specific application, the width of the raised structure 5 may be adjusted according to the width of the region 40 to be improved.
Referring to fig. 4, in the flat panel detector provided in this embodiment, the thickness of the raised structure 5 is d × tan θ, where θ is a gradient angle at the edge of the scintillator layer 2. I.e. the thickness of the raised structure 5 is adjusted in dependence on the diffusion of the edge region of the scintillator layer 2. Note that, taking the elevation structure 5 having an arc-shaped cross section as an example, the thickness of the elevation structure 5 is a thickness value of a position where the thickness of the elevation structure 5 is the largest.
Referring to fig. 4, in the flat panel detector provided in this embodiment, the material of the padding structure 5 is resin. Specifically, the raised structure 5 may be formed using a photosensitive resin, such as a photoresist.
Further, as shown in fig. 5, in the flat panel detector provided in this embodiment, the device layer 12 includes a control circuit layer 121 and a diode layer 122. The control circuit layer 121 and the diode layer 122 are explained in detail below.
As shown in fig. 5, the control circuit layer 121 includes a plurality of thin film transistors arranged in an array, a plurality of gate lines (not shown in fig. 5), and a plurality of data lines (not shown in fig. 5), the thin film transistors include an active island 1212, a gate 1211, a source 1213, and a drain 1214, the active island 1212 includes a source region, a drain region, and a channel region between the source region and the drain region, the gate 1211 is electrically connected to the gate lines, the source 1213 is electrically connected to the source region and the data line of the active island 1212, respectively, and the drain 1214 is electrically connected to the drain region of the active island 1212.
Specifically, as shown in fig. 5, in the display substrate 1 of the flat panel detector provided by the present application, the control circuit layer 121 includes a gate layer, a gate insulating layer 1215, an active layer, and a source drain electrode layer, which are sequentially arranged in a direction from the substrate 11 to the scintillator layer 2, wherein the gate layer includes a gate 1211 and a gate line electrically connected to the gate 1211, and the source drain electrode layer includes a source 1213, a drain 1214, and a data line electrically connected to the source 1213.
Although the thin film transistor in the display substrate 1 shown in fig. 5 has a bottom gate structure, in practical applications, the thin film transistor in the display substrate 1 may have a top gate structure, or the thin film transistor in the display substrate 1 may have a mixture of a top gate structure and a bottom gate structure.
As shown in fig. 5, the diode layer 122 includes a plurality of photodiodes arranged in an array and a plurality of bias lines 1224, each of the photodiodes includes a first electrode 1221, a second electrode 1223, and a PIN structure 1222 located between the first electrode 1221 and the second electrode 1223, each of the first electrodes 1221 is electrically connected to one of the drain electrodes 1214, and each of the second electrodes 1223 is electrically connected to one of the bias lines 1224.
Specifically, as shown in fig. 5, in the display substrate 1 of the flat panel detector provided in the present application, a first insulating layer 124 is disposed between the control circuit layer 121 and the diode layer 122.
Specifically, as shown in fig. 5, the present application provides a display substrate 1 of a flat panel detector, in which a photodiode includes a first electrode layer, a PIN structure layer, a second electrode layer, and a bias line layer arranged in this order in a direction from a substrate 11 toward a scintillator layer 2, wherein a second insulating layer 126 and a resin layer 125 for planarization are provided between the second electrode layer and the bias line layer.
Specifically, as shown in fig. 5, the first electrode layer includes a plurality of first electrodes 1221, and each of the first electrodes 1221 is electrically connected to the drain electrode 1214 of the corresponding thin film transistor. The PIN structure layer may be made of amorphous silicon material and includes a plurality of PIN structures 1222. The second electrode layer includes a plurality of second electrodes 1223, each of the second electrodes 1223 is electrically connected to one of the bias lines 1224, and the second electrode layer is made of a transparent conductive material, for example, the second electrode layer may be made of an Indium Tin Oxide (ITO) material. Specifically, a PIN structure refers to a structure in which a thin layer of lightly doped Intrinsic (Intrinsic) semiconductor is added between a P-type semiconductor and an N-type semiconductor material to form a P-I-N stack.
Further, as shown in fig. 5, in the flat panel detector provided in this embodiment, the device layer 12 further includes a plurality of light shielding portions 123, the light shielding portions 123 are located on a side of the control circuit layer 121 away from the substrate 11, an orthogonal projection of the light shielding portions 123 on the substrate 11 covers an orthogonal projection of the active islands 1212 on the substrate 11, and the light shielding portions 123 and the bias lines 1224 are made of the same material.
Specifically, as shown in fig. 5, the light shielding portion 123 may be integrated with the bias line 1224, or may be disposed separately from the bias line 1224, as long as the light shielding portion 123 is ensured to block light from irradiating the active layer of the thin film transistor. The light shielding portion 123 has a function of preventing light (natural light, visible light converted by the scintillator layer 2, and the like) from being irradiated to the active layer of the thin film transistor, thereby preventing the light from affecting the performance of the active layer to secure the performance of the thin film transistor. The light shielding layer and the bias line 1224 are fabricated in the same process, which is beneficial to reducing the number of process steps, thereby reducing the production cost.
Further, as shown in fig. 5 and fig. 6, in the flat panel detector provided in this embodiment, the display substrate 1 further includes a binding structure 14 located between the device layer 12 and the planarization layer 13, and the binding structure 14 is located in the frame region 20.
Specifically, the binding structures 14 are divided into gate signal binding structures 142 and data signal binding structures 141, wherein the gate signal binding structures 142 are used for transmitting gate signals to the gates 1211 and the data signal binding structures 141 are used for transmitting data signals to the sources 1213 of the corresponding thin film transistors of the display substrate 1, respectively.
Specifically, as shown in fig. 6 and 7, in order to ensure the insulating property, a third insulating layer 127 is further provided between the bonding structure 14 and the device layer 12.
As shown in fig. 5 and fig. 6, the operation principle of the flat panel detector is as follows: the scintillator layer 2 converts the attenuated X-ray penetrating the human body into visible light, the amorphous silicon photodiode array under the scintillator layer 2 converts the visible light into an electric signal, stored charges are formed on the capacitance of the photodiodes, the amount of the stored charges of each photodiode is in direct proportion to the intensity of the incident X-ray, the stored charges of each photodiode are scanned and read under the action of a control circuit formed by the control circuit layer 121, digital signals are output after analog-to-digital conversion, and then the X-ray digital image is formed through image processing.
Based on the same inventive concept, an embodiment of the present application further provides an X-ray imaging system, as shown in fig. 8, the X-ray imaging system in the present embodiment includes an X-ray emitting device and the flat panel detector in the above embodiment, which has the beneficial effects of the flat panel detector in the above embodiment, and details are not repeated here.
Based on the same inventive concept, an embodiment of the present application further provides a method for manufacturing a flat panel detector, as shown in fig. 2, fig. 3, and fig. 9, the flat panel detector in the embodiment includes a display area 10 and a frame area 20 surrounding the display area 10, where the display area 10 includes an area to be improved 40 located at an edge of the display area 10; the method for manufacturing the flat panel detector provided in the embodiment includes:
s1: a substrate 11 is provided, and a device layer 12 and a planarization layer 13 are sequentially formed on the substrate 11 to form the display substrate 1.
S2: a pad-up layer is formed on the planarization layer 13 and patterned to form a pad-up structure 5, and an orthographic projection of the pad-up structure 5 on the substrate 11 covers the region to be improved 40.
Specifically, in this step, a mask is used, and a resin material may be used to form the raised structure 5, and for example, photoresist is selected as a material for forming the raised structure 5, so that patterning to form the raised structure 5 can be more easily performed.
S3: a scintillator layer 2 is formed on the display substrate 1 after the step-up structure 5 is formed, and the scintillator layer 2 includes a flat portion and a gradient portion surrounding the flat portion, wherein an orthographic projection of the gradient portion on the substrate 11 does not overlap with an orthographic projection of the step-up structure 5 on the substrate 11.
Specifically, in this step, a material including cesium iodide or gadolinium oxysulfide may be fabricated in the display substrate 1 after the step-up structure 5 is formed to serve as the scintillator layer 2, and the scintillator layer 2 is formed by, for example, a deposition method or an attachment method.
In the method for manufacturing the flat panel detector provided by this embodiment, only by adding a mask, the step-up structure 5 is disposed on the display substrate 1, and the step-up structure 5 is utilized to reduce the influence of the shadow effect on the region 40 to be improved, so as to improve the uniformity of the thickness of the scintillator layer 2 in the region 40 to be improved, so that the thickness of the scintillator layer 2 in the region 40 is substantially the same as the thickness of the scintillator layer 2 in the display region 10 except the region 40 to be improved, and further improve the brightness of the whole display region 10 of the flat panel detector, thereby improving the display effect of the flat panel detector
Specifically, referring to fig. 5 and fig. 10, in the manufacturing method of the flat panel detector provided in this embodiment, step S1 includes:
s101: a gate layer including a plurality of gates 1211 and gate lines electrically connected to the gates 1211 is formed on the substrate 11.
S102: a gate insulating layer is formed on the gate layer.
S103: an active layer is formed on the gate insulating layer, the active layer including a plurality of active islands 1212, the active islands 1212 including source and drain regions and a channel region between the source and drain regions.
S104: a source drain electrode layer is formed on the active layer, and includes a plurality of source electrodes 1213, a plurality of drain electrodes 1214, and a plurality of data lines (not shown in fig. 5), wherein each source electrode 1213 is electrically connected to one data line, the source electrodes 1213 are electrically connected to the source regions of the active islands 1212, and the drain electrodes 1214 are electrically connected to the drain regions of the active islands 1212.
S105: a first insulating layer 124 is formed on the source-drain electrode layer.
S106: a first electrode layer is formed over the first insulating layer 124, and includes a plurality of first electrodes 1221, and each of the first electrodes 1221 is electrically connected to one of the drain electrodes 1214.
S107: a PIN structure layer is formed on the first electrode layer, the PIN structure layer includes a plurality of PIN structures 1222, and an orthogonal projection of each PIN structure 1222 on the substrate 11 is located within an orthogonal projection of one first electrode 1221 on the substrate 11.
S108: a second electrode layer on the PIN structure layer, the second electrode layer comprising a plurality of second electrodes 1223, an orthographic projection of each second electrode 1223 on the substrate 11 overlaying an orthographic projection of one PIN structure 1222 on the substrate 11.
S109: a resin layer is formed on the second electrode layer. The resin layer 125(resin layer) serves to planarize.
S110: a second insulating layer 126 is formed on the resin layer 125.
S111: a bias line layer is formed on the second insulating layer 126, the bias line layer including a plurality of bias lines 1224 and a plurality of light shielding portions 123, the bias lines 1224 being electrically connected to the corresponding second electrodes 1223, an orthographic projection of each light shielding portion 123 on the substrate 11 covering an orthographic projection of one active island on the substrate 11.
S112: a third insulating layer 127 is formed on the bias line layer.
S113: a bonding structure 14 is formed on the third insulating layer 127, and the bonding structure 14 is located in the frame region 20. Specifically, the binding structures 14 are divided into gate signal binding structures 142 and data signal binding structures 141, wherein the gate signal binding structures 142 are used for transmitting gate signals to the gates 1211 and the data signal binding structures 141 are used for transmitting data signals to the sources 1213 of the corresponding thin film transistors of the display substrate 1, respectively.
S114: a planarization layer 13 is formed on the binding structure 14.
Note that the thin film transistor in the display substrate 1 prepared according to the flow of step S1 is a thin film transistor with a bottom gate structure, but it is needless to say that the order of the steps in step S1 may be adjusted so that the thin film transistor in the display substrate 1 has a top gate structure, or the thin film transistor has a mixture of a top gate structure and a bottom gate structure.
By applying the embodiment of the application, the following beneficial effects can be at least realized:
the flat panel detector, the manufacturing method thereof and the X-ray imaging system provided by the embodiment of the application have the advantages that the padding structure is arranged on the display substrate, the influence of the shadow effect on the area to be improved is reduced by the padding structure, the uniformity of the thickness of the scintillator layer in the area to be improved is improved, the thickness of the scintillator layer in the area is enabled to be basically the same as the thickness of the scintillator layer in the display area except the area to be improved, the brightness of the whole display area of the flat panel detector is enabled to be basically consistent through promotion, and the display effect of the flat panel detector is improved.
Those of skill in the art will understand that various operations, methods, steps in the flow, measures, schemes discussed in this application can be alternated, modified, combined, or deleted. Further, other steps, measures, or schemes in various operations, methods, or flows that have been discussed in this application can be alternated, altered, rearranged, broken down, combined, or deleted. Further, steps, measures, schemes in the prior art having various operations, methods, procedures disclosed in the present application may also be alternated, modified, rearranged, decomposed, combined, or deleted.
In the description of the present application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present application.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In the description herein, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims (10)

1. A flat panel detector, includes the display area and surrounds the frame district of display area, the display area includes being located the region of treating improvement of display area edge, its characterized in that, flat panel detector includes:
the display substrate comprises a substrate, a device layer positioned on one side of the substrate and a planarization layer positioned on one side of the device layer far away from the substrate;
the elevation structure is positioned on one surface, away from the substrate, of the planarization layer, and the orthographic projection of the elevation structure on the substrate at least covers the area to be improved;
and the scintillator layer covers the elevation structure and the planarization layer and comprises a flat part and a gradient part positioned around the flat part, wherein the orthographic projection of the gradient part on the substrate is not overlapped with the orthographic projection of the elevation structure on the substrate.
2. The flat panel detector according to claim 1, wherein the raised structure is arcuate in cross-section.
3. The flat panel detector according to claim 2,
the width d of the heightening structure is 500-2000 mu m;
the raised structure has a thickness h of d tan θ, where θ is a slope angle at an edge of the scintillator layer.
4. The flat panel detector according to claim 1, wherein the material of the raised structure is resin.
5. The flat panel detector according to claim 1, wherein an orthographic projection of the elevated structure on the substrate further covers a portion of the border region.
6. A flat panel detector as claimed in claim 1, characterized in that the material of the scintillator comprises cesium iodide or gadolinium oxysulfide.
7. The flat panel detector according to any of claims 1-6, wherein the device layer comprises:
the control circuit layer comprises a plurality of thin film transistors arranged in an array manner, a plurality of gate lines and a plurality of data lines, wherein each thin film transistor comprises an active island, a gate, a source and a drain, the gate is electrically connected with the gate lines, and the source is electrically connected with the data lines;
the photodiode comprises a first electrode, a second electrode and a PIN structure located between the first electrode and the second electrode, each first electrode is electrically connected with one drain electrode, and each second electrode is electrically connected with one bias line.
8. The flat panel detector of claim 7, wherein the device layer further comprises:
a plurality of light shielding parts which are positioned on one side of the control circuit layer far away from the substrate, and the orthographic projection of the light shielding parts on the substrate covers the orthographic projection of the active layer on the substrate;
the light shielding portion and the bias line are made of the same material.
9. An X-ray imaging system comprising a flat panel detector according to any of claims 1 to 8.
10. A manufacturing method of a flat panel detector comprises a display area and a frame area surrounding the display area, wherein the display area comprises an area to be improved at the edge of the display area, and the manufacturing method of the flat panel detector comprises the following steps:
providing a substrate, and sequentially manufacturing a device layer and a planarization layer on the substrate to form a display substrate;
forming a padding layer on the planarization layer and carrying out patterning treatment on the padding layer to form a padding structure, wherein the orthographic projection of the padding structure on the substrate covers the area to be improved;
and forming a scintillator layer on the display substrate after the step-up structure is formed, wherein the scintillator layer comprises a flat part and a gradient part positioned around the flat part, and the orthographic projection of the gradient part on the substrate is not overlapped with the orthographic projection of the step-up structure on the substrate.
CN202011481366.7A 2020-12-15 2020-12-15 Flat panel detector, manufacturing method thereof and X-ray imaging system Pending CN114639689A (en)

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US20040155320A1 (en) * 2003-02-12 2004-08-12 Dejule Michael Clement Method and apparatus for deposited hermetic cover for digital X-ray panel
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