CN103137641B - A kind of array base palte and preparation method thereof, X-ray flat panel detector - Google Patents
A kind of array base palte and preparation method thereof, X-ray flat panel detector Download PDFInfo
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- CN103137641B CN103137641B CN201310031381.5A CN201310031381A CN103137641B CN 103137641 B CN103137641 B CN 103137641B CN 201310031381 A CN201310031381 A CN 201310031381A CN 103137641 B CN103137641 B CN 103137641B
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Abstract
The invention discloses a kind of array base palte and preparation method thereof, X-ray flat panel detector, relate to field of photoelectric technology, for can enhanced film transistor stability and invent.Described array base palte comprises: substrate; Be formed at the grid line layer on described substrate, the grid line that described grid line layer comprises grid and is connected with described grid; Be formed at the gate insulation layer above described grid line layer; Be formed at the active layer above described insulating barrier; Be formed at the data line layer above described active layer, the data wire that described data line layer comprises source electrode, drain electrode and is connected with described source electrode, described data wire intersects with described grid line, wherein, described active layer comprises conductor layer and semiconductor layer, described conductor layer is formed at the top of described gate insulation layer, and described semiconductor layer wraps up described conductor layer.The present invention is mainly useful in X-ray flat panel detector.
Description
Technical field
The present invention relates to field of photoelectric technology, particularly relate to a kind of array base palte and preparation method thereof, X-ray flat panel detector.
Background technology
At present, common amorphous silicon X-ray flat panel detector is a kind of X-ray detector being core with amorphous silicon photodiodes array.X-ray detector comprises array base palte, this array base palte comprises thin-film transistor (TFT, Thin Flim Transistor) and photodiode, under x-ray bombardment, x-ray photon is converted to visible ray by scintillator layers or the luminescent coating of detector, then under the effect of photodiode, visible ray is converted to the signal of telecommunication, thin-film transistor reads the signal of telecommunication and is exported by the signal of telecommunication and obtains showing image, wherein, in thin-film transistor, the closedown of raceway groove and conducting can control thin-film transistor to the storage of the signal of telecommunication and reading, therefore the performance of thin-film transistor is particularly important at this moment.
Usually, raceway groove in thin-film transistor is positioned at the active layer of semiconductor, particularly, as shown in Figure 1, in array base palte, substrate 1 ＇ deposits grid line layer 2 ＇, grid line layer 2 ＇ comprises grid 2a ＇ and grid line, and grid line layer deposits gate insulation layer 3 ＇, disposed thereon active layer 4 ＇ of gate insulation layer 3 ＇ is (as amorphous silicon layer, also a-si is claimed), the disposed thereon of active layer 4 ＇ has ohmic contact layer (as doped amorphous silicon layer, also n+a-si is claimed), ohmic contact layer 5 ＇ disposed thereon has data line layer 6 ＇, pass through patterning processes, be formed with data wire, source electrode 6a ＇, drain electrode 6b ＇ and raceway groove.But when active layer adopts semi-conducting material, carrier mobility speed is low, is unfavorable for the conducting of raceway groove.In addition, semiconductor active layer contacts with gate insulation layer and forms interface, charge carrier can be caught by the interface formed by semiconductor active layer and gate insulation layer, and capture effect is larger, quantity and the density of charge carrier will be reduced like this, cause threshold voltage relatively large, and then make the stability of thin-film transistor relatively weak.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and preparation method thereof, X-ray flat panel detector, can be beneficial to the conducting of raceway groove and the stability of enhanced film transistor.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of array base palte, comprising:
Substrate;
Be formed at the grid line layer on described substrate, the grid line that described grid line layer comprises grid and is connected with described grid;
Be formed at the gate insulation layer above described grid line layer;
Be formed at the active layer above described insulating barrier;
Be formed at the data line layer above described active layer, the data wire that described data line layer comprises source electrode, drain electrode and is connected with described source electrode, described data wire intersects with described grid line, wherein, described active layer comprises conductor layer and semiconductor layer, described conductor layer is formed at the top of described gate insulation layer, and described semiconductor layer wraps up described conductor layer.
Preferably, described conductor layer material is indium gallium zinc oxide conductor, and described semiconductor layer material is indium gallium zinc oxide semiconductor.
Further, be limited with pixel region in the region that adjacent described grid line and described data wire intersect, in described pixel region, be provided with photodiode, the lower end of described photodiode with described drain be electrically connected, upper end is electrically connected with biasing electrode layer.
Further, the upper end of described photodiode is provided with transparency conducting layer, the top of described transparency conducting layer is provided with the first passivation layer, described first passivation layer is provided with via hole, and the top of described first passivation layer is provided with biasing electrode layer, described transparency conducting layer is electrically connected with biasing electrode layer by described via hole.
Further, the top of described biasing electrode layer is provided with the second passivation layer.
A manufacture method for above-mentioned array base palte, comprising:
One substrate is provided;
The grid line forming grid on the substrate and be connected with described grid;
The substrate being formed with grid, grid line forms gate insulation layer;
The indium gallium zinc oxide film of deposited conductor on the substrate being formed with gate insulation layer, by patterning processes, forms conductor layer;
The indium gallium zinc oxide film of deposited semiconductor on the substrate being formed with conductor layer, by patterning processes, form semiconductor layer, described semiconductor layer wraps up described conductor layer.
A kind of X-ray detector, comprise x-ray source and sniffer, described sniffer comprises above-mentioned array base palte.
Array base palte that the embodiment of the present invention provides and preparation method thereof, X-ray flat panel detector, wherein, the active layer of described array base palte comprises conductor layer and semiconductor layer, described conductor layer is formed at the top of described gate insulation layer, described semiconductor layer wraps up described conductor layer, make described semiconductor layer and described layer come in contact and form interface, carrier mobility speed can be improved like this, be conducive to the conducting of raceway groove, and the contact layer defect at this interface is relatively less, it is reduced the capture effect of charge carrier, thus the quantity of charge carrier and concentration in raising thin-film transistor, and then can threshold voltage be reduced, improve the stability of thin-film transistor.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the schematic diagram of array base palte in prior art X-ray flat panel detector;
The schematic diagram of the array base palte that Fig. 2 provides for the embodiment of the present invention;
The Making programme figure of the array base palte that Fig. 3 provides for the embodiment of the present invention;
The Making programme figure of array base palte in the X-ray flat panel detector that Fig. 4 provides for the embodiment of the present invention;
Fig. 4 a-Fig. 4 g is the schematic flow sheet making array base palte in X-ray flat panel detector in the embodiment of the present invention.
Reference numeral:
1,1 ＇-substrate, 2,2 ＇-grid line layer, 2a, 2a ＇-grid, 3,3 ＇-gate insulation layer, 4-semiconductor layer, 4 ＇-active layer, 5-conductor layer, 5 ＇-ohmic contact layer, 6,6 ＇-data line layer, 6a, 6a ＇-source electrode, 6b, 6b ＇-drain electrode, 7-photodiode, 70-N type amorphous silicon tunic, 71-intrinsic amorphous silicon tunic, 72-P type amorphous silicon tunic, 8-transparency conducting layer, 9-first passivation layer, 10-biasing electrode layer, 11-second passivation layer, 12-via hole
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite of not making creative work, all belongs to the scope of protection of the invention.
As described in Figure 2, be a specific embodiment of array base palte of the present invention, described array base palte comprises:
Substrate 1;
Be formed at the grid line layer 2 on described substrate 1, the grid line (not shown) that described grid line layer 2 comprises grid 2a and is connected with described grid 2a;
Be formed at the gate insulation layer 3 above described grid line layer 2;
Be formed at the active layer above described insulating barrier;
Be formed at the data line layer 6 above described active layer, the data wire that described data line layer 6 comprises source electrode 6a, drain electrode 6b and is connected with described source electrode 6a, described data wire intersects with described grid line; Wherein, described active layer comprises conductor layer 5 and semiconductor layer 4, and described conductor layer 5 is formed at the top of described gate insulation layer 3, and described semiconductor layer 4 wraps up described conductor layer 5.
In the array base palte that the embodiment of the present invention provides, the active layer of described array base palte is made up of conductor layer 5 and semiconductor layer 4, described conductor layer 5 is formed at the top of described gate insulation layer 3, described semiconductor layer 4 wraps up described conductor layer 5, described semiconductor layer 4 is made to contact with described conductor layer 5 and form interface, carrier mobility speed can be improved like this, be conducive to the conducting of raceway groove, and the contact layer defect at this interface is also relatively less, it is reduced the capture effect of charge carrier, thus the quantity of charge carrier and concentration in raising thin-film transistor, and then can threshold voltage be reduced, improve the stability of thin-film transistor.
The material of above-mentioned conductor layer 5 is indium gallium zinc oxide (being called for short IGZO, Indium Gallium ZincOxide) conductor, and the material of semiconductor layer 4 is also indium gallium zinc oxide semiconductor.Be not difficult to find out that semiconductor layer and conductor layer are same material, the Lattice Matching of such semiconductor layer and conductor layer is capable better, can reduce the defect of both contact interfaces further, the conducting being also more conducive to raceway groove and the capture effect reduced charge carrier.
Carrier mobility in indium gallium zinc oxide can reach 20 ~ 30 times of amorphous silicon, can improve the charge-discharge velocity of thin-film transistor (TFT) like this, and can reduce the impact of temperature on thin-film transistor stability.Certainly also the program is not limited to, it can also be other metal oxide known to other those skilled in the art, to realize the object that the present invention will reach, in the present invention then with conductor layer 5 and semiconductor layer 4 for indium gallium zinc oxide is described for preferred embodiment.
It should be noted that, indium gallium zinc oxide (IGZO) passes through magnetron sputtering film forming usually, as the O passed into
2during quantity not sufficient, Rs value <106 Ω, is formed as the IGZO film (namely corresponding above-mentioned conductor layer 5) of conductor; As the O passed into
2when measuring moderate, Rs value <1012 Ω, is formed as the IGZO film (namely corresponding above-mentioned semiconductor layer 4) of semiconductor; As the O passed into
2when measuring more, Rs value >1012 Ω, is formed as the IGZO film of insulator.
Be stressed that further, from Fig. 2, it can also be seen that this array base palte forms two carrier pathway, namely the IGZO layer of the IGZO layer+semiconductor of the IGZO layer+conductor of the IGZO layer of the semiconductor on upper strata and the semiconductor of lower floor is respectively, the distance of raceway groove can be reduced so further, according to characteristic formula IDsat=W μ Cox/L* (VGS-Vth) 2 of thin-film transistor, wherein, wherein L represents the distance of raceway groove, when other value is definite value, L reduces, IDsat (saturation current) increases, such thin-film transistor ratio is easier to reach ON state current value Ion, namely thin-film transistor can be made to reach high electric current by low-voltage, threshold voltage can be reduced, save power consumption, and then the characteristic of thin-film transistor can be improved.
Pixel region is limited with in the region that adjacent described grid line and described data wire intersect, be applied in X-ray flat panel detector in order to embodiment of the present invention array base palte can be made, also be provided with photodiode 7 in described pixel region, with described, the lower end of described photodiode 7 drains that 6b is electrically connected, upper end is electrically connected with biasing electrode layer 10.Wherein biasing electrode layer 10 can accept the biasing voltage signal that outside provides, and then bias voltage can be applied to photodiode 7, when having visible ray according to during to photodiode 7, light signal can be converted to the signal of telecommunication by photodiode 7, and by electric signal storage in thin-film transistor.
Further, it (can be indium tin oxide that the upper end of described photodiode 7 can be provided with transparency conducting layer 8, be called for short ITO, or also can be IGZO), the top of described transparency conducting layer 8 is provided with the first passivation layer 9 (can be SiO2 or SiNx etc.), described first passivation layer 9 is provided with via hole 12, and the top of described first passivation layer 9 is provided with described biasing electrode layer 10, described transparency conducting layer 8 is electrically connected with biasing electrode layer 10 by described via hole, can realize the connection of biasing electrode layer 10 and photodiode 7 like this.
Further, the top of described biasing electrode layer 10 is provided with the second passivation layer 11 (can be resin), and the second passivation layer 11 can protect the biasing electrode layer 10 be positioned at below it.
As shown in Figure 3, the embodiment of the present invention additionally provides a kind of manufacture method of above-mentioned array base palte, comprising:
S300, provides a substrate;
S301, deposits grid line layer film on the substrate, by patterning processes, and the grid line forming grid and be connected with described grid;
S302, the substrate being formed with grid, grid line deposits gate insulation layer film, forms gate insulation layer 3;
S303, the indium gallium zinc oxide film of deposited conductor on the substrate being formed with gate insulation layer, by patterning processes, forms conductor layer;
S304, the indium gallium zinc oxide film of deposited semiconductor on the substrate being formed with conductor layer, by patterning processes, form semiconductor layer, described semiconductor layer wraps up described conductor layer.
The manufacture method of this array base palte makes described semiconductor layer and described layer come in contact and forms interface, carrier mobility speed can be improved like this, be conducive to the conducting of raceway groove, and the contact layer defect at this interface is relatively less, it is reduced the capture effect of charge carrier, thus the quantity of charge carrier and concentration in raising thin-film transistor, and then can threshold voltage be reduced, improve the stability of thin-film transistor.
Composition graphs 2, Fig. 4 and Fig. 4 a-Fig. 4 g describe the making of substrate in X-ray flat panel detector in detail, comprising:
S400, provides a substrate 1;
Wherein, described substrate 1 can be glass plate, quartz plate etc.
S401, described substrate 1 deposits grid line layer film, by patterning processes, and the grid line forming grid 2a and be connected with described grid 2a;
Particularly, with reference to Fig. 4 a, first the method for sputtering or thermal evaporation can be adopted to deposit one deck grid line tunic on substrate 1, grid line layer film can use the metals such as Cr, W, Ti, Ta, Mo, Al, Cu and alloy thereof, then common mask plate is adopted, by patterning processes, grid line layer film is etched, the grid line forming grid 2a on substrate 1 and be connected with described grid 2a.
S402, the substrate being formed with grid 2a, grid line deposits gate insulation layer film, forms gate insulation layer 3;
Particularly, with reference to Fig. 4 b, plasma reinforced chemical vapour deposition method (PECVD) can be adopted on the substrate being formed with grid 2a, grid line to deposit gate insulation layer film, form gate insulation layer 3.Wherein, gate insulation layer film can select oxide, nitride or oxynitrides, and corresponding reacting gas can be the mist of SiH4, NH4, N2 one-tenth or the mist of SiH2Cl4, NH3, N2.
S403, the indium gallium zinc oxide film of deposited conductor on the substrate being formed with gate insulation layer 3, by patterning processes, forms conductor layer 5;
Particularly, the method for sputtering can be adopted, and pass into not enough O2, the indium gallium zinc oxide film of deposited conductor on the substrate being formed with gate insulation layer 3, adopt mask plate, by patterning processes, described indium gallium zinc oxide film is etched, form conductor layer 5 as illustrated in fig. 4 c.
S404, the indium gallium zinc oxide film of deposited semiconductor on the substrate being formed with conductor layer, by patterning processes, form semiconductor layer 4, described semiconductor layer 4 wraps up described conductor layer 5;
Again from Fig. 4 c, the method of sputtering can be adopted, and pass into appropriate O2, the indium gallium zinc oxide film of deposited semiconductor on the substrate being formed with conductor layer 5, adopt mask plate, by patterning processes, described indium gallium zinc oxide film is etched, form the semiconductor layer 4 that can wrap up described conductor layer 5.
Can find out that semiconductor layer and conductor layer are same material by step S403 and step S404, make the Lattice Matching of semiconductor layer and conductor layer capable better like this, the defect of both contact interfaces can be reduced further, the conducting being also more conducive to raceway groove and the capture effect reduced charge carrier.And 20 ~ 30 times of amorphous silicon can be reached due to the carrier mobility in indium gallium zinc oxide, therefore can improve the charge-discharge velocity of thin-film transistor (TFT), and the impact of temperature on thin-film transistor stability can be reduced.
S405, the substrate being formed with semiconductor layer 4 deposits data wire layer film, by patterning processes, and the data wire forming raceway groove, drain electrode 6b, source electrode 6a and be connected with described source electrode 6a;
Particularly, as shown in figure 4d, the method of sputtering or thermal evaporation can be adopted on the substrate being formed with semiconductor layer 4 to deposit data wire layer film, data line layer film can use the metals such as Cr, W, Ti, Ta, Mo, Al, Cu and alloy thereof, adopt mask plate, by patterning processes, described data line layer film is etched, form source electrode 6a, drain electrode 6b, data wire and raceway groove, wherein said data wire and the mutual square crossing of described grid line.
S406, the substrate being formed with source electrode 6a, drain electrode 6b, data wire and raceway groove deposits photodiode film, by patterning processes, above described source electrode 6a, forms photodiode 7;
It should be noted that, composition graphs 4e, the manufacture method of described photodiode 7 specifically comprises:
S406a, adopt plasma reinforced chemical vapour deposition method (PECVD) successive sedimentation N-type non-crystalline silicon layer film 70, intrinsic amorphous silicon tunic 71, P-type non-crystalline silicon tunic 72 on the substrate being formed with source electrode 6a, drain electrode 6b, data wire and raceway groove, adopt mask plate, by patterning processes, form photodiode 7 as illustrated in figure 4e.
S407, deposit transparent membrane of conducting layer on the substrate being formed with photodiode 7, by patterning processes, forms transparency conducting layer 8 in the upper end of described photodiode 7;
With reference to Fig. 4 f, can adopt the method for sputtering deposit transparent membrane of conducting layer on substrate, electrically conducting transparent layer film can be ITO or IGZO, adopts mask plate, by patterning processes, electrically conducting transparent layer film is etched, form transparency conducting layer 8 in the upper end of photodiode 7.
S408, the substrate being formed with transparency conducting layer 8 deposits the first passivation layer film, forms the first passivation layer 9, and by patterning processes, above described photodiode 7, forms via hole 12;
Particularly, can adopt plasma reinforced chemical vapour deposition method (PECVD) on the substrate being formed with transparency conducting layer 8, deposit the first passivation layer film, form the first passivation layer 9.Wherein, first passivation layer film can select oxide, nitride or oxynitrides, corresponding reacting gas can be the mist of SiH4, NH4, N2 one-tenth or the mist of SiH2Cl4, NH3, N2, then can be etched the first passivation layer film by patterning processes, above photodiode 7, form via hole 12 as shown in fig. 4f.
S409, the substrate being formed with the first passivation layer 9 deposits bias electrode layer film, and by patterning processes, form biasing electrode layer 10, described biasing electrode layer 10 is connected with transparency conducting layer 8 by described via hole 12;
As shown in figure 4g, can adopt the method for sputtering on substrate, deposit bias electrode layer film, and bias electrode layer film also can be ITO or IGZO, adopt mask plate, by patterning processes, bias electrode layer film is etched, can form biasing electrode layer 10, transparency conducting layer 8 is connected with biasing electrode layer 10 by via hole 12, and then can realize the connection of biasing electrode layer 10 and photodiode 7.
S410, the substrate being formed with biasing electrode layer 10 deposits the second passivation layer film, forms the second passivation layer 11;
With reference to Fig. 2, the second passivation layer 11 can be resin bed, and this resin bed can protect the biasing electrode layer 10 be positioned at below it.
The embodiment of the present invention additionally provides a kind of X-ray flat panel detector, comprises x-ray source and sniffer, and described sniffer comprises array base palte.Because array base palte can be any one form above-mentioned, therefore repeat no more here.
Thin-film transistor in above-mentioned array base palte has good stability, therefore can improve the display performance of X-ray flat panel detector, in addition, can also adopt the photodiode of other type in the X-ray flat panel detector that the embodiment of the present invention provides.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should described be as the criterion with the protection range of claim.
Claims (9)
1. an array base palte, comprising:
Substrate;
Be formed at the grid line layer on described substrate, the grid line that described grid line layer comprises grid and is connected with described grid;
Be formed at the gate insulation layer above described grid line layer;
Be formed at the active layer above described gate insulation layer;
Be formed at the data line layer above described active layer, the data wire that described data line layer comprises source electrode, drain electrode and is connected with described source electrode, described data wire intersects with described grid line, it is characterized in that,
Described active layer comprises conductor layer and semiconductor layer, and described conductor layer is formed at the top of described gate insulation layer, and described semiconductor layer wraps up described conductor layer;
The formation material of described gate insulation layer is oxide, nitride or oxynitrides.
2. array base palte according to claim 1, is characterized in that, described conductor layer material is indium gallium zinc oxide conductor, and described semiconductor layer material is indium gallium zinc oxide semiconductor.
3. array base palte according to claim 1 and 2, it is characterized in that, pixel region is limited with in the region that adjacent described grid line and described data wire intersect, be provided with photodiode in described pixel region, the lower end of described photodiode with described drain be electrically connected, upper end is electrically connected with biasing electrode layer.
4. array base palte according to claim 3, it is characterized in that, the upper end of described photodiode is provided with transparency conducting layer, the top of described transparency conducting layer is provided with the first passivation layer, described first passivation layer is provided with via hole, and the top of described first passivation layer is provided with biasing electrode layer, described transparency conducting layer is electrically connected with biasing electrode layer by described via hole.
5. array base palte according to claim 4, is characterized in that, the top of described biasing electrode layer is provided with the second passivation layer.
6. a manufacture method for the array base palte as described in any one of claim 1-5, is characterized in that, comprising:
One substrate is provided;
The grid line forming grid on the substrate and be connected with described grid;
The substrate being formed with grid, grid line forms gate insulation layer;
The indium gallium zinc oxide film of deposited conductor on the substrate being formed with gate insulation layer, by patterning processes, forms conductor layer;
The indium gallium zinc oxide film of deposited semiconductor on the substrate being formed with conductor layer, by patterning processes, form semiconductor layer, described semiconductor layer wraps up described conductor layer.
7. the manufacture method of array base palte according to claim 6, is characterized in that, after the described semiconductor layer of formation, also comprises:
The substrate being formed with semiconductor layer deposits data wire layer film, by patterning processes, the data wire forming raceway groove, drain electrode, source electrode and be connected with described source electrode;
The substrate being formed with source electrode, drain electrode, data wire and raceway groove deposits photodiode film, by patterning processes, above described source electrode, forms photodiode;
Deposit transparent membrane of conducting layer on the substrate being formed with photodiode, by patterning processes, forms transparency conducting layer in the upper end of described photodiode.
8. the manufacture method of array base palte according to claim 7, is characterized in that, also comprises:
The substrate being formed with transparency conducting layer deposits the first passivation layer film, forms the first passivation layer, and by patterning processes, above described photodiode, form via hole;
The substrate being formed with the first passivation layer deposits bias electrode layer film, and by patterning processes, form biasing electrode layer, described biasing electrode layer is connected with transparency conducting layer by described via hole;
The substrate being formed with biasing electrode layer deposits the second passivation layer film, forms the second passivation layer.
9. an X-ray flat panel detector, comprises x-ray source and sniffer, it is characterized in that, described sniffer comprises the array base palte described in any one of claim 1-5.
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Families Citing this family (10)
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|---|---|---|---|---|
| CN103681717B (en) * | 2013-09-24 | 2017-04-26 | 徐廷贵 | An image sensor of an alpha-IGZO film sensing array and a manufacturing method thereof |
| KR101407936B1 (en) * | 2013-09-27 | 2014-06-17 | 실리콘 디스플레이 (주) | Optical thin film transistor type fingerprint sensor |
| CN103560135B (en) * | 2013-11-14 | 2015-12-02 | 北京京东方光电科技有限公司 | A kind of array base palte of X ray sensor and manufacture method thereof |
| TWI596793B (en) * | 2015-11-17 | 2017-08-21 | 友達光電股份有限公司 | Optical sensing apparatus and method for fabricating the same |
| CN107104108B (en) * | 2017-05-19 | 2020-08-21 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, flat panel detector and imaging equipment |
| CN109671729B (en) * | 2017-10-17 | 2021-04-09 | 京东方科技集团股份有限公司 | Detection unit, manufacturing method thereof and flat panel detector |
| CN108767016B (en) * | 2018-05-21 | 2021-09-21 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
| CN109950357A (en) * | 2019-03-26 | 2019-06-28 | 京东方科技集团股份有限公司 | A kind of PIN device and preparation method thereof, photosensory assembly, display device |
| CN110047859A (en) * | 2019-04-24 | 2019-07-23 | 北京京东方传感技术有限公司 | Sensor and preparation method thereof |
| CN110277418B (en) * | 2019-06-21 | 2021-03-30 | 北京大学深圳研究生院 | Pixel unit of perovskite image sensor and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0354372A1 (en) * | 1988-07-19 | 1990-02-14 | Agency Of Industrial Science And Technology | Plurality of thin film field-effect transistors and method of manufacturing the same |
| CN102169907A (en) * | 2010-12-30 | 2011-08-31 | 友达光电股份有限公司 | Thin film transistor and method of manufacturing the same |
| CN102290440A (en) * | 2010-06-21 | 2011-12-21 | 财团法人工业技术研究院 | Transistor and manufacturing method thereof |
| CN102629610A (en) * | 2012-03-27 | 2012-08-08 | 北京京东方光电科技有限公司 | Array substrate of X-ray detection device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203055911U (en) * | 2013-01-25 | 2013-07-10 | 北京京东方光电科技有限公司 | Array substrate and X-ray flat plate detector |
-
2013
- 2013-01-25 CN CN201310031381.5A patent/CN103137641B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0354372A1 (en) * | 1988-07-19 | 1990-02-14 | Agency Of Industrial Science And Technology | Plurality of thin film field-effect transistors and method of manufacturing the same |
| CN102290440A (en) * | 2010-06-21 | 2011-12-21 | 财团法人工业技术研究院 | Transistor and manufacturing method thereof |
| CN102169907A (en) * | 2010-12-30 | 2011-08-31 | 友达光电股份有限公司 | Thin film transistor and method of manufacturing the same |
| CN102629610A (en) * | 2012-03-27 | 2012-08-08 | 北京京东方光电科技有限公司 | Array substrate of X-ray detection device and manufacturing method thereof |
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