CN203055911U - Array substrate and X-ray flat plate detector - Google Patents
Array substrate and X-ray flat plate detector Download PDFInfo
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- CN203055911U CN203055911U CN 201320044606 CN201320044606U CN203055911U CN 203055911 U CN203055911 U CN 203055911U CN 201320044606 CN201320044606 CN 201320044606 CN 201320044606 U CN201320044606 U CN 201320044606U CN 203055911 U CN203055911 U CN 203055911U
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- grid line
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Abstract
The utility model discloses an array substrate and an X-ray flat plate detector, relates to the field of photoelectric technologies and aims to increase stability of a thin film transistor. The array substrate comprises a base plate, a grid line layer, a grid insulating layer, an active layer and a data line layer. The grid line layer is formed on the base plate and comprises a grid electrode and a grid line connected with the grid electrode. The grid insulating layer is formed above the grid line layer. The active layer formed above the grid insulating layer. The data line layer is formed above the active layer and comprises a source electrode, a drain electrode and a data line connected with the source electrode. The data line is intersected with the grid line. The active layer comprises a conductor layer and a semiconductor layer, the conductor layer is formed above the grid insulating layer, and the semiconductor layer wraps the conductor layer. The array substrate is mainly applied to the X-ray flat plate detector.
Description
Technical field
The utility model relates to field of photoelectric technology, relates in particular to a kind of array base palte and X ray flat panel detector.
Background technology
At present, common amorphous silicon X ray flat panel detector be a kind of be the X-ray detector of core with the amorphous silicon photodiodes array.X-ray detector comprises array base palte, comprise thin-film transistor (TFT in this array base palte, Thin Flim Transistor) and photodiode, under the irradiation of X ray, scintillator layers or the luminescent coating of detector are converted to visible light with x-ray photon, under the effect of photodiode, visible light is converted to the signal of telecommunication then, thin-film transistor reads the signal of telecommunication and signal of telecommunication output is obtained showing image, wherein, closing of raceway groove can be controlled thin-film transistor to the storage of the signal of telecommunication with conducting and read in the thin-film transistor, so the performance of thin-film transistor is particularly important at this moment.
Usually, raceway groove in the thin-film transistor is positioned at semi-conductive active layer, particularly, as shown in Figure 1, substrate 1 in the array base palte ' on deposit grid line layer 2 ', grid line layer 2 ' comprise grid 2a ' and grid line, and deposit on the grid line layer gate insulation layer 3 ', gate insulation layer 3 ' top deposition active layer 4 ' (as amorphous silicon layer, also claiming a-si), active layer 4 ' the top deposit ohmic contact layer (as doped amorphous silicon layer, also claim n+a-si), ohmic contact layer 5 ' top deposit data line layer 6 ', by composition technology, be formed with data wire, source electrode 6a ', drain electrode 6b ' and raceway groove.But when active layer adopted semi-conducting material, carrier mobility speed was low, is unfavorable for the conducting of raceway groove.In addition, semiconductor active layer contacts and forms the interface with gate insulation layer, charge carrier can be caught by the interface that is formed by semiconductor active layer and gate insulation layer, and capture effect is bigger, will reduce quantity and the density of charge carrier like this, cause threshold voltage relatively large, so make thin-film transistor stability relatively a little less than.
The utility model content
Embodiment of the present utility model provides a kind of array base palte and X ray flat panel detector, can be beneficial to conducting and the transistorized stability of enhanced film of raceway groove.
For achieving the above object, embodiment of the present utility model adopts following technical scheme:
A kind of array base palte comprises:
Substrate;
Be formed at the grid line layer on the described substrate, described grid line layer comprises grid and the grid line that is connected with described grid;
Be formed at the gate insulation layer of described grid line layer top;
Be formed at the active layer of described insulating barrier top;
Be formed at the data line layer of described active layer top, described data line layer comprises source electrode, drain electrode and the data wire that is connected with described source electrode, described data wire intersects with described grid line, wherein, described active layer comprises conductor layer and semiconductor layer, described conductor layer is formed at the top of described gate insulation layer, and described semiconductor layer wraps up described conductor layer.
Preferably, described conductor layer material is indium gallium zinc oxide conductor, and described semiconductor layer material is indium gallium zinc oxide semiconductor.
Further, be limited with pixel region in the zone that adjacent described grid line and described data wire intersect, be provided with photodiode in the described pixel region, the lower end of described photodiode is electrically connected with described drain electrode, the upper end is electrically connected with the bias electrode layer.
Further, the upper end of described photodiode is provided with transparency conducting layer, the top of described transparency conducting layer is provided with first passivation layer, described first passivation layer is provided with via hole, and the top of described first passivation layer is provided with the bias electrode layer, and described transparency conducting layer is electrically connected with the bias electrode layer by described via hole.
Further, the top of described bias electrode layer is provided with second passivation layer.
A kind of X-ray detector comprises x-ray source and sniffer, and described sniffer comprises above-mentioned array base palte.
The array base palte that the utility model embodiment provides and X ray flat panel detector, wherein, the active layer of described array base palte comprises conductor layer and semiconductor layer, described conductor layer is formed at the top of described gate insulation layer, described semiconductor layer wraps up described conductor layer, make described semiconductor layer contact and form the interface with described conductor layer, can improve carrier mobility speed like this, be conducive to the conducting of raceway groove, and the contact layer defective at this interface is less relatively, makes its capture effect to charge carrier reduce, thereby improves quantity and the concentration of charge carrier in the thin-film transistor, and then can reduce threshold voltage, improve the stability of thin-film transistor.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the schematic diagram of array base palte in the prior art X ray flat panel detector;
The schematic diagram of the array base palte that Fig. 2 provides for the utility model embodiment;
The making flow chart of the array base palte that Fig. 3 provides for the utility model embodiment;
The making flow chart of array base palte in the X ray flat panel detector that Fig. 4 provides for the utility model embodiment;
Fig. 4 a-Fig. 4 g is the schematic flow sheet of making array base palte in the X ray flat panel detector among the utility model embodiment.
Reference numeral:
1,1 '-substrate, 2,2 '-grid line layer, 2a, 2a '-grid, 3,3 '-gate insulation layer, the 4-semiconductor layer, 4 '-active layer, the 5-conductor layer, 5 '-ohmic contact layer, 6,6 '-data line layer, 6a, 6a '-source electrode, 6b, 6b '-drain electrode, the 7-photodiode, 70-N type amorphous silicon tunic, 71-intrinsic amorphous silicon tunic, 72-P type amorphous silicon tunic, 8-transparency conducting layer, 9-first passivation layer, 10-bias electrode layer, 11-second passivation layer, 12-via hole
Embodiment
Below in conjunction with the accompanying drawing among the utility model embodiment, the technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment only is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, the every other embodiment that those of ordinary skills obtain under the prerequisite of not making creative work belongs to the scope that the utility model is protected.
As described in Figure 2, be a specific embodiment of the utility model array base palte, described array base palte comprises:
Be formed at the grid line layer 2 on the described substrate 1, described grid line layer 2 comprises grid 2a and the grid line (not shown) that is connected with described grid 2a;
Be formed at the gate insulation layer 3 of described grid line layer 2 tops;
Be formed at the active layer of described insulating barrier top;
Be formed at the data line layer 6 of described active layer top, described data line layer 6 comprises source electrode 6a, drain electrode 6b and the data wire that is connected with described source electrode 6a, and described data wire intersects with described grid line; Wherein, described active layer comprises conductor layer 5 and semiconductor layer 4, and described conductor layer 5 is formed at the top of described gate insulation layer 3, the described conductor layer 5 of described semiconductor layer 4 parcels.
In the array base palte that the utility model embodiment provides, the active layer of described array base palte is made up of conductor layer 5 and semiconductor layer 4, described conductor layer 5 is formed at the top of described gate insulation layer 3, the described conductor layer 5 of described semiconductor layer 4 parcels, make described semiconductor layer 4 contact and form the interface with described conductor layer 5, can improve carrier mobility speed like this, be conducive to the conducting of raceway groove, and the contact layer defective at this interface is also less relatively, make its capture effect to charge carrier reduce, thereby the quantity of charge carrier and concentration in the raising thin-film transistor, and then can reduce threshold voltage, improve the stability of thin-film transistor.
The material of above-mentioned conductor layer 5 is indium gallium zinc oxide (being called for short IGZO, Indium Gallium Zinc Oxide) conductor, and the material of semiconductor layer 4 also is indium gallium zinc oxide semiconductor.Be not difficult to find out that semiconductor layer and conductor layer are same material, the lattice matching row of semiconductor layer and conductor layer is better like this, can further reduce the defective of both contact interfaces, also more is conducive to the conducting of raceway groove and reduces capture effect to charge carrier.
Carrier mobility in the indium gallium zinc oxide can reach 20～30 times of amorphous silicon, can improve the charge-discharge velocity of thin-film transistor (TFT) like this, and can reduce temperature to the influence of thin-film transistor stability.Certainly also be not limited to this scheme, it can also be other metal oxide known to other those skilled in the art, with the purpose that realizes that the utility model will reach, be that indium gallium zinc oxide is that preferred embodiment describes with conductor layer 5 and semiconductor layer 4 then in the utility model.
Need to prove that indium gallium zinc oxide (IGZO) is usually by the magnetron sputtering film forming, as the O that feeds
2During quantity not sufficient, Rs value＜106 Ω forms the IGZO film (namely corresponding above-mentioned conductor layer 5) of conductor; As the O that feeds
2Measure when moderate, Rs value＜1012 Ω forms semi-conductive IGZO film (namely corresponding above-mentioned semiconductor layer 4); As the O that feeds
2Amount more for a long time, Rs value＞1012 Ω forms the IGZO film of insulator.
Further be stressed that, it can also be seen that from Fig. 2 this array base palte forms two charge carrier passages, namely be respectively the IGZO layer+semi-conductive IGZO layer of the semi-conductive IGZO layer+conductor of the semi-conductive IGZO layer on upper strata and lower floor, can further reduce the distance of raceway groove like this, characteristic formula IDsat=W μ Cox/L* (VGS-Vth) 2 according to thin-film transistor, wherein, wherein L represents the distance of raceway groove, when other value is definite value, L reduces, IDsat (saturation current) increases, the thin-film transistor ratio is easier to reach ON state current value Ion like this, namely can make thin-film transistor reach high electric current by low-voltage, can reduce threshold voltage, save power consumption, and then can improve the characteristic of thin-film transistor.
Be limited with pixel region in the zone that adjacent described grid line and described data wire intersect, for the utility model embodiment array base palte is applied on the X ray flat panel detector, also be provided with photodiode 7 in the described pixel region, the lower end of described photodiode 7 is electrically connected with described drain electrode 6b, the upper end is electrically connected with bias electrode layer 10.Wherein bias electrode layer 10 can be accepted the biasing voltage signal that the outside provides, and then can apply bias voltage to photodiode 7, when visible light shone to photodiode 7, photodiode 7 can be converted to the signal of telecommunication with light signal, and the signal of telecommunication is stored in the thin-film transistor.
Further, the upper end of described photodiode 7 can be provided with transparency conducting layer 8 (can be indium tin oxide, be called for short ITO, perhaps also can be IGZO), the top of described transparency conducting layer 8 is provided with first passivation layer 9 (can be SiO2 or SiNx etc.), described first passivation layer 9 is provided with via hole 12, and the top of described first passivation layer 9 is provided with described bias electrode layer 10, described transparency conducting layer 8 is electrically connected with bias electrode layer 10 by described via hole, can realize being connected of bias electrode layer 10 and photodiode 7 like this.
Further, the top of described bias electrode layer 10 is provided with second passivation layer 11 (can be resin), and second passivation layer 11 can be protected the bias electrode layer 10 that is positioned at its below.
As shown in Figure 3, the utility model embodiment also provides a kind of manufacture method of above-mentioned array base palte, comprising:
S300 provides a substrate;
S301, at described substrate deposition grid line layer film, by composition technology, the grid line that forms grid and be connected with described grid;
S302 being formed with the substrate deposition gate insulation layer film of grid, grid line, forms gate insulation layer;
S303 being formed with the indium gallium zinc oxide film of deposited conductor on the substrate of gate insulation layer, by composition technology, forms conductor layer;
S304 being formed with the indium gallium zinc oxide film of deposited semiconductor on the substrate of conductor layer, by composition technology, forms semiconductor layer, and described semiconductor layer wraps up described conductor layer.
The manufacture method of this array base palte makes described semiconductor layer contact and form the interface with described conductor layer, can improve carrier mobility speed like this, be conducive to the conducting of raceway groove, and the contact layer defective at this interface is less relatively, make its capture effect to charge carrier reduce, thereby the quantity of charge carrier and concentration in the raising thin-film transistor, and then can reduce threshold voltage, improve the stability of thin-film transistor.
Describe the making of substrate in the X ray flat panel detector in detail in conjunction with Fig. 2, Fig. 4 and Fig. 4 a-Fig. 4 g, comprising:
S400 provides a substrate 1;
Wherein, described substrate 1 can be glass plate, quartz plate etc.
S401, at described substrate 1 deposition grid line layer film, by composition technology, the grid line that forms grid 2a and be connected with described grid 2a;
Particularly, with reference to Fig. 4 a, at first can adopt the method for sputter or thermal evaporation at substrate 1 deposition one deck grid line tunic, the grid line layer film can use metal and alloys thereof such as Cr, W, Ti, Ta, Mo, Al, Cu, adopt common mask plate then, by composition technology the grid line layer film is carried out etching, the grid line that forms grid 2a and be connected with described grid 2a at substrate 1.
S402 being formed with the substrate deposition gate insulation layer film of grid 2a, grid line, forms gate insulation layer 3;
Particularly, with reference to Fig. 4 b, can adopt plasma reinforced chemical vapour deposition method (PECVD) being formed with the substrate deposition gate insulation layer film of grid 2a, grid line, form gate insulation layer 3.Wherein, the gate insulation layer film can be selected oxide, nitride or oxynitrides for use, the mist of the mist that corresponding reacting gas can become for SiH4, NH4, N2 or SiH2Cl4, NH3, N2.
S403, the indium gallium zinc oxide film of deposited conductor on the substrate that is formed with gate insulation layer 3 by composition technology, forms conductor layer 5;
Particularly, can adopt the method for sputter, and feed sufficient O2, the indium gallium zinc oxide film of deposited conductor on the substrate that is formed with gate insulation layer 3, adopt mask plate, by composition technology described indium gallium zinc oxide film is carried out etching, form the conductor layer 5 shown in Fig. 4 c.
S404 being formed with the indium gallium zinc oxide film of deposited semiconductor on the substrate of conductor layer, by composition technology, forms semiconductor layer 4, the described conductor layer 5 of described semiconductor layer 4 parcels;
Again by Fig. 4 c as can be known, can adopt the method for sputter, and feed an amount of O2, the indium gallium zinc oxide film of deposited semiconductor on the substrate that is formed with conductor layer 5, adopt mask plate, by composition technology described indium gallium zinc oxide film is carried out etching, formation can be wrapped up the semiconductor layer 4 of described conductor layer 5.
Semiconductor layer and conductor layer are same material as can be seen by step S403 and step S404, make that like this lattice matching row of semiconductor layer and conductor layer is better, can further reduce the defective of both contact interfaces, also more be conducive to the conducting of raceway groove and reduce capture effect to charge carrier.And because the carrier mobility in the indium gallium zinc oxide can reach 20～30 times of amorphous silicon, therefore can improve the charge-discharge velocity of thin-film transistor (TFT), and can reduce temperature to the influence of thin-film transistor stability.
S405, being formed with the substrate deposition data wire layer film of semiconductor layer 4, by composition technology, the data wire that forms raceway groove, drain electrode 6b, source electrode 6a and be connected with described source electrode 6a;
Particularly, shown in Fig. 4 d, can adopt the method for sputter or thermal evaporation being formed with the substrate deposition data wire layer film of semiconductor layer 4, the data line layer film can use metal and alloys thereof such as Cr, W, Ti, Ta, Mo, Al, Cu, adopt mask plate, by composition technology described data line layer film is carried out etching, form source electrode 6a, drain electrode 6b, data wire and raceway groove, wherein said data wire and the mutual square crossing of described grid line.
S406 being formed with the substrate deposition photodiode film of source electrode 6a, drain electrode 6b, data wire and raceway groove, by composition technology, forms photodiode 7 above described source electrode 6a;
Need to prove that in conjunction with Fig. 4 e, the manufacture method of described photodiode 7 specifically comprises:
S406a, adopt plasma reinforced chemical vapour deposition method (PECVD) successive sedimentation N-type amorphous silicon tunic 70, intrinsic amorphous silicon tunic 71, P type amorphous silicon tunic 72 on the substrate that is formed with source electrode 6a, drain electrode 6b, data wire and raceway groove, adopt mask plate, by composition technology, form the photodiode 7 as shown in Fig. 4 e.
S407, deposit transparent membrane of conducting layer on the substrate that is formed with photodiode 7 by composition technology, forms transparency conducting layer 8 in the upper end of described photodiode 7;
With reference to Fig. 4 f, can adopt method deposit transparent membrane of conducting layer on substrate of sputter, the electrically conducting transparent layer film can be ITO or IGZO, adopts mask plate, by composition technology the electrically conducting transparent layer film is carried out etching, form transparency conducting layer 8 in the upper end of photodiode 7.
S408 being formed with the substrate deposition first passivation layer film of transparency conducting layer 8, forms first passivation layer 9, and by composition technology, forms via hole 12 above described photodiode 7;
Particularly, can adopt plasma reinforced chemical vapour deposition method (PECVD) being formed with the substrate deposition first passivation layer film of transparency conducting layer 8, form first passivation layer 9.Wherein, the first passivation layer film can be selected oxide, nitride or oxynitrides for use, the mist of the mist that corresponding reacting gas can become for SiH4, NH4, N2 or SiH2Cl4, NH3, N2, can carry out etching to the first passivation layer film by composition technology then, above photodiode 7, form the via hole 12 shown in Fig. 4 f.
S409 being formed with the substrate deposition bias electrode layer film of first passivation layer 9, by composition technology, forms bias electrode layer 10, and described bias electrode layer 10 is connected with transparency conducting layer 8 by described via hole 12;
Shown in Fig. 4 g, can adopt the method for sputter at substrate deposition bias electrode layer film, and the bias electrode layer film also can be ITO or IGZO, adopt mask plate, by composition technology the bias electrode layer film is carried out etching, can form bias electrode layer 10, transparency conducting layer 8 is connected with bias electrode layer 10 by via hole 12, and then can realize being connected of bias electrode layer 10 and photodiode 7.
S410 being formed with the substrate deposition second passivation layer film of bias electrode layer 10, forms second passivation layer 11;
With reference to Fig. 2, second passivation layer 11 can be resin bed, and this resin bed can be protected the bias electrode layer 10 that is positioned at its below.
The utility model embodiment also provides a kind of X ray flat panel detector, comprises x-ray source and sniffer, and described sniffer comprises array base palte.Because array base palte can be above-mentioned any one form, therefore repeat no more here.
Thin-film transistor in the above-mentioned array base palte has stability preferably, therefore can improve the display performance of X ray flat panel detector, in addition, can also adopt the photodiode of other type in the X ray flat panel detector that the utility model embodiment provides.
The above; it only is embodiment of the present utility model; but protection range of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; can expect easily changing or replacing, all should be encompassed within the protection range of the present utility model.Therefore, protection range of the present utility model should be as the criterion by described protection range with claim.
Claims (6)
1. array base palte comprises:
Substrate;
Be formed at the grid line layer on the described substrate, described grid line layer comprises grid and the grid line that is connected with described grid;
Be formed at the gate insulation layer of described grid line layer top;
Be formed at the active layer of described insulating barrier top;
Be formed at the data line layer of described active layer top, described data line layer comprises source electrode, drain electrode and the data wire that is connected with described source electrode, and described data wire intersects with described grid line, it is characterized in that,
Described active layer comprises conductor layer and semiconductor layer, and described conductor layer is formed at the top of described gate insulation layer, and described semiconductor layer wraps up described conductor layer.
2. array base palte according to claim 1 is characterized in that, described conductor layer material is indium gallium zinc oxide conductor, and described semiconductor layer material is indium gallium zinc oxide semiconductor.
3. array base palte according to claim 1 and 2, it is characterized in that, be limited with pixel region in the zone that adjacent described grid line and described data wire intersect, be provided with photodiode in the described pixel region, the lower end of described photodiode is electrically connected with described drain electrode, the upper end is electrically connected with the bias electrode layer.
4. array base palte according to claim 3, it is characterized in that, the upper end of described photodiode is provided with transparency conducting layer, the top of described transparency conducting layer is provided with first passivation layer, described first passivation layer is provided with via hole, and the top of described first passivation layer is provided with the bias electrode layer, and described transparency conducting layer is electrically connected with the bias electrode layer by described via hole.
5. array base palte according to claim 4 is characterized in that, the top of described bias electrode layer is provided with second passivation layer.
6. an X ray flat panel detector comprises x-ray source and sniffer, it is characterized in that, described sniffer comprises each described array base palte of claim 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320044606 CN203055911U (en) | 2013-01-25 | 2013-01-25 | Array substrate and X-ray flat plate detector |
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| CN 201320044606 CN203055911U (en) | 2013-01-25 | 2013-01-25 | Array substrate and X-ray flat plate detector |
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| CN203055911U true CN203055911U (en) | 2013-07-10 |
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| CN 201320044606 Expired - Lifetime CN203055911U (en) | 2013-01-25 | 2013-01-25 | Array substrate and X-ray flat plate detector |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137641A (en) * | 2013-01-25 | 2013-06-05 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof and X ray flat plate detector |
| CN110660816A (en) * | 2018-06-29 | 2020-01-07 | 京东方科技集团股份有限公司 | Flat panel detector |
-
2013
- 2013-01-25 CN CN 201320044606 patent/CN203055911U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137641A (en) * | 2013-01-25 | 2013-06-05 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof and X ray flat plate detector |
| CN110660816A (en) * | 2018-06-29 | 2020-01-07 | 京东方科技集团股份有限公司 | Flat panel detector |
| US11404469B2 (en) | 2018-06-29 | 2022-08-02 | Beijing Boe Optoelectronics Technology Co., Ltd. | Flat panel detector and manufacturing method thereof |
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Owner name: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY Effective date: 20150709 Owner name: JINGDONGFANG SCIENCE AND TECHNOLOGY GROUP CO., LTD Free format text: FORMER OWNER: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20150709 |
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Effective date of registration: 20150709 Address after: 100015 Jiuxianqiao Road, Beijing, No. 10, No. Patentee after: BOE TECHNOLOGY GROUP Co.,Ltd. Patentee after: BEIJING BOE OPTOELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 100176 Beijing city Daxing District economic and Technological Development Zone of Beijing Road No. 8 Patentee before: BEIJING BOE OPTOELECTRONICS TECHNOLOGY Co.,Ltd. |
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