CN109962113A - A kind of thin film transistor (TFT), array substrate and preparation method thereof and display panel - Google Patents
A kind of thin film transistor (TFT), array substrate and preparation method thereof and display panel Download PDFInfo
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- CN109962113A CN109962113A CN201910242724.XA CN201910242724A CN109962113A CN 109962113 A CN109962113 A CN 109962113A CN 201910242724 A CN201910242724 A CN 201910242724A CN 109962113 A CN109962113 A CN 109962113A
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- 239000000758 substrate Substances 0.000 title claims abstract description 75
- 239000010409 thin film Substances 0.000 title claims abstract description 55
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 117
- 239000010408 film Substances 0.000 claims abstract description 97
- 238000009413 insulation Methods 0.000 claims abstract description 53
- 230000008033 biological extinction Effects 0.000 claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- -1 grid Substances 0.000 claims abstract description 8
- XMBWDFGMSWQBCA-UHFFFAOYSA-N hydrogen iodide Chemical compound I XMBWDFGMSWQBCA-UHFFFAOYSA-N 0.000 claims description 26
- LLWRXQXPJMPHLR-UHFFFAOYSA-N methylazanium;iodide Chemical compound [I-].[NH3+]C LLWRXQXPJMPHLR-UHFFFAOYSA-N 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 21
- 229910052738 indium Inorganic materials 0.000 claims description 16
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 16
- 230000000694 effects Effects 0.000 claims description 12
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 11
- 229910052733 gallium Inorganic materials 0.000 claims description 11
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 11
- 238000004528 spin coating Methods 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 7
- QEZYDNSACGFLIC-UHFFFAOYSA-N CN.[I] Chemical compound CN.[I] QEZYDNSACGFLIC-UHFFFAOYSA-N 0.000 claims description 6
- YZZNJYQZJKSEER-UHFFFAOYSA-N gallium tin Chemical compound [Ga].[Sn] YZZNJYQZJKSEER-UHFFFAOYSA-N 0.000 claims description 6
- DRHWBADNSVQEGH-UHFFFAOYSA-L diiodyloxylead Chemical compound O=I(=O)O[Pb]OI(=O)=O DRHWBADNSVQEGH-UHFFFAOYSA-L 0.000 claims description 5
- GZCWPZJOEIAXRU-UHFFFAOYSA-N tin zinc Chemical compound [Zn].[Sn] GZCWPZJOEIAXRU-UHFFFAOYSA-N 0.000 claims description 5
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 239000011701 zinc Substances 0.000 claims description 4
- 239000004744 fabric Substances 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 21
- 238000005286 illumination Methods 0.000 description 16
- 239000004973 liquid crystal related substance Substances 0.000 description 9
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 4
- 230000001965 increasing effect Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZAKOWWREFLAJOT-CEFNRUSXSA-N D-alpha-tocopherylacetate Chemical compound CC(=O)OC1=C(C)C(C)=C2O[C@@](CCC[C@H](C)CCC[C@H](C)CCCC(C)C)(C)CCC2=C1C ZAKOWWREFLAJOT-CEFNRUSXSA-N 0.000 description 2
- BAVYZALUXZFZLV-UHFFFAOYSA-N Methylamine Chemical compound NC BAVYZALUXZFZLV-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000003574 free electron Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 230000011514 reflex Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910001257 Nb alloy Inorganic materials 0.000 description 1
- 229910000544 Rb alloy Inorganic materials 0.000 description 1
- HGWOWDFNMKCVLG-UHFFFAOYSA-N [O--].[O--].[Ti+4].[Ti+4] Chemical compound [O--].[O--].[Ti+4].[Ti+4] HGWOWDFNMKCVLG-UHFFFAOYSA-N 0.000 description 1
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical compound [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 description 1
- LADUOVJEPCTFNX-UHFFFAOYSA-N [Rb].[AlH3] Chemical compound [Rb].[AlH3] LADUOVJEPCTFNX-UHFFFAOYSA-N 0.000 description 1
- 238000004847 absorption spectroscopy Methods 0.000 description 1
- 238000000862 absorption spectrum Methods 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical group [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- IVUHDTWRNCXVCD-UHFFFAOYSA-N methylazanium;iodate Chemical compound [NH3+]C.[O-]I(=O)=O IVUHDTWRNCXVCD-UHFFFAOYSA-N 0.000 description 1
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
Abstract
The present invention relates to field of display technology more particularly to a kind of thin film transistor (TFT), array substrate and preparation method thereof and display panels.To improve the stability of high mobility TFT.A kind of thin film transistor (TFT), including setting gradually semiconductor layer, gate insulation layer, grid, interlayer insulating film and source electrode and drain electrode on substrate；Wherein, extinction film is additionally provided between the grid and the gate insulation layer, the orthographic projection of the extinction film over the substrate is Chong Die with the orthographic projection of the grid over the substrate.The embodiment of the present invention is used to improve the stability of high mobility TFT.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of thin film transistor (TFT), array substrate and preparation method thereof and
Display panel.
Background technique
Currently, thin film transistor (TFT) (Thin Film Transistor, TFT) is LCD (Liquid Crystal
Display, liquid crystal display) and AMOLED (Active Matrix Organic Light Emitting Diode, active square
Battle array Organic Light Emitting Diode) main driving element.
Summary of the invention
The embodiment of the present invention provides a kind of thin film transistor (TFT), array substrate and preparation method thereof and display panel, to
Improve the stability of high mobility TFT.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
In a first aspect, a kind of thin film transistor (TFT) is provided, including setting gradually semiconductor layer, gate insulation on substrate
Layer, grid, interlayer insulating film and source electrode and drain electrode；Extinction film, institute are additionally provided between the grid and the gate insulation layer
It is Chong Die with the orthographic projection of the grid over the substrate to state the orthographic projection of extinction film over the substrate.
Optionally, the extinction film is perovskite thin film.
Optionally, the material of the perovskite thin film is lead iodide methylamine.
Optionally, the extinction film with a thickness of
Optionally, the material of the semiconductor layer is indium oxide of the mass percentage of oxygen between 20%-35%
Indium gallium zinc-tin or indium gallium zinc of the mass percentage between 10%-30% of gallium tin, oxygen.
Second aspect, provides a kind of array substrate, including substrate, and setting over the substrate multiple are in array shape
The thin film transistor (TFT) of formula arrangement, the thin film transistor (TFT) are selected from thin film transistor (TFT) as described above.
The third aspect provides a kind of display panel, including array substrate as described above.
Fourth aspect, provides a kind of preparation method of array substrate, comprising: sequentially forms semiconductor layer, grid on substrate
Insulating layer, grid, interlayer insulating film and source electrode and drain electrode；The preparation method further include: by patterning processes in the grid
Extinction film is formed between pole and the gate insulation layer, the orthographic projection of the extinction film over the substrate covers the grid in institute
State the orthographic projection on substrate.
Optionally, extinction film is formed between the grid and the gate insulation layer by patterning processes includes: to be formed
It after gate insulation layer, is formed before the grid, forms lead iodide methylamine film on the gate insulation layer, and by exposing,
Etching carries out patterned process to the lead iodide methylamine film, obtains the extinction film.
Optionally, lead iodide methylamine film is formed on the gate insulation layer includes: the spin coating lead iodide on gate insulation layer
Solution, and lead iodide films are formed by curing under heat effect；The spin coating iodine methylamine solution on the lead iodide films, and adding
It is reacted under heat effect and is formed by curing lead iodide methylamine film.
Optionally, the iodate lead solution is formulated by lead iodide, DMF and water, wherein the lead iodide and DMF's
Molar ratio is 2-4, and the molarity of the lead iodide and the DMF in water is 0.5-1.5mol/L.
The embodiment of the present invention provides a kind of thin film transistor (TFT), array substrate and preparation method thereof and display panel, by
Increase extinction film between gate insulation layer and grid, when the illumination that backlight issues is injected in device, since extinction film is in substrate
On orthographic projection it is Chong Die with the orthographic projection of grid on substrate, and grid is corresponding with the channel region in semiconductor layer, therefore, passes through
The extinction film is blocked and is absorbed to light, can prevent light by grid reflex in channel region generate photo-generated carrier and
It drifts about in illumination bias lower threshold voltages, the electrology characteristic of semiconductor material is destroyed, so as to improve the steady of thin film transistor (TFT)
It is qualitative.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be in embodiment or description of the prior art
Required attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some realities of the invention
Example is applied, it for those of ordinary skill in the art, without creative efforts, can also be according to these attached drawings
Obtain other attached drawings.
Fig. 1 is a kind of structural schematic diagram of the thin film transistor (TFT) that provides of the relevant technologies in liquid crystal display panel；
Fig. 2 is a kind of structural schematic diagram for bottom gate type TFT that the relevant technologies provide；
Fig. 3 is a kind of structural schematic diagram for top gate type TFT that the relevant technologies provide；
Fig. 4 is a kind of physical structure of the thin film transistor (TFT) for n-channel type bottom grating structure that the relevant technologies provide；
Fig. 5 is a kind of schematic diagram for the negative drift of illumination bias lower threshold voltages that the relevant technologies provide；
Fig. 6 is a kind of structural schematic diagram for thin film transistor (TFT) that the embodiment of the present invention provides；
Fig. 7 is a kind of crystal structure figure for perovskite that the embodiment of the present invention provides；
Fig. 8 is the ultraviolet-visible absorption spectroscopy figure of perovskite under the different DMF concentration that the embodiment of the present invention provides；
Fig. 9 is a kind of structural schematic diagram for array substrate that the embodiment of the present invention provides；
Figure 10 is the surface of perovskite thin film and section Electronic Speculum view under the different technology conditions that the embodiment of the present invention provides
Figure comparison diagram；
Figure 11 is a kind of structural schematic diagram that light shield layer is formed on the substrate that the embodiment of the present invention provides；
Figure 12 is the structural schematic diagram that buffer layer is formed on the basis of Figure 11 that the embodiment of the present invention provides；
Figure 13 is the structural schematic diagram that semiconductor layer is formed on the basis of Figure 12 that the embodiment of the present invention provides；
Figure 14 is the structural schematic diagram that gate insulation layer is formed on the basis of Figure 13 that the embodiment of the present invention provides；
Figure 15 is the structural schematic diagram that extinction film is formed on the basis of Figure 14 that the embodiment of the present invention provides；
Figure 16 is the structural schematic diagram that grid is formed on the basis of Figure 15 that the embodiment of the present invention provides；
Figure 17 forms interlayer insulating film for what the embodiment of the present invention provided on the basis of Figure 16, and in layer insulation
Via hole is formed in layer, gate insulation layer, and forms the structure in signal conduction hole in interlayer insulating film, gate insulation layer and buffer layer
Schematic diagram；
Figure 18 is the output characteristic curve comparison diagram at the TFT different location that the embodiment of the present invention provides；
Figure 19 is under the positive gate bias that the embodiment of the present invention provides at 70 DEG C, in different time points the output characteristics of TFT
Curve comparison figure；
Figure 20 is under the negative-grid bias that the embodiment of the present invention provides at 70 DEG C, in different time points the output characteristics of TFT
Curve comparison figure.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that, term " center ", "upper", "lower", "front", "rear", " left side ",
The orientation or positional relationship of the instructions such as " right side ", "vertical", "horizontal", "top", "bottom", "inner", "outside" is based on the figure
Orientation or positional relationship is merely for convenience of description of the present invention and simplification of the description, rather than the device of indication or suggestion meaning or
Element must have a particular orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.
By taking liquid crystal display panel as an example, as shown in Figure 1, switch element of the thin film transistor (TFT) 1 as each sub-pix, setting
At more grid line G and data line D crossover location, as shown in Figure 1, include three electrodes, respectively grid 11, source electrode 12 and leakage
Pole 13, wherein grid 11 is connected with grid line G, and source electrode is connect with data line D, and drain electrode 13 is electrically connected with the pixel electrode in sub-pix
It connects, at work, by 12 input data voltage signal of source electrode, in 11 voltage V of gridgDriving under, if gate source voltage Vgs
Greater than the threshold voltage V of the thin film transistor (TFT)th, then be connected, power to pixel electrode, if gate source voltage V between source-drain electrodegsIt is small
In the threshold voltage V of the thin film transistor (TFT)th, then end between source-drain electrode, stop powering to pixel electrode.
Wherein, threshold voltage VthRefer to gate voltage when device is in critical conduction mode.In transfer curve, it is
Refer to that output voltage changes and the corresponding input voltage in midpoint of change dramatically break over region with input voltage.
Bottom gate type TFT can be divided by being configured at lower section or top, thin film transistor (TFT) 1 relative to semiconductor layer according to grid 11
Structure and top gate type TFT structure.
Be illustrated in figure 2 the structural schematic diagram of bottom gate type TFT a kind of, including be arranged on substrate 01 grid 11, covering
The gate insulation layer 14 of grid 11 includes the channel region A Chong Die with grid 11, source region B and drain electrode on gate insulation layer 14
The semiconductor layer 15 of region C is set to source-drain electrode pattern (the i.e. source on the source region B and drain region C on semiconductor layer 15
13), source-drain electrode pattern is electrically connected with source region B and drain region C respectively for pole 12 and drain electrode.It is illustrated in figure 3 a kind of top-gated
The structural schematic diagram of type TFT, including be arranged on substrate 01 include the channel region A Chong Die with grid 11, source region B and
The semiconductor layer 15 of drain region C, the gate insulation layer 14 for covering the semiconductor layer 15, the grid being arranged on gate insulation layer 14
11, and the interlayer insulating film 16 being arranged on the grid 11 and the source-drain electrode pattern being arranged on interlayer insulating film 16, equally
Ground, source-drain electrode pattern pass through the through-hole being arranged in interlayer insulating film 16 respectively and are electrically connected with source region B and drain region C.
By taking the thin film transistor (TFT) of n-channel type bottom grating structure as an example, physical structure is as shown in figure 4, in conjunction with Fig. 1, Fig. 2 and figure
4, when grid 11 imposes positive voltage, grid voltage VgElectric field is generated in gate insulation layer 14, power line is directed toward semiconductor by grid 11
15 surface of layer, and charge inducing is generated as gate voltage increases at surface, 15 surface of semiconductor layer will be changed by depletion layer
Electron accumulation layer forms inversion layer and (reaches cut-in voltage V when reaching strong inversionthWhen), it is just had plus voltage between source and drain
Carrier is by channel, and when source-drain voltage very little, conducting channel is approximately a constant resistance, and leakage current increases with source-drain voltage
And linearly increase.When source-drain voltage is very big, it can have an impact gate voltage so that in gate insulation layer 14 electric field by source to
Drain terminal gradually weakens, and electronics is gradually reduced by source to drain terminal in 15 surface inversion layer of semiconductor layer, and channel resistance is with source and drain
Voltage increases and increasing leakage current increase becomes slowly, and corresponding linear zone is to saturation region transition, when source-drain voltage increases to certain journey
Degree, drain terminal inversion layer thickness are kept to zero, and voltage is increasing, and device enters saturation region.In practical LCD production, hydrogen is mainly utilized
Change the ON state (being greater than cut-in voltage) of non-crystalline silicon tft to pixel capacitance ClcQuick charge keeps pixel capacitance C using OFF statelc
Voltage.
Wherein, threshold voltage VthThe factors such as the excess charges between 14 interface of gate insulation layer 14, channel region A and gate insulation layer
Related, the charge of gate insulation layer 14 or the capture of its surface will affect electric field to influence threshold voltage Vth。
In use, thin film transistor (TFT) 1 needs high mobility and suitable threshold voltage Vth, and under normal conditions,
Semiconductor layer 15 (such as the indium gallium tin (Indium Gallium Tin Oxide, IGTO), indium gallium zinc-tin of high mobility
(Indium Gallium Zinc Tin Oxide, IGZTO) and indium gallium zinc (Indium Gallium Zinc Oxide,
IGZO) etc.) there is a problem of stability difference under illumination bias, this is because: under light illumination, as shown in figure 5, luminous energy excites
Electronics in deep energy level Lacking oxygen is to conduction band EcOn, while the Lacking oxygen ion of electronics is lost in fermi level EfIt is formed about
New energy level, under minus gate voltage, positively charged Lacking oxygen ion is adsorbed to interface, conduction band EcOn free electron increase, it is right
Carrier concentration is higher for the TFT of high mobility, and free electron is increased more, so that under illumination bias, threshold
Threshold voltage VthOffset, as time increase degree becomes strong, so that the electrology characteristic of semiconductor material can be destroyed.
Based on this, for bottom gate type TFT, when being applied to liquid crystal display panel, since grid 11 is to backlight
Blocking for the light that source issues, can be avoided and cause threshold voltage V under illumination biasthDrift.And for top gate type TFT,
When being applied to liquid crystal display panel, since semiconductor layer 15 is located at the lower section of grid 11, the light that backlight issues irradiates
To channel region A, easily cause threshold voltage VthDrift, is unfavorable for the output characteristics of thin film transistor (TFT).
Based on this, referring to Fig. 6, the embodiment of the present invention provides a kind of thin film transistor (TFT) 1, including is successively set on substrate 01
Semiconductor layer 15, gate insulation layer 14, grid 11, interlayer insulating film 16 and source electrode 12 and drain electrode 13；Wherein, grid 11 and grid
Be additionally provided with extinction film 17 between insulating layer 14, extinction film 17 on substrate 01 orthographic projection and grid 11 on substrate 01 just
Projection overlapping.
In thin film transistor (TFT) provided in an embodiment of the present invention, by increasing extinction between gate insulation layer 14 and grid 11
Film 17, when the illumination that backlight issues is injected in device, since orthographic projection of the extinction film 17 on substrate 01 and grid 11 exist
Orthographic projection overlapping on substrate 01, and grid 11 is corresponding with the channel region in semiconductor layer 15, it is therefore, right by the extinction film 17
Light is blocked and is absorbed, can prevent light by grid 11 reflex in channel region generate photo-generated carrier and it is inclined in illumination
Depress VthDrift, destroys the electrology characteristic of semiconductor material, so as to improve the stability of thin film transistor (TFT).
Wherein, which can have the film of absorption for any pair of ultraviolet light.It such as can be titanium dioxide
Titanium film etc..
In one embodiment of the invention, which is perovskite thin film.Perovskite is generally cube or octahedron
Shape, crystal structure is as shown in fig. 7, its general molecular formula is ABX3, A are usually rare earth or alkaline earth element ion, and B were
Element ion is crossed, X is halide ion, and A and B all other ionic metal moieties similar in radius replace and keep its crystalline substance
Body structure is basically unchanged, and tests under different DMF concentration that the ultraviolet of perovskite thin film can by using ultraviolet-uisible spectrophotometer
See absorption spectrum, as shown in Figure 8, it will thus be seen that under different DMF concentration (in such as Fig. 8 perovskite concentration be respectively 10%wt,
20%wt and 30%wt), corresponding trap is respectively 41%, 89% and 92%, and therefore, perovskite thin film is to 400-
Ultraviolet light in the spectral region of 800nm all has obvious absorption, and as perovskite concentration increases, shows more obviously non-
Crystalline form state, it is more preferable to the assimilation effect of ultraviolet light.And high mobility oxide semiconductor is very poor to the stability of ultraviolet light, because
This, using the influence for the light that the film layer is used to that semiconductor material is protected to issue from backlight, to promote the stability of device.
In another embodiment of the present invention, the material of the perovskite thin film is lead iodide methylamine.It is in molecular formula ABX3In,
A is CH3NH3 +, B Pb2+, X I-.Lead iodide methylamine is the material generally used, and cost is relatively low, and non-to the absorption of ultraviolet light
Chang Qiang, manufacture craft are simple.
In another embodiment of the present invention, the extinction film with a thickness ofThe thickness of the extinction film is too thin,
Optical absorption is poor, too thick when etching to grid 11 etch period to be lengthened, and is unfavorable for the control of line width.
In order to keep higher mobility, optionally, the material of the semiconductor layer 15 be oxygen mass percentage between
Indium gallium of the mass percentage of indium gallium tin, oxygen between 20%wt-35%wt between 10wt%-30%wt
Zinc-tin or indium gallium zinc.
The embodiment of the present invention provides a kind of array substrate, referring to Fig. 9, including substrate 01, and setting on substrate more
A thin film transistor (TFT) 1 in array format arrangement, the thin film transistor (TFT) 1 are selected from thin film transistor (TFT) as described above.
The thin film transistor (TFT) that the beneficial effect and above-mentioned technical proposal of array substrate provided in an embodiment of the present invention provide
Beneficial effect is identical, and details are not described herein.
In order to further increase shaded effect, prevent backlight issue illumination be mapped to channel region generate photo-generated carrier and
V under illumination biasthDrift, destroys the electrology characteristic of semiconductor material, optionally, with continued reference to Fig. 5, which further includes
Thin film transistor (TFT) 1 is set close to the light shield layer 2 of 01 side of substrate, orthographic projection covering of the light shield layer 2 on substrate 01 is partly led
Orthographic projection of the body layer 15 on substrate 01.
Illumination can almost be ignored to thin under the collective effect of the light shield layer 2 and extinction film by the way that light shield layer 2 is arranged
The influence of film transistor 1, to obtain the high mobility TFT of high stability.
Optionally, with continued reference to Fig. 9, which can also include being arranged between light shield layer 2 and thin film transistor (TFT) 1
Buffer layer 3, source electrode 12 and the light shield layer 2 pass through the signal being arranged in buffer layer 3, gate insulation layer 14 and interlayer insulating film 16
Via hole P electrical connection.By the way that light shield layer 2 is connected to source electrode 12, makes to generate stable voltage on light shield layer 2, can be avoided
Floating gate effect is generated, guarantees the job stability of TFT.
Wherein, it should be noted that be the feelings that light shield layer 2 is completely covered in gate insulation layer 14 and interlayer insulating film 16 above
Condition, when the wherein at least one covering part light shield layer 2 in gate insulation layer 14 and interlayer insulating film 16, i.e., gate insulation layer 14 and/
Or interlayer insulating film 16 does not extend to the position of signal conduction hole P, which can also be only by being arranged in gate insulation layer 14
It is electrically connected with the signal conduction hole P one of in interlayer insulating film 16 and/or in buffer layer 2 with source electrode 12.
It should be noted that the array substrate that the embodiment of the present invention provides can be applied to liquid crystal display panel
(Liquid Crystal Display, abbreviation LCD) and organic electroluminescent LED (Organic Light Emitting
Diode, abbreviation OLED) display panel, when the array substrate is applied to liquid crystal display panel, which can also include
The pixel electrode being electrically connected with the drain electrode of TFT；It further can also include public electrode.
When array substrate is applied to OLED display panel, which can also include that the drain electrode with TFT is electrically connected
Anode, cathode and the organic material functional layer between anode and cathode.
The embodiment of the present invention provides a kind of display panel, including array substrate as described above.
The thin film transistor (TFT) that the beneficial effect and above-mentioned technical proposal of display panel provided in an embodiment of the present invention provide
Beneficial effect is identical, and details are not described herein.
In the description of above embodiment, particular features, structures, materials, or characteristics can be in any one or more
It can be combined in any suitable manner in embodiment or example.
The embodiment of the present invention provides a kind of preparation method of array substrate, referring to Fig. 6, comprising:
Semiconductor layer 15, gate insulation layer 14, grid 11, interlayer insulating film 16 and source electrode 12 are sequentially formed on substrate 01
With drain electrode 13；The preparation method further include: form extinction film 17 between grid 11 and gate insulation layer 14 by patterning processes, inhale
Light film 17 is Chong Die with orthographic projection of the grid 11 on substrate 01 in the orthographic projection on substrate 01.
The embodiment of the present invention provides a kind of preparation method of array substrate, by patterning processes in grid 11 and gate insulation layer
Between 14 formed extinction film 17, when backlight issue illumination inject device in when, due to extinction film 17 on substrate 01 just
Projection is Chong Die with orthographic projection of the grid 11 on substrate 01, and grid 11 is corresponding with the channel region in semiconductor layer 15, therefore, leads to
It crosses the extinction film 17 light is blocked and absorbed, can prevent light from being reflexed in channel region by grid 11 and generate photoproduction load
Stream and under illumination bias VthDrift, destroys the electrology characteristic of semiconductor material, so as to improve the steady of thin film transistor (TFT)
It is qualitative.
Wherein, in one embodiment of the invention, extinction is formed between grid 11 and gate insulation layer 14 by patterning processes
Film 17 includes: to be formed before grid 11 after forming gate insulation layer 14, and it is thin that lead iodide methylamine is formed on gate insulation layer 14
Film, and patterned process is carried out to the lead iodide methylamine film by exposure, etching, obtain extinction film 17.
It includes: the spin coating iodate lead solution on gate insulation layer 14 that lead iodide methylamine film is formed on gate insulation layer 14, and
Lead iodide films are formed by curing under heat effect；The spin coating iodine methylamine solution on lead iodide films, and it is anti-under heat effect
It should and be formed by curing lead iodide methylamine film.
In embodiments of the present invention, lead iodide methylamine film, compared with one-step method, Neng Gouwei are prepared by two step spin-coating methods
Lead iodide and iodate methylamine provide the sufficient reaction time, and it is uniform to be formed by lead iodide methylamine crystal size, to gate insulation layer
Level of coverage it is preferable, and surface is smooth, the cheap suitable large-scale production compared with vapour deposition process.
Optionally, which can be formulated by lead iodide, DMF and water, wherein lead iodide and DMF's rubs
, than that can be 2-4, the molarity of lead iodide and DMF in water can be 0.5-1.5mol/L for you.It can be utmostly
Upper raising film-formation result.
As shown in Figure 10, it is that 7:3 prepare in the case where spin coating that left side view, which is respectively the molar ratio of DMF and lead iodide,
The surface Electronic Speculum view and section Electronic Speculum view, right side view of the lead iodide methylamine film of acquisition are respectively DMF and lead iodide
Molar ratio is the surface Electronic Speculum view and section Electronic Speculum view that 2:1 carries out the lead iodide methylamine film prepared in the case where spin coating
Figure.
Comparison diagram can be learnt as shown in Figure 10: when the molar ratio of DMF and lead iodide is 7:3, surface topography and be cutd open
Face pattern is more preferable, forms a film finer and close.
The iodine methylamine solution can be formulated by iodine methylamine and isopropanol.
Based on this, the heating temperature that lead iodide films are formed by curing under heat effect can be 120-130 DEG C, heat
It is reacted under effect and the heating temperature for being formed by curing lead iodide methylamine film can be 100-120 DEG C.It can be improved lead iodide first
The crystallization uniformity and surface topography of amine.
Hereinafter, by being carried out with being provided with light shield layer in the array substrate to the preparation method of array substrate provided by the invention
It is described in detail.
Firstly, deposit one layer of metallic film on substrate 01 referring to Figure 11, to form light shield layer 2 by exposing, etching, it should
The material of metallic film can be aluminium, molybdenum, copper, aluminium rubidium alloy, molybdenum niobium alloy etc., and thickness can control
Then, referring to Figure 12, continuing buffer layer 3, buffer layer 3 on substrate 01 can be silicon nitride film and oxidation
Silicon thin film, thickness control exist
Then, referring to Figure 13, high mobility oxide semiconductor material is deposited on buffer layer 3, and pass through exposure etching
Technique formed semiconductor layer 15, wherein high mobility oxide semiconductor material can for oxygen mass percentage between
The indium gallium zinc-tin of the indium gallium tin of 20%-35% or the mass percentage of oxygen between 10%-30%.Thickness can
Think
Then, referring to Figure 14, continue to deposit gate insulation layer 14 on substrate, and control the silicon oxygen molar ratio of gate insulation layer 14
For 1-1.5, with a thickness of
And then, referring to Figure 15, the iodate lead solution of spin coating 1mol/L is (by lead iodide, DMF and water on gate insulation layer 14
The solution of preparation, wherein the molarity of lead iodide and DMF in water is 1mol/L), control revolving speed is 2500r/60s,
Lead iodide films are obtained in 120-130 DEG C of solidification 300s, the iodine methylamine solution of spin coating 30mg/mL is (by iodine on lead iodide films
Methylamine and isopropanol are formulated), 400s is equally reacted and solidified at 110-120 DEG C, obtains lead iodide methylamine film, with a thickness ofLater, patterned process is carried out to lead iodide methylamine film by exposure, etching technics, forms extinction film
17。
Then, referring to Figure 16, continuation deposits barrier metal layer on substrate 01, the material of barrier metal layer can for aluminium, molybdenum,
Copper, etc., with a thickness ofGrid 11 and grid line are formed by the techniques such as exposing, etching.
In turn, referring to Figure 17, continue to deposit interlayer insulating film 16 on substrate 01, material can be silica and nitridation
The combination film layer of silicon, thickness control existAnd it is formed in interlayer insulating film 16 for connecting semiconductor layer
Via hole between 15 and source-drain electrode, and for connecting the signal conduction hole P between source electrode 12 and light shield layer 2.
Finally, referring to Fig. 9, continue the deposited metal film on substrate 01, through overexposure, etching technics formed source electrode 12,
Drain electrode 13 and data line.
It is, of course, also possible to continue to form protective layer on substrate 01, material can be the combination of silica and silicon nitride
Film layer, thickness can beThe production of array substrate can be completed.
Experimental example
TFT obtained will be prepared under power on condition, carry out the test of TFT output characteristics.
As shown in figure 18, it is the output characteristic curve comparison diagram at a TFT different location, is in the breadth length ratio of channel region
In the case where 5/5, by testing the output characteristic curve at TFT different location, the variation range of threshold voltage is found
For 0.45 ± 1.5V, illustrate that TFT homogeneity obtained of the embodiment of the present invention is preferable.
As shown in figure 19, at 70 DEG C under the gate bias that are positive, the output characteristic curve comparison diagram of TFT in different time points, together
Sample is when 0.38V in the case where the breadth length ratio of channel region is 5/5, when the drift value of threshold voltage is from 0s increases to 2h
1.15V, subthreshold swing 0.77V.As shown in figure 20, for, at 70 DEG C, the output of TFT is special in different time points under negative-grid bias
Linearity curve the comparison diagram, -1.7V when offset of threshold voltage is from 0s are decreased to -2.2V when 2h, and subthreshold swing is -
0.5V.It is with good stability.
In conclusion by forming extinction film between grid and gate insulation layer, when device is injected in the illumination that backlight issues
When in part, since extinction film is Chong Die with orthographic projection of the grid on substrate 01 in the orthographic projection on substrate 01, and grid with partly lead
Channel region in body layer is corresponding, therefore, light is blocked and is absorbed by the extinction film, light can be prevented anti-by grid
Be incident upon in channel region generate photo-generated carrier and under illumination bias VthDrift, destroys the electrology characteristic of semiconductor material, thus
It can be improved the stability of thin film transistor (TFT).
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (11)
1. a kind of thin film transistor (TFT), which is characterized in that including set gradually semiconductor layer on substrate, gate insulation layer, grid,
Interlayer insulating film and source electrode and drain electrode；
Wherein, it is additionally provided with extinction film between the grid and the gate insulation layer, the extinction film is over the substrate just
It projects Chong Die with the orthographic projection of the grid over the substrate.
2. thin film transistor (TFT) according to claim 1, which is characterized in that
The extinction film is perovskite thin film.
3. thin film transistor (TFT) according to claim 2, which is characterized in that
The material of the perovskite thin film is lead iodide methylamine.
4. thin film transistor (TFT) according to claim 2, which is characterized in that
The extinction film with a thickness of
5. thin film transistor (TFT) according to claim 2, which is characterized in that
The material of the semiconductor layer is the matter of indium gallium tin of the mass percentage between 20%-35% of oxygen, oxygen
Measure indium gallium zinc-tin or indium gallium zinc of the percentage composition between 10%-30%.
6. a kind of array substrate, which is characterized in that including substrate, and setting over the substrate multiple arrange in array format
The thin film transistor (TFT) of cloth, the thin film transistor (TFT) are selected from thin film transistor (TFT) as described in any one in claim 1-5.
7. a kind of display panel, which is characterized in that including array substrate as claimed in claim 6.
8. a kind of preparation method of array substrate characterized by comprising
Semiconductor layer, gate insulation layer, grid, interlayer insulating film and source electrode and drain electrode are sequentially formed on substrate；
The preparation method further include: extinction film, institute are formed between the grid and the gate insulation layer by patterning processes
It states the orthographic projection of extinction film over the substrate and covers the orthographic projection of the grid over the substrate.
9. the preparation method of array substrate according to claim 8, which is characterized in that
Forming extinction film between the grid and the gate insulation layer by patterning processes includes:
It after forming gate insulation layer, is formed before the grid, forms lead iodide methylamine film on the gate insulation layer, and
Patterned process is carried out to the lead iodide methylamine film by exposing, etching, obtains the extinction film.
10. the preparation method of array substrate according to claim 9, which is characterized in that formed on the gate insulation layer
Lead iodide methylamine film includes:
The spin coating iodate lead solution on gate insulation layer, and lead iodide films are formed by curing under heat effect；
The spin coating iodine methylamine solution on the lead iodide films, and reacted under heat effect and to be formed by curing lead iodide methylamine thin
Film.
11. the preparation method of array substrate according to claim 10, which is characterized in that
The iodate lead solution is formulated by lead iodide, DMF and water, wherein and the molar ratio of the lead iodide and DMF are 2-4,
The molarity of the lead iodide and the DMF in water is 0.5-1.5mol/L.
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