CN206961834U - Thin film transistor (TFT) and dot structure - Google Patents
Thin film transistor (TFT) and dot structure Download PDFInfo
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- CN206961834U CN206961834U CN201720797428.2U CN201720797428U CN206961834U CN 206961834 U CN206961834 U CN 206961834U CN 201720797428 U CN201720797428 U CN 201720797428U CN 206961834 U CN206961834 U CN 206961834U
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Abstract
The utility model provides a kind of thin film transistor (TFT) and dot structure.Thin film transistor (TFT) is configured on substrate and including first electrode, channel layer, grid, gate insulation layer, interlayer dielectric layer and second electrode.First electrode is configured on substrate.Channel layer covers first electrode.Gate configuration is in overlapping with first electrode on channel layer and in the normal direction of substrate.Gate insulation layer is configured between grid and channel layer with grid and the channel layer of being electrically insulated.Interlayer dielectric layer covers grid and the contact hole with exposed vias layer.Second electrode is configured on interlayer dielectric layer and inserts contact hole to contact channel layer.Second electrode in the normal direction with gate overlap.The area of second electrode and gate overlap is substantially equal to the area of first electrode and gate overlap.Thin film transistor (TFT) occupied area of the present utility model is small.
Description
Technical field
It the utility model is related to a kind of electronic component, more particularly to a kind of thin film transistor (TFT) and dot structure.
Background technology
With the development of display science and technology, high-resolution is increasingly becoming one of primary demand.Generally by the size of dot structure
Reduce to meet high-resolution demand.In response to the dot structure of diminution, the area shared by thin film transistor (TFT) must also reduce,
To maintain or be lifted the aperture opening ratio of display panel (aperture ratio).At present, though can be by the way that source electrode and drain configuration be existed
Different layers reach above-mentioned purpose, but have the shortcomings that thin film transistor (TFT) is easily shut off.
The content of the invention
The utility model provides a kind of thin film transistor (TFT), and area occupied is small and electrically good.
The utility model provides a kind of dot structure again, and aperture opening ratio is good.
A kind of thin film transistor (TFT) of the present utility model, is configured on substrate.Thin film transistor (TFT) includes first electrode, passage
Layer, grid, gate insulation layer, interlayer dielectric layer and second electrode.First electrode is configured on substrate.The electricity of channel layer covering first
Pole.Gate configuration is in overlapping with first electrode on channel layer and in the normal direction of substrate.Gate insulation layer be configured at grid and
With grid and the channel layer of being electrically insulated between channel layer.Interlayer dielectric layer covers grid and the contact hole with exposed vias layer.
Second electrode is configured on interlayer dielectric layer and inserts contact hole to contact channel layer.Second electrode in the normal direction with grid
It is overlapping.The area of second electrode and gate overlap is substantially equal to the area of first electrode and gate overlap.
In an embodiment of the present utility model, grid and gate insulation layer in the normal direction can be completely overlapped.
In an embodiment of the present utility model, one in first electrode and second electrode can be source electrode, first electrode
With in second electrode another can be drain electrode.
In an embodiment of the present utility model, in the normal direction, the area of channel layer can be more than the area of grid.
In an embodiment of the present utility model, thin film transistor (TFT), which may also include, to be configured between first electrode and substrate
Light shield layer.
A kind of dot structure of the present utility model, is configured on substrate.Dot structure includes thin film transistor (TFT) and pixel
Electrode.Thin film transistor (TFT) includes first electrode, channel layer, grid, gate insulation layer, interlayer dielectric layer and second electrode.First
Electrode configuration is on substrate.Channel layer covers first electrode.Gate configuration on channel layer and in the normal direction of substrate with
First electrode is overlapping.Gate insulation layer is configured between grid and channel layer with grid and the channel layer of being electrically insulated.Interlayer dielectric layer
Cover grid and the contact hole with exposed vias layer.Second electrode is configured on interlayer dielectric layer and inserts contact hole to contact
Channel layer.Second electrode in the normal direction with gate overlap.The area of second electrode and gate overlap is substantially equal to first
The area of electrode and gate overlap.Pixel electrode is electrically connected with first electrode or second electrode.
In an embodiment of the present utility model, grid and gate insulation layer in the normal direction can be completely overlapped.
In an embodiment of the present utility model, in the normal direction, the area of channel layer can be more than the area of grid.
In an embodiment of the present utility model, pixel electrode can be electrically connected with second electrode, and second electrode and pixel
Electrode can be located at same layer.
In an embodiment of the present utility model, second electrode and pixel electrode can have phase same material.
Based on above-mentioned, in the thin film transistor (TFT) of the embodiment of the utility model one, the area of second electrode and gate overlap
The substantially equal to area of first electrode and gate overlap.Thereby, thin film transistor (TFT) just sweep pattern (forward mode) or
It is counter to sweep under pattern (reverse mode), it can effectively turn off thin film transistor (TFT).
For features described above and advantage of the present utility model can be become apparent, special embodiment below, and coordinate accompanying drawing
It is described in detail below.
Brief description of the drawings
Fig. 1 is the profile of the dot structure comprising thin film transistor (TFT) of the present utility model.
Description of reference numerals：
1000：Dot structure；
100：Substrate；
102：Interlayer dielectric layer；
104：Light shield layer；
106：Insulating barrier；
A1、A2：Area；
CH：Channel layer；
D：Drain electrode；
E1：First electrode；
E2：Second electrode；
G：Grid；
GI：Gate insulation layer；
H：Contact hole；
PE：Pixel electrode；
S：Source electrode；
TFT：Thin film transistor (TFT).
Embodiment
Fig. 1 is the profile of the dot structure comprising thin film transistor (TFT) of the present utility model.It refer to Fig. 1.Dot structure
1000 are configured on substrate 100 and including thin film transistor (TFT) TFT and pixel electrode PE.For optical characteristics, substrate 100 can
For transparent substrates or light tight/reflection substrate.The material of transparent substrates may be selected from glass, quartz, organic polymer, other are appropriate
Material or its combination.The material of light tight/reflection substrate may be selected from conductive material, metal, wafer, ceramics, other suitable materials
Or its combination.For mechanical property, substrate 100 can be rigid substrates or flexible base plate.The material of rigid substrates may be selected from
Glass, quartz, conductive material, metal, wafer, ceramics, other suitable materials or its combination.The material of flexible base plate may be selected from
Ultra-thin glass, organic polymer (such as：Plastics), other suitable materials or its combination.
Thin film transistor (TFT) TFT is configured on substrate 100 and including first electrode E1, channel layer CH, grid G, gate insulation layer
GI, interlayer dielectric layer 102 and second electrode E2.In an embodiment of the present utility model, thin film transistor (TFT) TFT and substrate
Can have extra layer, such as light shield layer 104 between 100.Light shield layer 104 covers substrate 100 to cover from substrate 100 towards thin
The light of film transistor TFT irradiations so that thin film transistor (TFT) TFT electrical stabilization.The material of light shield layer 104 include metal material or
Opaque high polymer material.Metal material is, for example, chromium, aluminium, copper or titanium.Opaque high polymer material be, for example, doped with
The resin (resin) of pigment.It should be noted that if when light shield layer 104 is from metal material, need to be in light shield layer 104 and film
Insulating barrier 106 is set between transistor TFT, to avoid that the problem of short-circuit occurs between light shield layer 104 and thin film transistor (TFT) TFT.
The material of insulating barrier 106 may be selected from inorganic material (such as：Silica, silicon nitride, silicon oxynitride, other suitable materials or on
State the stack layer of at least two kinds materials), organic material, other suitable materials or combinations of the above.
First electrode E1 is configured on substrate 100.Fig. 1 exemplarily represents that first electrode E1 is source S.But this practicality is new
Type is not limited to this, and in other embodiments, first electrode E1 can be drain D.In the case where first electrode E1 is source S,
The some of availability data line (data line) is as source S or can be in other appropriate patterns.For example, by data wire
The conductive area extended to channel layer CH.Source S is usually to use metal material.However, the utility model is not limited to this,
In other embodiment, source S can also use other conductive materials (such as：Alloy, the nitride of metal material, metal material
Oxide, the nitrogen oxides etc. of metal material) or metal material and other conductive materials stack layer.
Channel layer CH covering first electrodes E1.In the present embodiment, channel layer CH is to be covered in the first patterned electricity
On the E1 of pole.Therefore, will not produce due to patterned first electrodes E1 and caused by channel layer CH damage.Channel layer CH can be
Single or multiple lift structure, its material may be selected from non-crystalline silicon, polysilicon, microcrystal silicon, monocrystalline silicon, metal oxide semiconductor material
[such as：Indium gallium zinc (Indium-Gallium-Zinc Oxide, IGZO), zinc oxide (ZnO), tin oxide (SnO), oxidation
Indium zinc (Indium-Zinc Oxide, IZO), gallium oxide zinc (Gallium-Zinc Oxide, GZO), zinc-tin oxide (Zinc-
Tin Oxide, ZTO), tin indium oxide (Indium-Tin Oxide, ITO) etc.], other suitable materials or combinations of the above.
Grid G is configured on channel layer CH.In detail, in the normal direction of substrate 100, channel layer CH area is more than
The area of grid G.In addition, grid G is overlapping with first electrode E1 one end in the normal direction of substrate 100, and grid G and the
One electrode E1 has overlapping area A1 in the normal direction of substrate 100.In the present embodiment, using scan line (scan
Line) part for (not shown) is as grid G.But the utility model is not limited to this, in other embodiments, grid G
Can be in other appropriate patterns, such as：By the abducent conductive area of scan line.Grid G is usually to use metal material, but this
Utility model not limited to this, in other embodiments, grid G can also use other conductive materials (such as：Alloy, metal material
The nitride of material, the oxide of metal material, the nitrogen oxides etc. of metal material) or metal material and other conductive materials
Stack layer.
Gate insulation layer GI is configured between grid G and channel layer CH with grid G and the channel layer CH of being electrically insulated.In this implementation
Example in, can simultaneously patterned gate insulating barrier GI and grid G so that grid G and gate insulation layer GI are in the normal direction of substrate 100
Can be completely overlapped.Accordingly, can avoid repeatedly patterning cause between grid G and gate insulation layer GI produce contraposition skew the problem of and
Technique can be simplified.Gate insulation layer GI material may be selected from inorganic material (such as：Silica, silicon nitride, silicon oxynitride, Qi Tahe
Suitable material or the stack layer of above-mentioned at least two kinds materials), organic material, other suitable materials or combinations of the above.
Interlayer dielectric layer 102 covers grid G and channel layer CH, and has in side of the grid G away from first electrode E1
Exposed vias layer CH contact hole H.In the present embodiment, the interlayer dielectric layer 102 for covering channel layer CH can exempt from channel layer CH
In by damage caused by subsequent pattern second electrode E2.The material of interlayer dielectric layer 102 may be selected from inorganic material (example
Such as：Silica, silicon nitride, silicon oxynitride, the stack layer of other suitable materials or above-mentioned at least two kinds materials), You Jicai
Material, other suitable materials or combinations of the above.
Second electrode E2 is configured on interlayer dielectric layer 102 and inserts contact hole H to contact channel layer CH.Fig. 1 is exemplary
Ground represents that second electrode E2 is drain D.But the utility model is not limited to this, in other embodiments, second electrode E2 can be
Source S.Drain D is usually to use metal material.However, the utility model is not limited to this, and in other embodiments, drain D
Can also use other conductive materials (such as：Alloy, the nitride of metal material, the oxide of metal material, metal material
Nitrogen oxides etc.) or the stack layer of metal material and other conductive materials.In addition, normals of the second electrode E2 in substrate 100
It is overlapping with grid G on direction.In detail, grid G overlapping with first electrode E1 to overlapping with second electrode E2 one end,
And grid G has overlapping area A2 with second electrode E2 in the normal direction of substrate 100.Second electrode E2 and grid G weight
Folded area A2 is substantially equal to the first electrode E1 area A1s overlapping with grid G.Thereby, thin film transistor (TFT) TFT is even in anti-
Sweep under pattern (reverse mode), can also effectively turn off thin film transistor (TFT) TFT.In addition, on interlayer dielectric layer 102
Second electrode E2 can also be exempted in addition to it can be electrically insulated by interlayer dielectric layer 102 and grid G by interlayer dielectric layer 102
Influences of the second electrode E2 to channel layer CH on interlayer dielectric layer 102.
Pixel electrode PE is electrically connected with thin film transistor (TFT) TFT first electrode E1 or second electrode E2.The exemplary earth's surfaces of Fig. 1
Show that pixel electrode PE is electrically connected with thin film transistor (TFT) TFT second electrode E2 (drain D).In an embodiment of the present utility model
In, second electrode E2 (drain D) and pixel electrode PE can be formed in the technique with along with so that second electrode E2 (drain D) and
Pixel electrode PE can be located at same layer and can have phase same material.But the utility model is not limited thereto, in other embodiment
In, dot structure 1000 is optionally included with insulating barrier between pixel electrode PE and second electrode E2 (drain D) (not
Show).Insulating barrier can have a contact hole so that pixel electrode PE can insert the contact hole and with second electrode (drain D)
It is electrically connected with.Pixel electrode PE can be designed as penetration pixel electrode, reflective pixel electrodes according to actual demand or partly penetrate
Semi-reflective pixel electrode.The material of penetration pixel electrode includes metal oxide, such as：Indium tin oxide, the oxidation of indium zinc
Thing, aluminium tin-oxide, aluminium zinc oxide, indium germanium zinc oxide, other suitable oxides or be the heap of above-mentioned at least two
Stack layer.The material of reflective pixel electrodes includes the conductive material with high reflectance, such as：Metal etc..Semi-penetration semi-reflective
The material of formula pixel electrode includes the combination of high reflectance conductive material and high transmission rate conductive material.Particularly, when pixel electricity
When pole PE and second electrode E2 (drain D) material are metal oxide, dot structure 1000 is contributed to be applied to high-resolution
Display panel in.
In summary, in the thin film transistor (TFT) and dot structure of the embodiment of the utility model one, second electrode and grid
Overlapping area is substantially equal to the area of first electrode and gate overlap.Thereby, the face shared by thin film transistor (TFT) can be reduced
Product, improve aperture opening ratio (aperture ratio).Also, thin film transistor (TFT) is just sweeping pattern (forward mode) or counter is sweeping mould
Under formula (reverse mode), it can effectively turn off, it is electrically good.
Finally it should be noted that：Various embodiments above is only to illustrate the technical solution of the utility model, rather than it is limited
System；Although the utility model is described in detail with reference to foregoing embodiments, one of ordinary skill in the art should
Understand：It can still modify to the technical scheme described in foregoing embodiments, either to which part or whole
Technical characteristic carries out equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from this practicality newly
The scope of each embodiment technical scheme of type.
Claims (10)
1. a kind of thin film transistor (TFT), is configured on substrate, the thin film transistor (TFT) is characterised by, including：
First electrode, it is configured on the substrate；
Channel layer, cover the first electrode；
Grid, it is configured on the channel layer and overlapping with the first electrode in the normal direction of the substrate；
Gate insulation layer, it is configured between the grid and the channel layer with the grid and the channel layer of being electrically insulated；
Interlayer dielectric layer, covers the grid, and the interlayer dielectric layer has the contact hole of the exposure channel layer；And
Second electrode, it is configured on the interlayer dielectric layer and inserts the contact hole to contact the channel layer, described second
Electrode in the normal direction with the gate overlap, wherein the area of the second electrode and the gate overlap is equal to institute
State the area of first electrode and the gate overlap.
2. thin film transistor (TFT) according to claim 1, it is characterised in that the grid and the gate insulation layer are in the method
It is completely overlapped on line direction.
3. thin film transistor (TFT) according to claim 1, it is characterised in that in the first electrode and the second electrode
One is source electrode, and another in the first electrode and the second electrode is drain electrode.
4. thin film transistor (TFT) according to claim 1, it is characterised in that in the normal direction, the channel layer
Area is more than the area of the grid.
5. thin film transistor (TFT) according to claim 1, it is characterised in that also include：
Light shield layer, it is configured between the first electrode and the substrate.
6. a kind of dot structure, is configured on substrate, the dot structure is characterised by, including：
Thin film transistor (TFT), the thin film transistor (TFT) include：
First electrode, it is configured on the substrate；
Channel layer, cover the first electrode；
Grid, it is configured on the channel layer and overlapping with the first electrode in the normal direction of the substrate；
Gate insulation layer, it is configured between the grid and the channel layer with the grid and the channel layer of being electrically insulated；
Interlayer dielectric layer, covers the grid, and the interlayer dielectric layer has the contact hole of the exposure channel layer；And
Second electrode, it is configured on the interlayer dielectric layer and inserts the contact hole to contact the channel layer, described second
Electrode in the normal direction with the gate overlap, wherein the area of the second electrode and the gate overlap is equal to institute
State the area of first electrode and the gate overlap；And
Pixel electrode, it is electrically connected with the first electrode or the second electrode.
7. dot structure according to claim 6, it is characterised in that the grid and the gate insulation layer are in the normal
It is completely overlapped on direction.
8. dot structure according to claim 6, it is characterised in that in the normal direction, the face of the channel layer
Area of the product more than the grid.
9. dot structure according to claim 6, it is characterised in that the pixel electrode is electrically connected with second electricity
Pole, and the second electrode and the pixel electrode are located at same layer.
10. dot structure according to claim 9, it is characterised in that the second electrode and the pixel electrode have
Phase same material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720797428.2U CN206961834U (en) | 2017-07-04 | 2017-07-04 | Thin film transistor (TFT) and dot structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720797428.2U CN206961834U (en) | 2017-07-04 | 2017-07-04 | Thin film transistor (TFT) and dot structure |
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| Publication Number | Publication Date |
|---|---|
| CN206961834U true CN206961834U (en) | 2018-02-02 |
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| CN201720797428.2U Expired - Fee Related CN206961834U (en) | 2017-07-04 | 2017-07-04 | Thin film transistor (TFT) and dot structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021031393A1 (en) * | 2019-08-22 | 2021-02-25 | 武汉华星光电技术有限公司 | Manufacturing method of array substrate, and array substrate |
| CN113053892A (en) * | 2020-10-08 | 2021-06-29 | 友达光电股份有限公司 | Vertical logic gate structure |
-
2017
- 2017-07-04 CN CN201720797428.2U patent/CN206961834U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021031393A1 (en) * | 2019-08-22 | 2021-02-25 | 武汉华星光电技术有限公司 | Manufacturing method of array substrate, and array substrate |
| CN113053892A (en) * | 2020-10-08 | 2021-06-29 | 友达光电股份有限公司 | Vertical logic gate structure |
| CN113053892B (en) * | 2020-10-08 | 2023-11-03 | 友达光电股份有限公司 | vertical logic gate structure |
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| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
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Granted publication date: 20180202 Termination date: 20200704 |