CN113053892B - vertical logic gate structure - Google Patents

vertical logic gate structure Download PDF

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Publication number
CN113053892B
CN113053892B CN202110263492.3A CN202110263492A CN113053892B CN 113053892 B CN113053892 B CN 113053892B CN 202110263492 A CN202110263492 A CN 202110263492A CN 113053892 B CN113053892 B CN 113053892B
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electrode
channel layer
gate
layer
disposed
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CN113053892A (en
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郑贸薰
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AU Optronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A vertical logic gate structure includes a substrate, a first channel layer, a gate electrode, a first electrode, a second channel layer, and a third electrode. The first channel layer is disposed on the substrate. The gate electrode is arranged on the first channel layer and overlapped with the first channel layer. The first electrode is disposed on the first channel layer and electrically connected to the first channel layer. The second electrode is arranged on the first channel layer and is electrically connected with the first channel layer, and the grid electrode, the first channel layer, the first electrode and the second electrode form a top grid transistor. The second channel layer is arranged on the gate electrode, the first electrode is electrically connected with the second channel layer, and the second channel layer is partially overlapped with the first channel layer in the vertical direction. The third electrode is arranged on the second channel layer and is electrically connected with the second channel layer, and the grid electrode, the second channel layer, the first electrode and the third electrode form a bottom grid transistor.

Description

Vertical logic gate structure
Technical Field
The invention combines bottom gate transistors and top gate transistors to save vertical logic gate structure of circuit layout area.
Background
Generally, transistors are classified into top-gate transistors and bottom-gate transistors according to gate location. Depending on the actual circuit requirements, it may be desirable to utilize both top gate and bottom gate transistors, but this increases the area required for circuit layout, which is detrimental to high-density logic gate systems (high-density logic system).
In view of the foregoing, the present inventors have conceived and devised a vertical logic gate structure that is intended to address the shortcomings of the prior art and thereby enhance the industrial implementation.
Disclosure of Invention
In view of the above-mentioned problems, it is an object of the present invention to provide a vertical logic gate structure for solving the problems of the prior art.
In view of the above, the present invention provides a vertical logic gate structure including a substrate, a first channel layer, a gate electrode, a first electrode, a second channel layer, and a third electrode. The first channel layer is disposed on the substrate. The gate electrode is arranged on the first channel layer and overlapped with the first channel layer. The first electrode is disposed on the first channel layer and electrically connected to the first channel layer. The second electrode is arranged on the first channel layer and is electrically connected with the first channel layer, and the grid electrode, the first channel layer, the first electrode and the second electrode form a top grid transistor. The second channel layer is arranged on the gate electrode, the first electrode is electrically connected with the second channel layer, and the second channel layer is partially overlapped with the first channel layer in the vertical direction. The third electrode is arranged on the second channel layer and is electrically connected with the second channel layer, and the grid electrode, the second channel layer, the first electrode and the third electrode form a bottom grid transistor.
In an embodiment of the present invention, the present invention further includes a first gate insulating layer, a second gate insulating layer, an interlayer dielectric layer, and a barrier protection layer. The first gate insulating layer is disposed between the first channel layer and the gate electrode. The second gate insulating layer is disposed on the first gate insulating layer. The interlayer dielectric layer is disposed on the second gate insulating layer. The barrier protection layer is disposed on the interlayer dielectric layer.
In an embodiment of the present invention, the gate electrode is disposed between the first gate insulating layer and the second gate insulating layer, the second channel layer, the first electrode, the second electrode and the third electrode are disposed between the interlayer dielectric layer and the barrier protection layer, the first electrode and the third electrode partially overlap the second channel layer, the first electrode is electrically connected to the first channel layer along the first via hole, and the second electrode is electrically connected to the first channel layer along the second via hole.
In an embodiment of the present invention, the gate electrode is connected to the input terminal, the first electrode is connected to the output terminal, and the second electrode and the third electrode are respectively connected to the voltage source.
In an embodiment of the present invention, the gate electrode is disposed between the first gate insulating layer and the second gate insulating layer, the first electrode and the second electrode are disposed between the interlayer dielectric layer and the barrier protection layer, the second channel layer and the third electrode are disposed between the second gate insulating layer and the interlayer dielectric layer, the third electrode partially overlaps the second channel layer, the first electrode is electrically connected to the first channel layer along the first via hole, and the second electrode is electrically connected to the first channel layer along the second via hole.
In an embodiment of the present invention, the gate electrode is connected to the input terminal, the second electrode is connected to the output terminal, and the second electrode and the third electrode are respectively connected to the voltage source.
In an embodiment of the invention, the gate electrode includes a first gate and a second gate, the first gate is disposed between the first gate insulating layer and the second gate insulating layer, the second gate is disposed between the second gate insulating layer and the interlayer dielectric layer, the second electrode and the third electrode form an extension electrode, the second channel layer, the first electrode and the extension electrode are disposed between the interlayer dielectric layer and the barrier protection layer, the first electrode and the extension electrode partially overlap the second channel layer, the first electrode is electrically connected to the first channel layer along the first through hole, and the extension electrode is electrically connected to the first channel layer along the second through hole.
In an embodiment of the present invention, the first gate is connected to the clock signal source, the second gate is connected to the inverted clock signal source, the first electrode is connected to the input terminal, and the second electrode and the third electrode are connected to the output terminal.
In an embodiment of the present invention, the present invention further includes a buffer layer disposed between the substrate and the first channel layer.
In view of the above, the vertical logic gate structure of the present invention combines the bottom gate transistor and the top gate transistor to save the circuit layout area.
Drawings
Fig. 1 is a schematic diagram of an inverter.
Fig. 2 is a block diagram of a first embodiment of a vertical logic gate structure of the present invention.
Fig. 3 is a block diagram of a second embodiment of a vertical logic gate structure of the present invention.
Fig. 4 is a schematic diagram of a transmission gate.
Fig. 5 is a block diagram of a third embodiment of a vertical logic gate structure of the present invention.
Reference numerals illustrate:
BP: barrier protection layer
BL: buffer layer
C1: first channel layer
C2: second channel layer
G: gate electrode
G1: first grid electrode
And G2: second grid electrode
GI1: first gate insulating layer
GI2: second gate insulating layer
ID: interlayer dielectric layer
IN: input terminal
M1: first electrode
M2: second electrode
M3: third electrode
M4: fourth electrode
OUT: an output terminal
S: substrate board
T1: top gate transistor
T2: bottom gate transistor
VDD, VSS: voltage source
Detailed Description
The advantages, features and technical approaches to the present invention will be more readily understood from the following more detailed description of the exemplary embodiments and the accompanying drawings, and the invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather should be construed to provide those skilled in the art with a thorough and complete understanding of the scope of the present invention, and the present invention will only be defined by the appended claims.
It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Accordingly, the terms "first element," "first component," "first region," "first layer," and/or "first portion" discussed below may be termed "second element," "second component," "second region," "second layer," and/or "second portion" without departing from the spirit and scope of the present invention.
Furthermore, the terms "comprises," "comprising," and/or "includes" specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a definition that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to fig. 1 and 2, there is shown a schematic diagram of an inverter and a block diagram of a first embodiment of a vertical logic gate structure according to the present invention. As shown in fig. 1 and 2, the vertical logic gate structure of the present invention has a logic gate as an inverter, and includes a substrate S, a first channel layer C1, a gate electrode G, a first electrode M1, a second electrode M2, a second channel layer C2, and a third electrode M3. The first channel layer C1 is disposed on the substrate S. The gate electrode G is disposed on the first channel layer C1, and the gate electrode G overlaps the first channel layer C1 (i.e., a vertical projection of the gate electrode G on the substrate S overlaps a vertical projection of the first channel layer C1 on the substrate S). The first electrode M1 is disposed on the first channel layer C1 and electrically connected to the first channel layer C1. The second electrode M2 is disposed on the first channel layer C1 and electrically connected to the first channel layer C1, and the gate electrode G, the first channel layer C1, the first electrode M1 and the second electrode M2 form a top gate transistor T1. The second channel layer C2 is disposed on the gate electrode G, the first electrode M1 is electrically connected to the second channel layer C2, and the second channel layer C2 is partially overlapped with the first channel layer C1 in the vertical direction (i.e., the vertical projection of the second channel layer C2 on the substrate S is partially overlapped with the vertical projection of the first channel layer C1 on the substrate S). The third electrode M3 is disposed on the second channel layer C2 and is electrically connected to the second channel layer C2, and the gate electrode G, the second channel layer C2, the first electrode M1 and the third electrode M3 form a bottom gate transistor T2.
In this embodiment, the vertical logic gate structure of the present invention further includes a buffer layer BL, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer dielectric layer ID, and a barrier protection layer BP. The first gate insulating layer GI1 is disposed between the first channel layer C1 and the gate electrode G, the buffer layer BL is disposed between the substrate S and the first channel layer C1, and the buffer layer BL is also disposed between the substrate S and the first gate insulating layer GI 1. The second gate insulating layer GI2 is disposed on the first gate insulating layer GI 1. The interlayer dielectric layer ID is disposed on the second gate insulating layer GI 2. The barrier protection layer BP is disposed on the interlayer dielectric layer ID, and covers the first electrode M1, the second electrode M2, the second channel layer C2 and the third electrode M3.
The gate electrode G is disposed between the first gate insulating layer GI1 and the second gate insulating layer GI2, and is also located at a junction between the first gate insulating layer GI1 and the second gate insulating layer GI 2. The second channel layer C2, the first electrode M1, the second electrode M2 and the third electrode M3 are disposed between the interlayer dielectric layer ID and the barrier protection layer BP, the second channel layer C2, the first electrode M1, the second electrode M2 and the third electrode M3 are also located at the junction of the barrier protection layer BP and the interlayer dielectric layer ID, and the first electrode M1 and the third electrode M3 are partially overlapped on the second channel layer C2. The first electrode M1 is electrically connected to the first channel layer C1 along the first through hole, and the second electrode M2 is electrically connected to the first channel layer C1 along the second through hole; that is, the first electrode M1 extends from the first channel layer C1 in the first gate insulating layer GI1 to the interface between the barrier protection layer BP and the interlayer dielectric layer ID, and the second electrode M2 extends from the first channel layer C1 in the first gate insulating layer GI1 to the interface between the barrier protection layer BP and the interlayer dielectric layer ID.
IN one embodiment, the gate electrode G is connected to the input terminal IN, the first electrode M1 is connected to the output terminal OUT, the second electrode M2 is connected to the voltage source VDD, and the third electrode M3 is connected to the voltage source VSS. IN another embodiment, the gate electrode G is connected to the input terminal IN, the first electrode M1 is connected to the output terminal OUT, the second electrode M2 is connected to the voltage source VSS, and the third electrode M3 is connected to the voltage source VDD.
Note that, top gate transistors T1 andthe bottom gate transistor T2 is, for example, p-type or n-type, and the transistor may include a thin film transistor (thin film transistor, TFT) and a vertical transistor (vertical TFT), but may be any other suitable transistor, and is not limited to the scope of the present invention. The substrate S may include, for example, a glass substrate, a quartz substrate, a substrate formed of a polymer resin, or a flexible substrate formed of a flexible material such as polyimide; the material of the polymer resin may include Polyethersulfone (PES), polyacrylate (PA), polyarylate (PAT), polyetherimide (PEI), polyethylene 2,6 naphthalate (polyethylene naphthalate, PEN), polyethylene terephthalate (polyethylene terephthalate, PET), polyphenylene sulfide (polyphenylene sulfide, PPS), polyarylate (polyallylate), polyimide (PI), polycarbonate (PC), cellulose triacetate (cellulose triacetate, CAT or TAC), cellulose acetate propionate (cellulose acetate propionate, CAP), and combinations thereof. The materials of the buffer layer BL, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer dielectric layer ID and the barrier protection layer BP may include silicon oxide (SiO) x ) Silicon nitride (SiN) x ) Silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide (SiOC) or aluminum oxide (AlO) x ) And combinations thereof. The materials of the gate electrode G, the first electrode M1, the second electrode M2, and the third electrode M3 may include at least one of indium (In), tin (Sn), aluminum (Al), gold (Au), platinum (Pt), indium (In), zinc (Zn), germanium (Ge), silver (Ag), lead (Pb), palladium (Pd), copper (Cu), beryllium (AuBe), beryllium (BeGe), nickel (Ni), lead stannate (PbSn), chromium (Cr), zinc (AuZn), titanium (Ti), tungsten (W), and titanium Tungsten (TiW), for example. The top gate transistor T1 and the bottom gate transistor T2 may be, for example, a transistor with polysilicon as a main material, or the top gate transistor T1 and the bottom gate transistor T2 may be a transistor with a transparent conductive material as a main material, and the transparent conductive material may include Indium Tin Oxide (ITO), zinc oxide (ZnO), aluminum gallium indium tin oxide (algalnsno), aluminum Zinc Oxide (AZO), tin oxide (SnO 2 ) Indium oxide (In) 2 O 3 ) Zinc tin oxide (SnZnO) or Graphene (Graphene).The foregoing materials are only examples, and of course, other preferred materials are also possible and are not limited to the scope of the present invention.
Referring to fig. 1 and 3, a schematic diagram of an inverter and a structure diagram of a second embodiment of a vertical logic gate structure of the present invention are shown. As shown in fig. 1 and 3, the vertical logic gate structure of the present invention is an inverter, and includes a substrate S, a first channel layer C1, a gate electrode G, a first electrode M1, a second electrode M2, a second channel layer C2, a third electrode M3, a fourth electrode M4, a buffer layer BL, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer dielectric layer ID, and a barrier protection layer BP, and the configuration relationships are similar to those of the first embodiment, and the description of the similarities is not repeated here, but the second embodiment of the present invention is different from the first embodiment in that: the first electrode M1 and the second electrode M2 are disposed between the interlayer dielectric layer ID and the barrier protection layer BP, the second channel layer C2, the third electrode M3 and the fourth electrode M4 are disposed between the second gate insulating layer GI2 and the interlayer dielectric layer ID, the third electrode M3 and the fourth electrode M4 are partially overlapped on the second channel layer C2, and the third electrode M3 and the fourth electrode M4 are disposed on the periphery of the second channel layer C2. The first electrode M1 is electrically connected to the first channel layer C1 along the first through hole, and the second electrode M2 is electrically connected to the first channel layer C1 along the second through hole; that is, the first electrode M1 extends from the first channel layer C1 in the first gate insulating layer GI1 to the interface between the barrier protection layer BP and the interlayer dielectric layer ID, and the second electrode M2 extends from the first channel layer C1 in the first gate insulating layer GI1 to the interface between the barrier protection layer BP and the interlayer dielectric layer ID.
In the second embodiment, the third electrode M3 and the fourth electrode M4 are the same layer as the second channel layer C2, the third electrode M3 and the fourth electrode M4 are located at opposite sides with respect to the second channel layer C2, the third electrode M3, the fourth electrode M4, the second channel layer C2 and the gate electrode G form the bottom gate transistor T2, and the third electrode M3 and the fourth electrode M4 are the drain and the source of the bottom gate transistor T2.
IN one embodiment, the gate electrode G is connected to the input terminal IN, the first electrode M1 is connected to the output terminal OUT, the second electrode M2 is connected to the voltage source VDD, and the third electrode M3 is connected to the voltage source VSS. IN another embodiment, the gate electrode G is connected to the input terminal IN, the first electrode M1 is connected to the output terminal OUT, the second electrode M2 is connected to the voltage source VSS, and the third electrode M3 is connected to the voltage source VDD.
Referring to fig. 4 and 5, schematic diagrams of transmission gates and a third embodiment of the vertical logic gate structure of the present invention are shown. As shown in fig. 4 and 5, the vertical logic gate structure of the present invention is a transmitter, and includes a substrate S, a first channel layer C1, a first electrode M1, an extension electrode M5, a second channel layer C2, a buffer layer BL, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer dielectric layer ID and a barrier protection layer BP, and the configuration relationships are similar to those of the first embodiment, and the description of the similarities is not repeated herein, but the third embodiment of the present invention is different from the first embodiment in that: the gate electrode G includes a first gate G1 and a second gate G2, the first gate G1 is disposed between the first gate insulating layer GI1 and the second gate insulating layer GI2, the first gate G1 is also disposed at a junction between the first gate insulating layer GI1 and the second gate insulating layer GI2, the second gate G2 is disposed between the second gate insulating layer GI2 and the interlayer dielectric layer ID, and the second gate G2 is also disposed at a junction between the second gate insulating layer GI2 and the interlayer dielectric layer ID. The second electrode M2 and the third electrode M3 form an extension electrode M5, the second channel layer C2, the first electrode M1 and the extension electrode M5 are disposed between the interlayer dielectric layer ID and the barrier protection layer BP, the first electrode M1 and the extension electrode M5 are partially overlapped on the second channel layer C2, and the first electrode M1 and the extension electrode M5 are also located at the periphery of the second channel layer C2. The first electrode M1 is electrically connected to the first channel layer C1 along the first through hole, and the extension electrode M5 is electrically connected to the first channel layer C1 along the second through hole; that is, the first electrode M1 extends from the first channel layer C1 in the first gate insulating layer GI1 to the interface between the barrier protection layer BP and the interlayer dielectric layer ID, and the extension electrode M5 extends from the first channel layer C1 in the first gate insulating layer GI1 to the interface between the barrier protection layer BP and the interlayer dielectric layer ID.
It should be noted that the formation of the extension electrode M5 may be directly performed without forming the second electrode M2 and the third electrode M3, and the formation of the extension electrode M5 may be similar to the formation of the second electrode M2 of the second embodiment, but the extension electrode M5 directly extends to contact the second channel layer C2.
IN an embodiment, the first gate G1 is connected to the clock signal source CLK1, the second gate G2 is connected to the inverted clock signal source CLK2, the first electrode M1 is connected to the input terminal IN, and the second electrode M2 and the third electrode M3 are connected to the output terminal OUT.
In view of the above, the vertical logic gate structure of the present invention combines the bottom gate transistor T2 and the top gate transistor T1 to save the circuit layout area.
The foregoing is by way of example only and is not intended as limiting. Any equivalent modifications or alterations to the present invention without departing from the spirit and scope of the present invention are intended to be included in the claims.

Claims (6)

1. A vertical logic gate structure, comprising:
a substrate;
a first channel layer disposed on the substrate;
a gate electrode disposed on the first channel layer, the gate electrode overlapping the first channel layer;
the first electrode is arranged on the first channel layer and is electrically connected with the first channel layer;
the second electrode is arranged on the first channel layer and is electrically connected with the first channel layer, and the grid electrode, the first channel layer, the first electrode and the second electrode form a top grid transistor;
the second channel layer is arranged on the gate electrode, the first electrode is electrically connected with the second channel layer, and the second channel layer is partially overlapped with the first channel layer in a vertical direction; and
a third electrode disposed on the second channel layer and electrically connected to the second channel layer, wherein the gate electrode, the second channel layer, the first electrode and the third electrode form a bottom gate transistor,
further comprising:
a first gate insulating layer disposed between the first channel layer and the gate electrode;
a second gate insulating layer disposed on the first gate insulating layer;
an interlayer dielectric layer disposed on the second gate insulating layer; and
a barrier protection layer disposed on the interlayer dielectric layer,
the gate electrode is disposed between the first gate insulating layer and the second gate insulating layer, the second channel layer, the first electrode, the second electrode and the third electrode are disposed between the interlayer dielectric layer and the barrier protection layer, the first electrode and the third electrode partially overlap the second channel layer, the first electrode is electrically connected to the first channel layer along a first via hole, and the second electrode is electrically connected to the first channel layer along a second via hole.
2. The vertical logic gate structure of claim 1, wherein the gate electrode is connected to an input terminal, the first electrode is connected to an output terminal, and the second electrode and the third electrode are respectively connected to a voltage source.
3. The vertical logic gate structure of claim 1, wherein the second channel layer and the third electrode are disposed between the second gate insulating layer and the interlayer dielectric layer.
4. The vertical logic gate structure of claim 1, wherein the gate electrode comprises a first gate and a second gate, the first gate is disposed between the first gate insulating layer and the second gate insulating layer, the second gate is disposed between the second gate insulating layer and the interlayer dielectric layer, the second electrode and the third electrode form an extension electrode, the extension electrode is disposed between the interlayer dielectric layer and the barrier protection layer, the extension electrode partially overlaps the second channel layer, and the extension electrode is electrically connected to the first channel layer along a second via.
5. The vertical logic gate structure of claim 4, wherein the first gate is connected to a clock signal source, the second gate is connected to a reverse clock signal source, the first electrode is connected to an input terminal, and the second electrode and the third electrode are connected to an output terminal.
6. The vertical logic gate structure of claim 1, further comprising a buffer layer disposed between the substrate and the first channel layer.
CN202110263492.3A 2020-10-08 2021-03-11 vertical logic gate structure Active CN113053892B (en)

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CN103165575A (en) * 2011-12-13 2013-06-19 格罗方德半导体公司 Semiconductor device with transistor local interconnects
CN106653852A (en) * 2015-10-30 2017-05-10 台湾积体电路制造股份有限公司 Semiconductor device
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CN108020968A (en) * 2016-10-31 2018-05-11 乐金显示有限公司 Liquid crystal display
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