TWI745115B - Vertical logic gate structure - Google Patents

Vertical logic gate structure Download PDF

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TWI745115B
TWI745115B TW109134974A TW109134974A TWI745115B TW I745115 B TWI745115 B TW I745115B TW 109134974 A TW109134974 A TW 109134974A TW 109134974 A TW109134974 A TW 109134974A TW I745115 B TWI745115 B TW I745115B
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electrode
gate
channel layer
layer
disposed
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TW109134974A
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TW202215639A (en
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鄭貿薰
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友達光電股份有限公司
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Priority to CN202110263492.3A priority patent/CN113053892B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Abstract

A vertical logic gate structure includes a substrate, a first channel layer, a gate electrode, a first electrode, a second channel layer and a third electrode. The gate electrode is disposed on the first channel layer and overlaps the first channel layer. The first electrode is disposed on the first channel layer and is electrically connected to the first channel layer. The second electrode is disposed on the first channel layer and is electrically connected to the first channel layer. The gate electrode, the first channel layer, the first electrode and the second electrode forms a top-gate transistor. The second channel layer is disposed on the gate electrode. The first electrode is electrically connected to the second channel layer. The second channel layer overlaps the first channel layer on the vertical direction. The third electrode is disposed on the second channel layer and is electrically connected to the second channel layer. The gate electrode, the second channel layer, the first electrode and the third electrode forms a bottom-gate transistor.

Description

垂直邏輯閘結構Vertical logic gate structure

本發明結合底閘極電晶體和頂閘極電晶體來節省電路佈局面積之垂直邏輯閘結構。The present invention combines the bottom gate transistor and the top gate transistor to save a vertical logic gate structure of the circuit layout area.

一般而言，電晶體根據閘極位置分為頂閘極電晶體和底閘極電晶體。根據實際電路所需，可能需同時利用頂閘極電晶體和底閘極電晶體，但其提高電路佈局所需面積，不利於高密度邏輯閘系統(high-density logic system)。Generally speaking, transistors are divided into top gate transistors and bottom gate transistors according to the gate position. According to actual circuit requirements, it may be necessary to use both the top gate transistor and the bottom gate transistor, but this increases the area required for the circuit layout and is not conducive to high-density logic systems.

綜觀前所述，本發明之發明者思索並設計一種垂直邏輯閘結構，以期針對習知技術之缺失加以改善，進而增進產業上之實施利用。In summary, the inventor of the present invention considered and designed a vertical logic gate structure in order to improve the lack of conventional technology, thereby enhancing the industrial application.

有鑑於上述習知之問題，本發明的目的在於提供一種垂直邏輯閘結構，用以解決習知技術中所面臨之問題。In view of the above-mentioned conventional problems, the purpose of the present invention is to provide a vertical logic gate structure to solve the problems faced by the conventional technology.

基於上述目的，本發明提供一種垂直邏輯閘結構，其包括基板、第一通道層、閘極電極、第一電極、第二電極、第二通道層以及第三電極。第一通道層設置於基板上。閘極電極設置於第一通道層上，閘極電極重疊於第一通道層。第一電極設置於第一通道層上，且電性連接第一通道層。第二電極設置於第一通道層上，且電性連接第一通道層，閘極電極、第一通道層、第一電極及第二電極形成頂閘極電晶體。第二通道層設置於閘極電極上，第一電極電性連接第二通道層，且第二通道層於垂直方向上部分重疊於第一通道層。第三電極設置於第二通道層上，且電性連接第二通道層，閘極電極、第二通道層、第一電極及第三電極形成底閘極電晶體。Based on the above objective, the present invention provides a vertical logic gate structure, which includes a substrate, a first channel layer, a gate electrode, a first electrode, a second electrode, a second channel layer, and a third electrode. The first channel layer is arranged on the substrate. The gate electrode is arranged on the first channel layer, and the gate electrode overlaps the first channel layer. The first electrode is disposed on the first channel layer and is electrically connected to the first channel layer. The second electrode is arranged on the first channel layer and is electrically connected to the first channel layer. The gate electrode, the first channel layer, the first electrode and the second electrode form a top gate transistor. The second channel layer is disposed on the gate electrode, the first electrode is electrically connected to the second channel layer, and the second channel layer partially overlaps the first channel layer in the vertical direction. The third electrode is arranged on the second channel layer and is electrically connected to the second channel layer. The gate electrode, the second channel layer, the first electrode and the third electrode form a bottom gate transistor.

在本發明的實施例中，本發明進一步包括第一閘極絕緣層、第二閘極絕緣層、層間介電層及屏障保護層。第一閘極絕緣層設置在第一通道層與閘極電極之間。第二閘極絕緣層設置於第一閘極絕緣層上。層間介電層設置於第二閘極絕緣層上。屏障保護層設置於層間介電層上。In the embodiment of the present invention, the present invention further includes a first gate insulating layer, a second gate insulating layer, an interlayer dielectric layer, and a barrier protection layer. The first gate insulating layer is disposed between the first channel layer and the gate electrode. The second gate insulating layer is disposed on the first gate insulating layer. The interlayer dielectric layer is arranged on the second gate insulating layer. The barrier protection layer is arranged on the interlayer dielectric layer.

在本發明的實施例中，閘極電極設置在第一閘極絕緣層與第二閘極絕緣層之間，第二通道層、第一電極、第二電極及第三電極設置在層間介電層與屏障保護層之間，第一電極與第三電極部分重疊於第二通道層，第一電極沿著第一通孔電性連接第一通道層，第二電極沿著第二通孔電性連接第一通道層。In the embodiment of the present invention, the gate electrode is arranged between the first gate insulating layer and the second gate insulating layer, and the second channel layer, the first electrode, the second electrode and the third electrode are arranged on the interlayer dielectric Between the layer and the barrier protection layer, the first electrode and the third electrode partially overlap the second channel layer, the first electrode is electrically connected to the first channel layer along the first through hole, and the second electrode is electrically connected along the second through hole. Sexual connection to the first channel layer.

在本發明的實施例中，閘極電極連接於輸入端，第一電極連接於輸出端，第二電極及第三電極分別連接於電壓源。In the embodiment of the present invention, the gate electrode is connected to the input terminal, the first electrode is connected to the output terminal, and the second electrode and the third electrode are respectively connected to a voltage source.

在本發明的實施例中，閘極電極設置在第一閘極絕緣層與第二閘極絕緣層之間，第一電極及第二電極設置在層間介電層與屏障保護層之間，第二通道層及第三電極設置在第二閘極絕緣層與層間介電層之間，第三電極部分重疊於第二通道層，第一電極沿著第一通孔電性連接第一通道層，第二電極沿著第二通孔電性連接第一通道層。In the embodiment of the present invention, the gate electrode is arranged between the first gate insulating layer and the second gate insulating layer, the first electrode and the second electrode are arranged between the interlayer dielectric layer and the barrier protection layer, and the first The two channel layer and the third electrode are arranged between the second gate insulating layer and the interlayer dielectric layer, the third electrode partially overlaps the second channel layer, and the first electrode is electrically connected to the first channel layer along the first through hole , The second electrode is electrically connected to the first channel layer along the second through hole.

在本發明的實施例中，閘極電極連接於輸入端，第二電極連接於輸出端，第二電極及第三電極分別連接於電壓源。In the embodiment of the present invention, the gate electrode is connected to the input terminal, the second electrode is connected to the output terminal, and the second electrode and the third electrode are respectively connected to a voltage source.

在本發明的實施例中，閘極電極包含第一閘極及第二閘極，第一閘極設置在第一閘極絕緣層與第二閘極絕緣層之間，第二閘極設置在第二閘極絕緣層與層間介電層之間，第二電極和第三電極形成延伸電極，第二通道層、第一電極及延伸電極設置在層間介電層與屏障保護層之間，第一電極與延伸電極部分重疊於第二通道層，第一電極沿著第一通孔電性連接第一通道層，延伸電極沿著第二通孔電性連接第一通道層。In an embodiment of the present invention, the gate electrode includes a first gate and a second gate, the first gate is arranged between the first gate insulating layer and the second gate insulating layer, and the second gate is arranged Between the second gate insulating layer and the interlayer dielectric layer, the second electrode and the third electrode form an extension electrode. The second channel layer, the first electrode and the extension electrode are arranged between the interlayer dielectric layer and the barrier protection layer. An electrode and the extension electrode partially overlap the second channel layer, the first electrode is electrically connected to the first channel layer along the first through hole, and the extension electrode is electrically connected to the first channel layer along the second through hole.

在本發明的實施例中，第一閘極連接於時脈訊號源，第二閘極連接於反向時脈訊號源，第一電極連接於輸入端，第二電極及第三電極連接於輸出端。In the embodiment of the present invention, the first gate is connected to the clock signal source, the second gate is connected to the reverse clock signal source, the first electrode is connected to the input terminal, and the second electrode and the third electrode are connected to the output end.

在本發明的實施例中，本發明進一步包含緩衝層，緩衝層設置在基板與第一通道層之間。In an embodiment of the present invention, the present invention further includes a buffer layer, and the buffer layer is disposed between the substrate and the first channel layer.

承上所述，本發明之垂直邏輯閘結構，結合底閘極電晶體和頂閘極電晶體，來節省電路佈局面積。In summary, the vertical logic gate structure of the present invention combines the bottom gate transistor and the top gate transistor to save the circuit layout area.

本發明之優點、特徵以及達到之技術方法將參照例示性實施例及所附圖式進行更詳細地描述而更容易理解，且本發明可以不同形式來實現，故不應被理解僅限於此處所陳述的實施例，相反地，對所屬技術領域具有通常知識者而言，所提供的實施例將使本揭露更加透徹與全面且完整地傳達本發明的範疇，且本發明將僅為所附加的申請專利範圍所定義。The advantages, features, and technical methods of the present invention will be described in more detail with reference to exemplary embodiments and the accompanying drawings to make it easier to understand, and the present invention can be implemented in different forms, so it should not be understood to be limited to what is here. The stated embodiments, on the contrary, for those with ordinary knowledge in the technical field, the provided embodiments will make this disclosure more thorough, comprehensive and complete to convey the scope of the present invention, and the present invention will only be additional Defined by the scope of the patent application.

應當理解的是，儘管術語「第一」、「第二」等在本發明中可用於描述各種元件、部件、區域、層及/或部分，但是這些元件、部件、區域、層及/或部分不應受這些術語的限制。這些術語僅用於將一個元件、部件、區域、層及/或部分與另一個元件、部件、區域、層及/或部分區分開。因此，下文討論的「第一元件」、「第一部件」、「第一區域」、「第一層」及/或「第一部分」可以被稱為「第二元件」、「第二部件」、「第二區域」、「第二層」及/或「第二部分」，而不悖離本發明的精神和教示。It should be understood that although the terms "first", "second", etc. may be used in the present invention to describe various elements, components, regions, layers and/or parts, these elements, components, regions, layers and/or parts Should not be restricted by these terms. These terms are only used to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. Therefore, the "first element", "first part", "first area", "first layer" and/or "first part" discussed below can be referred to as "second element", "second part" , "Second Area", "Second Layer" and/or "Second Part" without departing from the spirit and teachings of the present invention.

另外，術語「包括」及/或「包含」指所述特徵、區域、整體、步驟、操作、元件及/或部件的存在，但不排除一個或多個其他特徵、區域、整體、步驟、操作、元件、部件及/或其組合的存在或添加。In addition, the terms "including" and/or "including" refer to the existence of the features, regions, wholes, steps, operations, elements, and/or components, but do not exclude one or more other features, regions, wholes, steps, operations , The presence or addition of elements, components, and/or combinations thereof.

除非另有定義，本發明所使用的所有術語(包括技術和科學術語)具有與本發明所屬技術領域的普通技術人員通常理解的相同含義。將進一步理解的是，諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的定義，並且將不被解釋為理想化或過度正式的意義，除非本文中明確地這樣定義。Unless otherwise defined, all terms (including technical and scientific terms) used in the present invention have the same meanings as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having definitions consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or overly formal Unless explicitly defined as such in this article.

請參閱第1圖和第2圖，其為反向器之示意圖和本發明之垂直邏輯閘結構之第一實施例之結構圖。如第1圖和第2圖所示，本發明之垂直邏輯閘結構，其對應的邏輯閘為反向器，並包括基板S、第一通道層C1、閘極電極G、第一電極M1、第二電極M2、第二通道層C2以及第三電極M3。第一通道層C1設置於基板S上。閘極電極G設置於第一通道層C1上，閘極電極G重疊於第一通道層C1(亦即，閘極電極G於基板S上之垂直投影重疊於第一通道層C1於基板S上之垂直投影)。第一電極M1設置於第一通道層C1上，且電性連接第一通道層C1。第二電極M2設置於第一通道層C1上且電性連接第一通道層C1，閘極電極G、第一通道層C1、第一電極M1及第二電極M2形成頂閘極電晶體T1。第二通道層C2設置於閘極電極G上，第一電極M1電性連接第二通道層C2，且第二通道層C2於垂直方向上部分重疊於第一通道層C1(亦即，第二通道層C2於基板S上之垂直投影部分重疊於第一通道層C1於基板S上之垂直投影)。第三電極M3設置於第二通道層C2上，且電性連接第二通道層C2，閘極電極G、第二通道層C2、第一電極M1及第三電極M3形成底閘極電晶體T2。Please refer to Figures 1 and 2, which are schematic diagrams of inverters and the structural diagram of the first embodiment of the vertical logic gate structure of the present invention. As shown in Figures 1 and 2, the vertical logic gate structure of the present invention corresponds to an inverter and includes a substrate S, a first channel layer C1, a gate electrode G, a first electrode M1, The second electrode M2, the second channel layer C2, and the third electrode M3. The first channel layer C1 is disposed on the substrate S. The gate electrode G is disposed on the first channel layer C1, and the gate electrode G overlaps the first channel layer C1 (that is, the vertical projection of the gate electrode G on the substrate S overlaps the first channel layer C1 on the substrate S The vertical projection). The first electrode M1 is disposed on the first channel layer C1 and is electrically connected to the first channel layer C1. The second electrode M2 is disposed on the first channel layer C1 and is electrically connected to the first channel layer C1. The gate electrode G, the first channel layer C1, the first electrode M1, and the second electrode M2 form a top gate transistor T1. The second channel layer C2 is disposed on the gate electrode G, the first electrode M1 is electrically connected to the second channel layer C2, and the second channel layer C2 partially overlaps the first channel layer C1 (that is, the second The vertical projection of the channel layer C2 on the substrate S partially overlaps the vertical projection of the first channel layer C1 on the substrate S). The third electrode M3 is disposed on the second channel layer C2 and is electrically connected to the second channel layer C2. The gate electrode G, the second channel layer C2, the first electrode M1, and the third electrode M3 form a bottom gate transistor T2 .

於本實施例中，本發明之垂直邏輯閘結構更包括緩衝層BL、第一閘極絕緣層GI1、第二閘極絕緣層GI2、層間介電層ID及屏障保護層BP。第一閘極絕緣層GI1設置在第一通道層C1與閘極電極G之間，緩衝層BL設置於基板S和第一通道層C1之間，緩衝層BL也位於基板S和第一閘極絕緣層GI1之間。第二閘極絕緣層GI2設置於第一閘極絕緣層GI1上。層間介電層ID設置於第二閘極絕緣層GI2上。屏障保護層BP設置於層間介電層ID上，屏障保護層BP覆蓋第一電極M1、第二電極M2、第二通道層C2以及第三電極M3。In this embodiment, the vertical logic gate structure of the present invention further includes a buffer layer BL, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer dielectric layer ID, and a barrier protection layer BP. The first gate insulating layer GI1 is disposed between the first channel layer C1 and the gate electrode G, the buffer layer BL is disposed between the substrate S and the first channel layer C1, and the buffer layer BL is also located between the substrate S and the first gate electrode. Between the insulating layers GI1. The second gate insulating layer GI2 is disposed on the first gate insulating layer GI1. The interlayer dielectric layer ID is disposed on the second gate insulating layer GI2. The barrier protection layer BP is disposed on the interlayer dielectric layer ID, and the barrier protection layer BP covers the first electrode M1, the second electrode M2, the second channel layer C2, and the third electrode M3.

其中，閘極電極G設置於第一閘極絕緣層GI1與第二閘極絕緣層GI2之間，閘極電極G也位於第一閘極絕緣層GI1和第二閘極絕緣層GI2的交界處。第二通道層C2、第一電極M1、第二電極M2及第三電極M3設置在層間介電層ID與屏障保護層BP之間，第二通道層C2、第一電極M1、第二電極M2及第三電極M3也位於屏障保護層BP和層間介電層ID的交界處，第一電極M1與第三電極M3部分重疊於第二通道層C2。第一電極M1沿著第一通孔電性連接第一通道層C1，第二電極M2沿著第二通孔電性連接第一通道層C1；亦即，第一電極M1從第一閘極絕緣層GI1中的第一通道層C1延伸至屏障保護層BP和層間介電層ID的交界，第二電極M2從第一閘極絕緣層GI1中的第一通道層C1延伸至屏障保護層BP 和層間介電層ID的交界。Wherein, the gate electrode G is disposed between the first gate insulating layer GI1 and the second gate insulating layer GI2, and the gate electrode G is also located at the junction of the first gate insulating layer GI1 and the second gate insulating layer GI2 . The second channel layer C2, the first electrode M1, the second electrode M2, and the third electrode M3 are disposed between the interlayer dielectric layer ID and the barrier protection layer BP, the second channel layer C2, the first electrode M1, and the second electrode M2 The third electrode M3 and the third electrode M3 are also located at the junction of the barrier protection layer BP and the interlayer dielectric layer ID. The first electrode M1 and the third electrode M3 partially overlap the second channel layer C2. The first electrode M1 is electrically connected to the first channel layer C1 along the first through hole, and the second electrode M2 is electrically connected to the first channel layer C1 along the second through hole; The first channel layer C1 in the insulating layer GI1 extends to the boundary between the barrier protective layer BP and the interlayer dielectric layer ID, and the second electrode M2 extends from the first channel layer C1 in the first gate insulating layer GI1 to the barrier protective layer BP The interface with the ID of the interlayer dielectric layer.

於一實施例中，閘極電極G連接於輸入端IN，第一電極M1連接於輸出端OUT，第二電極M2連接於電壓源VDD，第三電極M3連接於電壓源VSS。於另一實施例中，閘極電極G連接於輸入端IN，第一電極M1連接於輸出端OUT，第二電極M2連接於電壓源VSS，第三電極M3連接於電壓源VDD。In one embodiment, the gate electrode G is connected to the input terminal IN, the first electrode M1 is connected to the output terminal OUT, the second electrode M2 is connected to the voltage source VDD, and the third electrode M3 is connected to the voltage source VSS. In another embodiment, the gate electrode G is connected to the input terminal IN, the first electrode M1 is connected to the output terminal OUT, the second electrode M2 is connected to the voltage source VSS, and the third electrode M3 is connected to the voltage source VDD.

需說明的是，頂閘極電晶體T1和底閘極電晶體T2例如為p型或n型，電晶體可包括薄膜電晶體(thin film transistor, TFT)和立體式的電晶體（vertical TFT），當然也可為其他合適的電晶體，並未侷限於本發明所列舉的範圍。基板S例如可包括玻璃基板、石英基板、聚合物樹脂所形成的基板或例如聚亞醯胺之可撓性材料形成的可撓性基板；聚合物樹脂的材料可包括聚醚碸(polyethersulfone，PES)、聚丙烯酸酯(polyacrylate，PA)、聚芳酯(polyarylate，PAT)、聚醚醯亞胺(polyetherimide，PEI)、聚2,6萘二甲酸乙二酯(polyethylene naphthalate，PEN)、聚對酞酸乙二酯(polyethylene terephthalate，PET)、聚苯硫(polyphenylene sulfide，PPS)、聚芳基酸酯(polyallylate)、聚亞醯胺(polyimide，PI)、聚碳酸酯(polycarbonate，PC)、纖維素三乙酸酯(cellulose triacetate，CAT或TAC)、醋酸丙酸纖維素(cellulose acetate propionate，CAP)、以及其組合物。緩衝層BL、第一閘極絕緣層GI1、第二閘極絕緣層GI2、層間介電層ID及屏障保護層BP的材料例如可包括氧化矽(SiO x)、氮化矽(SiN x)、氮氧化矽(SiON)、碳氮化矽(SiCN)、碳氧化矽(SiOC)或氧化鋁(AlO x)及其組合物。閘極電極G、第一電極M1、第二電極M2以及第三電極M3的材料例如可包括銦(In)、錫(Sn)、鋁(Al)、金(Au)、鉑(Pt)、銦(In)、鋅(Zn)、鍺(Ge)、銀(Ag)、鉛(Pb)、鈀(Pd)、銅(Cu)、鈹化金(AuBe)、鈹化鍺(BeGe)、鎳(Ni)、錫化鉛(PbSn)、鉻(Cr)、鋅化金(AuZn)、鈦(Ti)、鎢(W)以及鎢化鈦(TiW)等所組成材料中至少一種。頂閘極電晶體T1和底閘極電晶體T2例如可為多晶矽為主要材料的電晶體，或者，頂閘極電晶體T1和底閘極電晶體T2可以透明導電材料為主要材料的電晶體，透明導電材料可包括氧化銦錫(ITO)、氧化鋅(ZnO)、氧化鋁鎵銦錫(AlGaInSnO)、氧化鋁鋅(AZO)、氧化錫(SnO 2)、氧化銦(In 2O 3)、氧化鋅錫(SnZnO)或石墨烯(Graphene)。前述的材料僅為列舉，當然也可為其他較佳的材料，而未侷限於本發明所列舉的範圍。 It should be noted that the top gate transistor T1 and the bottom gate transistor T2 are, for example, p-type or n-type, and the transistors may include thin film transistors (TFT) and three-dimensional transistors (vertical TFT) Of course, it can also be other suitable transistors, and is not limited to the scope of the present invention. The substrate S may include, for example, a glass substrate, a quartz substrate, a substrate formed of a polymer resin, or a flexible substrate formed of a flexible material such as polyimide; the material of the polymer resin may include polyethersulfone (PES). ), polyacrylate (PA), polyarylate (PAT), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene Polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), Cellulose triacetate (CAT or TAC), cellulose acetate propionate (CAP), and combinations thereof. The materials of the buffer layer BL, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer dielectric layer ID, and the barrier protection layer BP may include, for example , silicon oxide (SiO x ), silicon nitride (SiN x ), Silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide (SiOC) or aluminum oxide (AlO x ) and combinations thereof. The materials of the gate electrode G, the first electrode M1, the second electrode M2, and the third electrode M3 may include, for example, indium (In), tin (Sn), aluminum (Al), gold (Au), platinum (Pt), and indium. (In), zinc (Zn), germanium (Ge), silver (Ag), lead (Pb), palladium (Pd), copper (Cu), gold beryllium (AuBe), germanium beryllium (BeGe), nickel ( At least one of materials consisting of Ni), lead tin (PbSn), chromium (Cr), gold zinc (AuZn), titanium (Ti), tungsten (W), and titanium tungsten (TiW). The top gate transistor T1 and the bottom gate transistor T2 can be, for example, polysilicon as the main material, or the top gate transistor T1 and the bottom gate transistor T2 can be the transparent conductive material as the main material. The transparent conductive material may include indium tin oxide (ITO), zinc oxide (ZnO), aluminum gallium indium tin (AlGaInSnO), zinc aluminum oxide (AZO), tin oxide (SnO 2 ), indium oxide (In 2 O 3 ), Zinc tin oxide (SnZnO) or graphene (Graphene). The aforementioned materials are only examples, and of course other preferable materials can be used, and they are not limited to the scope of the present invention.

請參閱第1圖和第3圖，其為反向器之示意圖和本發明之垂直邏輯閘結構之第二實施例之結構圖。如第1圖和第3圖所示，本發明之垂直邏輯閘結構，其對應的邏輯閘為反向器，並包括基板S、第一通道層C1、閘極電極G、第一電極M1、第二電極M2、第二通道層C2、第三電極M3、第四電極M4、緩衝層BL、第一閘極絕緣層GI1、第二閘極絕緣層GI2、層間介電層ID及屏障保護層BP，其配置關係與第一實施例類似，於此不再加以重新敘述相似之處，但本發明之第二實施例與第一實施例仍有不同之處，其差異：第一電極M1及第二電極M2設置在層間介電層ID與屏障保護層BP之間，第二通道層C2、第三電極M3及第四電極M4設置在第二閘極絕緣層GI2與層間介電層ID之間，第三電極M3和第四電極M4部分重疊於第二通道層C2，第三電極M3和第四電極M4設置於第二通道層C2的周側。第一電極M1沿著第一通孔電性連接第一通道層C1，第二電極M2沿著第二通孔電性連接第一通道層C1；亦即，第一電極M1從第一閘極絕緣層GI1中的第一通道層C1延伸至屏障保護層BP和層間介電層ID的交界，第二電極M2從第一閘極絕緣層GI1中的第一通道層C1延伸至屏障保護層BP和層間介電層ID的交界。Please refer to Figures 1 and 3, which are schematic diagrams of the inverter and the structure diagram of the second embodiment of the vertical logic gate structure of the present invention. As shown in Figures 1 and 3, the vertical logic gate structure of the present invention, the corresponding logic gate is an inverter, and includes a substrate S, a first channel layer C1, a gate electrode G, a first electrode M1, The second electrode M2, the second channel layer C2, the third electrode M3, the fourth electrode M4, the buffer layer BL, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer dielectric layer ID, and the barrier protection layer BP, its configuration relationship is similar to that of the first embodiment, and the similarities will not be re-described here. However, the second embodiment of the present invention is still different from the first embodiment. The differences are: the first electrode M1 and the first embodiment. The second electrode M2 is disposed between the interlayer dielectric layer ID and the barrier protection layer BP, and the second channel layer C2, the third electrode M3, and the fourth electrode M4 are disposed between the second gate insulating layer GI2 and the interlayer dielectric layer ID. In between, the third electrode M3 and the fourth electrode M4 partially overlap the second channel layer C2, and the third electrode M3 and the fourth electrode M4 are arranged on the peripheral side of the second channel layer C2. The first electrode M1 is electrically connected to the first channel layer C1 along the first through hole, and the second electrode M2 is electrically connected to the first channel layer C1 along the second through hole; The first channel layer C1 in the insulating layer GI1 extends to the boundary between the barrier protective layer BP and the interlayer dielectric layer ID, and the second electrode M2 extends from the first channel layer C1 in the first gate insulating layer GI1 to the barrier protective layer BP The interface with the ID of the interlayer dielectric layer.

需說明的是，於第二實施例中，第三電極M3和第四電極M4為和第二通道層C2同一層，第三電極M3和第四電極M4位於以第二通道層C2為基準的相對兩側，第三電極M3、第四電極M4、第二通道層C2以及閘極電極G形成底閘極電晶體T2，第三電極M3和第四電極M4為底閘極電晶體T2的汲極和源極。It should be noted that in the second embodiment, the third electrode M3 and the fourth electrode M4 are in the same layer as the second channel layer C2, and the third electrode M3 and the fourth electrode M4 are located on the basis of the second channel layer C2. On opposite sides, the third electrode M3, the fourth electrode M4, the second channel layer C2, and the gate electrode G form a bottom gate transistor T2, and the third electrode M3 and the fourth electrode M4 are drains of the bottom gate transistor T2. Pole and source.

於一實施例中，閘極電極G連接於輸入端IN，第一電極M1連接於輸出端OUT，第二電極M2連接於電壓源VDD，第三電極M3連接於電壓源VSS。於另一實施例中，閘極電極G連接於輸入端IN，第一電極M1連接於輸出端OUT，第二電極M2連接於電壓源VSS，第三電極M3連接於電壓源VDD。In one embodiment, the gate electrode G is connected to the input terminal IN, the first electrode M1 is connected to the output terminal OUT, the second electrode M2 is connected to the voltage source VDD, and the third electrode M3 is connected to the voltage source VSS. In another embodiment, the gate electrode G is connected to the input terminal IN, the first electrode M1 is connected to the output terminal OUT, the second electrode M2 is connected to the voltage source VSS, and the third electrode M3 is connected to the voltage source VDD.

請參閱第4圖和第5圖，其為傳輸閘之示意圖和本發明之垂直邏輯閘結構之第三實施例之結構圖。如第4圖和第5圖所示，本發明之垂直邏輯閘結構，其對應的邏輯閘為傳輸器，並包括基板S、第一通道層C1、第一電極M1、延伸電極M5、第二通道層C2、緩衝層BL、第一閘極絕緣層GI1、第二閘極絕緣層GI2、層間介電層ID及屏障保護層BP，其配置關係與第一實施例類似，於此不再加以重新敘述相似之處，但本發明之第三實施例與第一實施例仍有不同之處，其差異：閘極電極G包含第一閘極G1及第二閘極G2，第一閘極G1設置在第一閘極絕緣層GI1與第二閘極絕緣層GI2之間，第一閘極G1也位於第一閘極絕緣層GI1和第二閘極絕緣層GI2的交界處，第二閘極G2設置在第二閘極絕緣層GI2與層間介電層ID之間，第二閘極G2也位於第二閘極絕緣層GI2與層間介電層ID的交界處。第二電極M2和第三電極M3形成延伸電極M5，第二通道層C2、第一電極M1及延伸電極M5設置在層間介電層ID與屏障保護層BP之間，第一電極M1與延伸電極M5部分重疊於第二通道層C2，第一電極M1與延伸電極M5也位於第二通道層C2的周側。第一電極M1沿著第一通孔電性連接第一通道層C1，延伸電極M5沿著第二通孔電性連接第一通道層C1；亦即，第一電極M1從第一閘極絕緣層GI1中的第一通道層C1延伸至屏障保護層BP和層間介電層ID的交界，延伸電極M5從第一閘極絕緣層GI1中的第一通道層C1延伸至屏障保護層BP 和層間介電層ID的交界。Please refer to FIG. 4 and FIG. 5, which are schematic diagrams of the transmission gate and the structure diagram of the third embodiment of the vertical logic gate structure of the present invention. As shown in Figures 4 and 5, the vertical logic gate structure of the present invention has a corresponding logic gate as a transmitter and includes a substrate S, a first channel layer C1, a first electrode M1, an extension electrode M5, and a second The channel layer C2, the buffer layer BL, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer dielectric layer ID, and the barrier protection layer BP. The configuration relationship is similar to that of the first embodiment, and will not be described here. Restate the similarities, but there are still differences between the third embodiment of the present invention and the first embodiment. The differences: the gate electrode G includes the first gate G1 and the second gate G2, and the first gate G1 Is arranged between the first gate insulating layer GI1 and the second gate insulating layer GI2, the first gate G1 is also located at the junction of the first gate insulating layer GI1 and the second gate insulating layer GI2, and the second gate G2 is disposed between the second gate insulating layer GI2 and the interlayer dielectric layer ID, and the second gate G2 is also located at the junction of the second gate insulating layer GI2 and the interlayer dielectric layer ID. The second electrode M2 and the third electrode M3 form an extension electrode M5. The second channel layer C2, the first electrode M1 and the extension electrode M5 are arranged between the interlayer dielectric layer ID and the barrier protection layer BP. The first electrode M1 and the extension electrode M5 partially overlaps the second channel layer C2, and the first electrode M1 and the extension electrode M5 are also located on the peripheral side of the second channel layer C2. The first electrode M1 is electrically connected to the first channel layer C1 along the first through hole, and the extension electrode M5 is electrically connected to the first channel layer C1 along the second through hole; that is, the first electrode M1 is insulated from the first gate The first channel layer C1 in the layer GI1 extends to the boundary between the barrier protection layer BP and the interlayer dielectric layer ID, and the extension electrode M5 extends from the first channel layer C1 in the first gate insulating layer GI1 to the barrier protection layer BP and the interlayer The junction of the dielectric layer ID.

需說明的是，延伸電極M5的形成可不需先形成第二電極M2和第三電極M3而直接形成，延伸電極M5的形成可類似第二實施例的第二電極M2形成，僅是延伸電極M5直接延伸接觸到第二通道層C2 。It should be noted that the formation of the extension electrode M5 can be directly formed without first forming the second electrode M2 and the third electrode M3. The formation of the extension electrode M5 can be similar to that of the second electrode M2 of the second embodiment, except that the extension electrode M5 is formed. It extends directly to the second channel layer C2.

於一實施例中，第一閘極G1連接於時脈訊號源CLK1，第二閘極G2連接於反向時脈訊號源CLK2，第一電極M1連接於輸入端IN，第二電極M2及第三電極M3連接於輸出端OUT。In one embodiment, the first gate G1 is connected to the clock signal source CLK1, the second gate G2 is connected to the reverse clock signal source CLK2, the first electrode M1 is connected to the input terminal IN, the second electrode M2 and the The three-electrode M3 is connected to the output terminal OUT.

綜觀所述，本發明之垂直邏輯閘結構，結合底閘極電晶體T2和頂閘極電晶體T1，來節省電路佈局面積。In summary, the vertical logic gate structure of the present invention combines the bottom gate transistor T2 and the top gate transistor T1 to save the circuit layout area.

以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包含於後附之申請專利範圍中。The above descriptions are merely illustrative and not restrictive. Any equivalent modifications or alterations that do not depart from the spirit and scope of the present invention should be included in the scope of the appended patent application.

BP:屏障保護層 BL:緩衝層 C1:第一通道層 C2:第二通道層 G:閘極電極 G1:第一閘極 G2:第二閘極 GI1:第一閘極絕緣層 GI2:第二閘極絕緣層 ID:層間介電層 IN:輸入端 M1:第一電極 M2:第二電極 M3:第三電極 M4:第四電極 OUT:輸出端 S:基板 T1:頂閘極電晶體 T2:底閘極電晶體 VDD、VSS:電壓源BP: barrier protection layer BL: buffer layer C1: The first channel layer C2: The second channel layer G: Gate electrode G1: first gate G2: second gate GI1: first gate insulating layer GI2: The second gate insulating layer ID: Interlayer dielectric layer IN: Input M1: first electrode M2: second electrode M3: third electrode M4: Fourth electrode OUT: output terminal S: substrate T1: Top gate transistor T2: bottom gate transistor VDD, VSS: voltage source

第1圖為反向器之示意圖。Figure 1 is a schematic diagram of the inverter.

第2圖為本發明之垂直邏輯閘結構之第一實施例之結構圖。Figure 2 is a structural diagram of the first embodiment of the vertical logic gate structure of the present invention.

第3圖為本發明之垂直邏輯閘結構之第二實施例之結構圖。Figure 3 is a structural diagram of the second embodiment of the vertical logic gate structure of the present invention.

第4圖為傳輸閘之示意圖。Figure 4 is a schematic diagram of the transmission gate.

第5圖為本發明之垂直邏輯閘結構之第三實施例之結構圖。Figure 5 is a structural diagram of the third embodiment of the vertical logic gate structure of the present invention.

BP:屏障保護層 BP: barrier protection layer

BL:緩衝層 BL: buffer layer

C1:第一通道層 C1: The first channel layer

C2:第二通道層 C2: The second channel layer

G:閘極電極 G: Gate electrode

GI1:第一閘極絕緣層 GI1: first gate insulating layer

GI2:第二閘極絕緣層 GI2: The second gate insulating layer

ID:層間介電層 ID: Interlayer dielectric layer

IN:輸入端 IN: Input

M1:第一金屬 M1: The first metal

M2:第二金屬 M2: second metal

M3:第三金屬 M3: The third metal

OUT:輸出端 OUT: output terminal

S:基板 S: substrate

VDD、VSS:電壓源 VDD, VSS: voltage source

Claims (9)

一種垂直邏輯閘結構，其包含： 一基板； 一第一通道層，設置於該基板上； 一閘極電極，設置於該第一通道層上，該閘極電極重疊於該第一通道層； 一第一電極，設置於該第一通道層上，且電性連接該第一通道層； 一第二電極，設置於該第一通道層上，且電性連接該第一通道層，該閘極電極、該第一通道層、該第一電極及該第二電極形成一頂閘極電晶體； 一第二通道層，設置於該閘極電極上，該第一電極電性連接該第二通道層，且該第二通道層於一垂直方向上部分重疊於該第一通道層；以及 一第三電極，設置於該第二通道層上，且電性連接該第二通道層，該閘極電極、該第二通道層、該第一電極及該第三電極形成一底閘極電晶體。 A vertical logic gate structure, which includes: A substrate; A first channel layer disposed on the substrate; A gate electrode disposed on the first channel layer, and the gate electrode overlaps the first channel layer; A first electrode disposed on the first channel layer and electrically connected to the first channel layer; A second electrode is disposed on the first channel layer and is electrically connected to the first channel layer. The gate electrode, the first channel layer, the first electrode, and the second electrode form a top gate electrode Crystal A second channel layer disposed on the gate electrode, the first electrode is electrically connected to the second channel layer, and the second channel layer partially overlaps the first channel layer in a vertical direction; and A third electrode is disposed on the second channel layer and is electrically connected to the second channel layer. The gate electrode, the second channel layer, the first electrode, and the third electrode form a bottom gate electrode Crystal. 如請求項1所述之垂直邏輯閘結構，進一步包含： 一第一閘極絕緣層，設置在該第一通道層與該閘極電極之間； 一第二閘極絕緣層，設置於該第一閘極絕緣層上； 一層間介電層，設置於該第二閘極絕緣層上；以及 一屏障保護層，設置於該層間介電層上。 The vertical logic gate structure as described in claim 1, further comprising: A first gate insulating layer disposed between the first channel layer and the gate electrode; A second gate insulating layer disposed on the first gate insulating layer; An interlayer dielectric layer disposed on the second gate insulating layer; and A barrier protection layer is arranged on the interlayer dielectric layer. 如請求項2所述之垂直邏輯閘結構，其中該閘極電極設置在該第一閘極絕緣層與該第二閘極絕緣層之間，該第二通道層、該第一電極、該第二電極及該第三電極設置在該層間介電層與該屏障保護層之間，該第一電極與該第三電極部分重疊於該第二通道層，該第一電極沿著一第一通孔電性連接該第一通道層，該第二電極沿著一第二通孔電性連接該第一通道層。The vertical logic gate structure according to claim 2, wherein the gate electrode is disposed between the first gate insulating layer and the second gate insulating layer, the second channel layer, the first electrode, and the second gate insulating layer The two electrodes and the third electrode are arranged between the interlayer dielectric layer and the barrier protection layer, the first electrode and the third electrode partially overlap the second channel layer, and the first electrode is along a first channel. The hole is electrically connected to the first channel layer, and the second electrode is electrically connected to the first channel layer along a second through hole. 如請求項3所述之垂直邏輯閘結構，其中該閘極電極連接於一輸入端，該第一電極連接於一輸出端，該第二電極及該第三電極分別連接於一電壓源。The vertical logic gate structure according to claim 3, wherein the gate electrode is connected to an input terminal, the first electrode is connected to an output terminal, and the second electrode and the third electrode are respectively connected to a voltage source. 如請求項2所述之垂直邏輯閘結構，其中該閘極電極設置在該第一閘極絕緣層與該第二閘極絕緣層之間，該第一電極及該第二電極設置在該層間介電層與該屏障保護層之間，該第二通道層及該第三電極設置在該第二閘極絕緣層與該層間介電層之間，該第三電極部分重疊於該第二通道層，該第一電極沿著一第一通孔電性連接該第一通道層，該第二電極沿著一第二通孔電性連接該第一通道層。The vertical logic gate structure according to claim 2, wherein the gate electrode is arranged between the first gate insulating layer and the second gate insulating layer, and the first electrode and the second electrode are arranged between the layers Between the dielectric layer and the barrier protection layer, the second channel layer and the third electrode are disposed between the second gate insulating layer and the interlayer dielectric layer, and the third electrode partially overlaps the second channel The first electrode is electrically connected to the first channel layer along a first through hole, and the second electrode is electrically connected to the first channel layer along a second through hole. 如請求項5所述之垂直邏輯閘結構，其中該閘極電極連接於一輸入端，該第一電極連接於一輸出端，該第二電極及該第三電極分別連接於一電壓源。The vertical logic gate structure according to claim 5, wherein the gate electrode is connected to an input terminal, the first electrode is connected to an output terminal, and the second electrode and the third electrode are respectively connected to a voltage source. 如請求項2所述之垂直邏輯閘結構，其中該閘極電極包含一第一閘極及一第二閘極，該第一閘極設置在該第一閘極絕緣層與該第二閘極絕緣層之間，該第二閘極設置在該第二閘極絕緣層與該層間介電層之間，該第二電極和該第三電極形成一延伸電極，該第二通道層、該第一電極及該延伸電極設置在該層間介電層與該屏障保護層之間，該第一電極與該延伸電極部分重疊於該第二通道層，該第一電極沿著一第一通孔電性連接該第一通道層，該延伸電極沿著一第二通孔電性連接該第一通道層。The vertical logic gate structure according to claim 2, wherein the gate electrode includes a first gate and a second gate, and the first gate is disposed on the first gate insulating layer and the second gate Between the insulating layers, the second gate is arranged between the second gate insulating layer and the interlayer dielectric layer, the second electrode and the third electrode form an extended electrode, the second channel layer, the second An electrode and the extension electrode are disposed between the interlayer dielectric layer and the barrier protection layer, the first electrode and the extension electrode partially overlap the second channel layer, and the first electrode is electrically connected along a first through hole. The first channel layer is electrically connected, and the extension electrode is electrically connected to the first channel layer along a second through hole. 如請求項1所述之垂直邏輯閘結構，該第一閘極連接於一時脈訊號源，該第二閘極連接於一反向時脈訊號源，該第一電極連接於一輸入端，該第二電極及該第三電極連接於一輸出端。According to the vertical logic gate structure of claim 1, the first gate is connected to a clock signal source, the second gate is connected to a reverse clock signal source, the first electrode is connected to an input terminal, the The second electrode and the third electrode are connected to an output terminal. 如請求項1所述之垂直邏輯閘結構，進一步包含一緩衝層，該緩衝層設置在該基板與該第一通道層之間。The vertical logic gate structure according to claim 1, further comprising a buffer layer disposed between the substrate and the first channel layer.
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