CN103137477A - Preparation method for InP based high electron mobility transistor (HEMT) on Si substrate - Google Patents

Preparation method for InP based high electron mobility transistor (HEMT) on Si substrate Download PDF

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CN103137477A
CN103137477A CN2013100611053A CN201310061105A CN103137477A CN 103137477 A CN103137477 A CN 103137477A CN 2013100611053 A CN2013100611053 A CN 2013100611053A CN 201310061105 A CN201310061105 A CN 201310061105A CN 103137477 A CN103137477 A CN 103137477A
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CN103137477B (en
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李士颜
周旭亮
于鸿艳
李梦珂
米俊萍
潘教青
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Institute of Semiconductors of CAS
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Abstract

The invention discloses a preparation method for an InP based high electron mobility transistor (HEMT) on a Si substrate. The preparation method for the InP based HEMT on the Si substrate includes the steps: S1, growing a SiO2 layer on the Si substrate; S2, corrading the SiO2 layer to form a plurality of grooves in the SiO2 layer, and enabling the Si substrate to be exposed to the bottoms of the grooves; S3, adopting a process of low-pressure metal organic chemical vapor deposition to grow first InP buffer layers, Fe-mixed InP half insulating layers, second InP buffer layers, GaInAs channel layers, AlInAs isolating layers, Si-mixed GaInAs supply layers, barrier layers and Si-mixed GaInAs contact layers in the grooves in sequence; and S4, manufacturing source electrodes, drain electrodes and grid electrodes on the Si-mixed GaInAs contact layers. Due to the fact that growth raw materials are changed, growth temperature is lowered, and a growth rate is optimized, defects of heterogeneous interfaces are reduced and quality of epitaxial layers is improved.

Description

The method for preparing the InP based hemts on the Si base
Technical field
The present invention relates to a kind of method for preparing InP based hemts (high electron mobility field-effect transistor) on the Si base, particularly a kind of MOCVD and high aspect ratio trench quite restriction technologies (AspectRatio Trapping, ART) are combined the method for preparing the InP based hemts on the Si base.
Background technology
High electron mobility field-effect transistor (HEMT), claiming again modulation-doped FET (MODFET), is a kind of field-effect transistor (FET) of two-dimensional electron gas conduction of the heterogeneous interface that forms with backing material and another kind of wide bandgap material.Because of free from admixture in its raceway groove, basically do not exist ionized impurity scattering on the impact of electron motion, so electron mobility is higher and gain the name.The operation principle of HEMT is that the variation by the control gate pole tension makes the source, the channel current between leaking produces corresponding the variation, thereby reaches the purpose of amplifying signal.Its advantage is to have high frequency and low-noise characteristic.HEMT now has been applied to accepting in circuit of satellite television, mobile communication, military communication and radar system.Since GaAs based hemts in 1980 is succeeded in developing, obtained very fast development.And the InP based hemts has higher operating frequency and lower noise, is used for millimeter wave high frequency band and submillimeter wave frequency range.
Yet HEMT generally is based on the semi-conducting material preparation of III-V family.Become the circuit technology can not be compatible with present Si basis set, limited the application of HEMT.and along with improving constantly of integrated level, integrated circuit technique develops into 22 nm technology node and when following, the Si basis set becomes circuit engineering in speed, power consumption, integrated level, the aspects such as reliability will be subject to the restriction of a series of Basic Physical Problems and technology problem, and expensive building of production line and manufacturing cost make IC industry face huge investment risk, the Si basis set becomes to be faced with huge challenge, thereby realize that the preparation of high mobility devices on the Si base and compatibility are the effective ways that addresses this problem, therefore the preparation that realizes the III-V family device on the Si base is the effective ways that reply Si basis set becomes challenge.
The high-quality III-V of extension family semi-conducting material is the prerequisite of preparation Si base high mobility devices on the Si substrate.But the lattice mismatch of InP material and Si is larger, and heat is adaptive larger, therefore can produce a large amount of dislocations when heteroepitaxy.Simultaneously, existence due to polar material extension and substrate level on nonpolar substrate, can produce a large amount of antiphase domain (Anti-phase domain in epitaxial loayer, APD), antiphase domain border (Anti-phase boundary, APB) be scattering and the complex centre of charge carrier, introduce simultaneously defect level in the forbidden band.These dislocations and antiphase domain border can extend to the surface of epitaxial loayer always, have had a strong impact on the quality of epitaxial loayer, reduce the mobility of charge carrier.The preparation of the Si base III-V HEMT of family device must solve lattice mismatch and these two problems of antiphase domain of InP and Si.
Summary of the invention
The technical problem that (one) will solve
The object of the invention is to, a kind of method for preparing the InP based hemts on the Si base is provided, the method can prepare the InP HEMT on the Si base, the HEMT device of the type can with traditional Si process compatible, improve device speed, reduce power consumption, and expanded greatly the application of HEMT.The method is used the MOCVD growing technology, by feed change and in conjunction with the high aspect ratio trench quite restriction technologies, the generation of InP/Si interface misfit dislocation and APD have been suppressed in the vertical direction to the extension of epitaxial loayer, thereby obtain high-quality InP epitaxial loayer, and then design and produce high-mobility field-effect transistor (HEMT) device on the high-quality epitaxial loayer in raceway groove.
(2) technical scheme
For solving the problems of the technologies described above, the present invention proposes a kind of method for preparing the InP based hemts on the Si base, comprises the steps: step S1: SiO grows on silicon substrate 2Layer; Step S2: the described SiO of etching 2Layer is with at this SiO 2Form a plurality of grooves on layer, and make channel bottom expose described silicon substrate; Step S3: adopt low-pressure MOCVD technique grow successively AlInAs accommodating layer, the barrier layer of an InP resilient coating, the InP semi-insulating layer of mixing Fe, the 2nd InP resilient coating, GaInAs channel layer, AlInAs separator, doping Si, the GaInAs contact layer of doping Si in described groove; Step S4: make source electrode, drain and gate on the GaInAs contact layer of described doping Si.
In a kind of specific embodiment of the present invention, described Si substrate is that p-type resistivity is greater than high resistant (001) Si of 2000 Ω cm.
In a kind of specific embodiment of the present invention, described SiO 2The thickness of layer is 500～1000nm, and the width of described groove is 200～300nm.
In a kind of specific embodiment of the present invention, in described step S2, as the SiO of described channel bottom 2The thickness of layer stops etching and cleans groove when being certain thickness, to remove the remaining SiO of described channel bottom 2Layer is to expose silicon substrate
In a kind of specific embodiment of the present invention, in described step S3, described low-pressure MOCVD technology controlling and process reative cell growth pressure is 70～120mBar.
In a kind of specific embodiment of the present invention, in described step S3, the growth temperature of the described InP resilient coating of growing and growth rate are lower than growth temperature and the growth rate of other each layers of growth.
In a kind of specific embodiment of the present invention, the growth temperature of the described InP resilient coating of described growth is between 450～550 ℃, and growth rate is 0.1～0.5nm/s; Growth is total to the growth temperature of his each layer between 600～700 ℃, and growth rate is 0.8～1.2nm/s.
In a kind of specific embodiment of the present invention, in described step S3, after described each layer of having grown, will exceed the GaInAs contact layer polishing of the described doping Si of groove, be polished to and described SiO 2Layer is substantially flush.
In a kind of specific embodiment of the present invention, the atom ratio of described GaInAs channel layer 7 is Ga 0.47In 0.53As.
In a kind of specific embodiment of the present invention, the atom ratio of described AlInAs accommodating layer is Al 0.48In 0.52As.
(3) beneficial effect
The present invention is combined by the method that limits with metal organic-matter chemical vapour phase epitaxy (MOCVD) and high aspect ratio trench quite, makes the misfit dislocation at InP/Si interface and antiphase domain border terminate in SiO 2On wall, obtain high-quality InP epitaxially deposited layer in the growth of Si substrate.
The present invention reduces growth temperature by changing growth raw material, other parameters such as Optimal Growing speed, the defective of minimizing heterogeneous interface, the quality of raising epitaxial loayer.
The present invention can further prepare InP based hemts (high electron mobility field-effect transistor) device of Si base on high-quality InP epitaxial loayer.
Description of drawings
Fig. 1 is that the method according to this invention is at Si Grown SiO 2Structural representation after layer;
Fig. 2 is that the method according to this invention forms SiO after photoetching 2The structural representation of groove;
Fig. 3 is that the method according to this invention washes thin layer SiO in groove 2Structural representation;
Fig. 4 is the structural representation after the method according to this invention growing semi-insulated indium phosphide in groove is mixed iron layer and indium phosphide resilient coating;
Fig. 5 is the structural representation of the single raceway groove of Fig. 4;
Fig. 6 is grow on the InP resilient coating structural representation of the InP semi-insulating layer of mixing Fe of the method according to this invention
Fig. 7 is that the method according to this invention is being mixed the structural representation of giving birth to the InP resilient coating on the InP semi-insulating layer of Fe
Fig. 8 is grow on the InP resilient coating structural representation of GaInAs channel layer of the method according to this invention;
Fig. 9 is the structural representation of the method according to this invention extension AlInAs separator on the GaInAs channel layer;
Figure 10 is the structural representation of the method according to this invention accommodating layer of the AlInAs of grow doping Si on the AlInAs separator;
Figure 11 is the structural representation of the method according to this invention extension AlInAs barrier layer on the accommodating layer of AlInAs;
Figure 12 is the structural representation of the method according to this invention contact layer of the GaInAs of grow doping Si on the AlInAs barrier layer;
Figure 13 is that the method according to this invention adopts chemico-mechanical polishing that the GaInAs contact layer is polished to and SiO 2The structural representation that layer flushes;
Figure 14 is that the method according to this invention prepares the structural representation of source electrode, drain and gate on the GaInP contact layer.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in further detail.
Fig. 1～Figure 14 has shown each step of the method for preparing the InP based hemts on the Si base of one embodiment of the present of invention.See also Fig. 1～Figure 14, method of the present invention comprises the following steps:
Step S1: SiO grows on silicon substrate 2Layer.
In this embodiment, as shown in Figure 1, SiO grows on Si substrate 1 2 Layer 2, described Si substrate 1 is that p-type resistivity is greater than high resistant (001) Si of 2000 Ω cm, described SiO 2The thickness of layer 2 is 500～1000nm;
Step S2: the described SiO of etching 2Layer is with at this SiO 2Form a plurality of grooves on layer, and make channel bottom expose described silicon substrate.
In this embodiment, adopt photoetching and RIE (plasma etching) method at SiO 2On layer 2 along silicon substrate 1＜110〉direction etch a plurality of grooves 3, wherein the width of groove 3 is 200～300nm, is not subjected to the infringement of etching, the SiO when groove 3 bottoms in order to protect silicon substrate 2The thickness of layer 2 stops etching when being about the 25nm left and right, as shown in Figure 2; Then, use respectively piranha (concentrated sulfuric acid and hydrogen peroxide), SC 2(hydrochloric acid and hydrogen peroxide), HF and washed with de-ionized water groove are to remove the remaining SiO of channel bottom 2Layer is to expose silicon substrate, as shown in Figure 3.
Step S3: adopt low-pressure MOCVD (metal organic-matter chemical vapour phase epitaxy) technique grow successively AlInAs accommodating layer, the barrier layer of an InP resilient coating, the InP semi-insulating layer of mixing Fe, the 2nd InP resilient coating, GaInAs channel layer, AlInAs separator, doping Si, the GaInAs contact layer of doping Si in groove.
So-called low-pressure MOCVD technique refers to the metal organic-matter chemical process for vapor phase epitaxy of reative cell growth pressure under 70～120mBar.
The present invention is under 70～120mbar at growth pressure, adopts the method for MOCVD, first under lower temperature and lower growth rate, at interior growth the one InP resilient coating 4 of groove 3, as shown in Figure 4 and Figure 5, wherein for the sake of clarity, Fig. 5 has only shown the situation of a groove.That is, the growth temperature of growth the one InP resilient coating 4 and growth rate are controlled at growth temperature and the growth rate lower than other each layers of growth.
Then, as Fig. 6～shown in Figure 12, under 70～120mbar condition, AlInAs accommodating layer 9, the barrier layer 10 of InP semi-insulating layer 5, the 2nd InP resilient coating 6, GaInAs channel layer 7, AlInAs separator 8, the doping Si of Fe, the GaInAs contact layer 11 of doping Si are mixed in growth.
In this embodiment, in described low-pressure MOCVD technique, with triethylindium, phosphine, tert-butyl group dihydro arsenic, triethyl-gallium, trimethyl aluminium and silane are as raw material.When growth the one InP resilient coating 4, growth temperature is between 450～550 ℃, and growth rate is 0.1～0.5nm/s, and growth thickness is 100～200nm.When the InP semi-insulating layer 5 of Fe was mixed in growth, growth temperature was between 600～700 ℃, and growth rate is 0.8～1.2nm/s, and growth thickness is 200～300nm, and doped source is used diethyl iron solid source, and resistance concentration is greater than 10 7Ohms per square centimetre.When growth the 2nd InP resilient coating 6, growth temperature is between 600～700 ℃, and growth rate is 0.8～1.2nm/s, and growth thickness is 300nm.When growth GaInAs channel layer 7, growth temperature is between 600～700 ℃, and growth rate is 0.8～1.2nm/s, and growth thickness is 30nm, and the atom ratio of described GaInAs channel layer 7 is Ga 0.47In 0.53As.When growth AlInAs separator 8, growth temperature is between 600～700 ℃, and growth rate is 0.8～1.2nm/s, and growth thickness is 10nm.When the AlInAs of grow doping Si accommodating layer 9, growth temperature is between 600～700 ℃, and growth rate is 0.8～1.2nm/s, and growth thickness is 5nm, and atom ratio is Al 0.48In 0.52As.When growth barrier layer 10, growth temperature is between 600～700 ℃, and growth rate is 0.8～1.2nm/s, and growth thickness is 10nm.When the GaInAs of grow doping Si contact layer 11, growth temperature is between 600～700 ℃, and growth rate is 0.8～1.2nm/s, and growth thickness is 100～150nm, and the Si doping content is 1 * 10 9/ cm 3
After above-mentioned each layer of having grown, adopt the method for chemical polishing, GaInAs contact layer 11 polishings that will exceed the doping Si of groove are polished to and SiO 2Layer 2 is substantially flush, as shown in figure 13.
Step S4: make source electrode, drain and gate on the GaInAs contact layer 11 of doping Si.
In this embodiment, adopt the method for evaporation to prepare source electrode 12, drain electrode 13 and grid 14 on the GaInAs contact layer, each electrode adopts Au/Ge/Ni (gold germanium nickel) and Au (gold) multi-layer metal structure, completes thus the preparation of HEMT device, as shown in figure 14.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; be understood that; the above is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims (10)

1. a method for preparing the InP based hemts on the Si base, is characterized in that, comprises the steps:
Step S1: SiO grows on silicon substrate 2Layer;
Step S2: the described SiO of etching 2Layer is with at this SiO 2Form a plurality of grooves on layer, and make channel bottom expose described silicon substrate;
Step S3: adopt low-pressure MOCVD technique grow successively AlInAs accommodating layer, the barrier layer of an InP resilient coating, the InP semi-insulating layer of mixing Fe, the 2nd InP resilient coating, GaInAs channel layer, AlInAs separator, doping Si, the GaInAs contact layer of doping Si in described groove;
Step S4: make source electrode, drain and gate on the GaInAs contact layer of described doping Si.
2. the method for preparing the InP based hemts on the Si base as claimed in claim 1, is characterized in that, described Si substrate is that p-type resistivity is greater than high resistant (001) Si of 2000 Ω cm.
3. the method for preparing the InP based hemts on the Si base as claimed in claim 1, is characterized in that, described SiO 2The thickness of layer is 500～1000nm, and the width of described groove is 200～300nm.
4. the method for preparing the InP based hemts on the Si base as claimed in claim 1, is characterized in that, in described step S2, as the SiO of described channel bottom 2The thickness of layer stops etching and cleans groove when being certain thickness, to remove the remaining SiO of described channel bottom 2Layer is to expose silicon substrate.
5. the method for preparing the InP based hemts on the Si base as claimed in claim 1, is characterized in that, in described step S3, described low-pressure MOCVD technology controlling and process reative cell growth pressure is 70～120mBar.
6. the method for preparing the InP based hemts on the Si base as claimed in claim 5, is characterized in that, in described step S3, the growth temperature of the described InP resilient coating of growing and growth rate are lower than growth temperature and the growth rate of other each layers of growth.
7. the method for preparing the InP based hemts on the Si base as claimed in claim 6, is characterized in that, the growth temperature of the described InP resilient coating of described growth is between 450～550 ℃, and growth rate is 0.1～0.5nm/s; Growth is total to the growth temperature of his each layer between 600～700 ℃, and growth rate is 0.8～1.2nm/s.
8. the method for preparing the InP based hemts on the Si base as claimed in claim 5, is characterized in that, in described step S3, after described each layer of having grown, will exceed the GaInAs contact layer polishing of the described doping Si of groove, is polished to and described SiO 2Layer is substantially flush.
9. the method for preparing the InP based hemts on the Si base as described in any one in claim 1-8, is characterized in that, the atom ratio of described GaInAs channel layer 7 is Ga 0.47In 0.53As.
10. the method for preparing the InP based hemts on the Si base as described in any one in claim 1-8, is characterized in that, the atom ratio of described AlInAs accommodating layer is Al 0.48In 0.52As.
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CN103902668A (en) * 2014-03-14 2014-07-02 中国电子科技集团公司第十三研究所 Method for establishing model of Inp-base HEMT on terahertz frequency band
CN106207752A (en) * 2016-08-31 2016-12-07 武汉光迅科技股份有限公司 A kind of Si based high-power laser instrument and preparation method thereof
CN111106506A (en) * 2019-12-10 2020-05-05 郑州大学 Silicon-based nano laser based on surface plasmon and preparation method thereof

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CN106207752A (en) * 2016-08-31 2016-12-07 武汉光迅科技股份有限公司 A kind of Si based high-power laser instrument and preparation method thereof
CN106207752B (en) * 2016-08-31 2019-02-12 武汉光迅科技股份有限公司 A kind of Si based high-power laser and preparation method thereof
CN111106506A (en) * 2019-12-10 2020-05-05 郑州大学 Silicon-based nano laser based on surface plasmon and preparation method thereof

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