JP2011054685A - Semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress formation of a transition layer in an AlGaAs/InGaP interface. <P>SOLUTION: A semiconductor substrate includes a second semiconductor made of an arsenic compound and a third semiconductor made of a phosphorus compound, wherein the second semiconductor and third semiconductor are in contact with each other, and the second semiconductor contains first atoms in a second concentration and also contains second atoms. Here, the first atoms make the second semiconductor generate carriers of a first conductivity type, and the second concentration is equal to or higher than the concentration of the first atoms at which, the number of carriers increasing as a number of the first atoms doped in the second semiconductor increases, begins to get saturated, and the second atoms decrease the difference between a Fermi level and a charge neutrality level in the second semiconductor. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor substrate.

  Conventionally, as a compound semiconductor manufacturing technique, a technique of selectively wet-etching an AlGaAs-based material using an InGaP-based material as a stopper is known. When phosphoric acid is used as the etching solution, the etching rate of the AlGaAs-based material is high, but the etching rate of the InGaP-based material is low. In contrast, when hydrochloric acid is used as the etching solution, the etching rate of the AlGaAs-based material is low, and the etching rate of the InGaP-based material is high. Therefore, if an InGaP-based epitaxial crystal layer is formed in the middle of an AlGaAs-based epitaxial crystal layer, etching of the AlGaAs-based epitaxial crystal layer can be stopped accurately at a depth where the InGaP-based epitaxial crystal layer exists.

  In Patent Document 1, for the purpose of improving the steepness of the GaAs / InGaP interface, an As-based gas and a Ga-based gas are supplied to a reaction tube and reacted to perform GaAs growth, and the Ga-based gas is turned off. The step of eliminating the Ga droplets, the step of supplying only Ga-based gas to the reaction tube and converting the surface excess As to GaAs by Ga, and the introduction of the Ga-based gas are preceded. It is disclosed that an In-based gas is introduced after a predetermined time, and further a step of supplying a P-based gas to a reaction tube and reacting them to perform InGaP growth after a predetermined time.

International Publication WO2002 / 078068

  However, improvement in the steepness of the interface between a semiconductor made of an arsenic compound (for example, GaAs) and a semiconductor made of a phosphorus compound (for example, InGaP) has not been sufficient. An object of the present invention is to further improve the steepness of the interface between a semiconductor made of an arsenic compound and a semiconductor made of a phosphorus compound.

  In order to solve the above-described problem, in the first aspect of the present invention, a second semiconductor made of an arsenic compound and a third semiconductor made of a phosphorus compound are included, and the second semiconductor and the third semiconductor are in contact with each other. The second semiconductor contains a first atom in a second concentration and contains a second atom, the first atom generates carriers of the first conductivity type in the second semiconductor, and 2 concentration is a concentration equal to or higher than the concentration of the first atom, the carrier number which increases as the amount of the first atom doped into the second semiconductor increases, and the second atom is the second semiconductor. Provided is a semiconductor substrate that reduces the difference between the Fermi level and the charge neutral level.

  Examples of the second atom include an atom having an ionization energy of 0.03 eV or less. In this specification, the ionization energy of the second atom means energy necessary for generating a carrier of the second conductivity type opposite to the first conductivity type when the second atom is introduced into the second semiconductor. The second semiconductor and the third semiconductor contain a third atom belonging to group IIIB, and the bond energy between the second atom and the third atom is larger than the bond energy between the first atom and the third atom. It is preferable. An example of the third atom is Ga.

Preferably, the semiconductor substrate further includes a first semiconductor made of an arsenic compound, the second semiconductor is preferably located between the first semiconductor and the third semiconductor, and the first semiconductor is It is preferable that the first atom is contained at a first concentration, and the first concentration increases as the amount of the first atom doped into the first semiconductor increases, and the number of carriers that starts increasing becomes saturated. It is mentioned that it is the density | concentration beyond the density | concentration of an atom. N type is mentioned as said 1st conductivity type. Examples of the second semiconductor include Al _x1 Ga _y1 As (x1 + y1 = 1, 0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1), and examples of the third semiconductor include In _x2 Ga _y2 P (x2 + y2 = 1, 0 ≦ x2 ≦). 1, 0 ≦ y2 ≦ 1).

Examples of the first atom include one or more atoms selected from Si, Ge, Se, and Te, and examples of the second atom include one or more atoms selected from C, B, Be, O, N, and F. It is done. It is preferable that the second semiconductor contains the second atom having a concentration lower than the second concentration. The second semiconductor preferably contains the second atom at a concentration of 1 × 10 ¹⁷ [pieces / cm ³ ] or more. When the second semiconductor is layered, the thickness of the layered second semiconductor is preferably 5 nm to 100 nm.

In a second aspect of the present invention, the second semiconductor includes a second semiconductor made of an arsenic compound and a third semiconductor made of a phosphorus compound, and the second semiconductor and the third semiconductor are in contact with each other. Contains N-type impurity atoms at a concentration of 4 × 10 ¹⁸ [pieces / cm ³ ] or more, and 1 × 10 ¹⁷ [pieces] of one or more atoms selected from C, B, Be, O, N, and F / Cm ³ ] and a semiconductor substrate containing 4 × 10 ¹⁸ [pieces / cm ³ ] in concentration.

  According to a third aspect of the present invention, there is provided an electronic device including an electronic element obtained using, as an active region, one or more semiconductors selected from the third semiconductor and the second semiconductor in the semiconductor substrate. Examples of the electronic element include a bipolar transistor, and examples of the second semiconductor include a sub-collector of the bipolar transistor. Examples of the electronic element include a field effect transistor, and examples of the second semiconductor include an electron supply layer of the field effect transistor. The electronic element includes a light receiving element or a light emitting element, and the second semiconductor includes a semiconductor layer constituting the light receiving element or the light emitting element.

  In a fourth aspect of the present invention, the method includes forming a second semiconductor made of an arsenic compound on a substrate and forming a third semiconductor made of a phosphorus compound, and forming the second semiconductor. In the step, a first atom that generates carriers of the first conductivity type is introduced at a second concentration, and a second atom that reduces the difference between the Fermi level and the charge neutral level in the second semiconductor is introduced. In the step of forming the third semiconductor, the third semiconductor is formed in contact with the second semiconductor, and the second concentration increases as the amount of the first atoms doped into the second semiconductor increases. Provided is a method for manufacturing a semiconductor substrate having a concentration equal to or higher than the concentration of the first atoms at which the number of carriers to be started to saturate.

  In a fifth aspect of the present invention, the semiconductor device includes a second semiconductor made of an arsenic compound and a third semiconductor made of a phosphorus compound, and the second semiconductor and the third semiconductor are in contact with each other, and the second semiconductor Contains first atoms at a second concentration and contains second atoms, the first atoms generate carriers of the first conductivity type in the second semiconductor, and the second concentration is the second semiconductor. The carrier number that increases as the amount of the first atom doped into the semiconductor layer increases to a concentration equal to or higher than the concentration of the first atom, and the second atom has a Fermi level and charge neutrality in the second semiconductor. Preparing a semiconductor substrate that reduces a difference from a level, etching one of the semiconductors selected from the third semiconductor and the second semiconductor using the other semiconductor as an etching stop material, The other It provides a method of making an electronic device comprising the steps of etching the conductor.

An example of a cross section of a semiconductor substrate 100 is shown. The relationship between the silicon supply amount doped into the AlGaAs crystal and the carrier concentration is shown. An example of a cross section in the case of processing a semiconductor layer in the semiconductor substrate 100 is shown. An example of a cross section in the case of processing a semiconductor layer in the semiconductor substrate 100 is shown. An example of a cross section in the case of processing a semiconductor layer in the semiconductor substrate 100 is shown. An example of a cross section of a semiconductor substrate 600 is shown. The cross-sectional example in the middle of the process of the semiconductor substrate 600 is shown. A cross-sectional example of a heterojunction bipolar transistor 800 manufactured using a semiconductor substrate 600 is shown. An example of a cross section of a semiconductor substrate 900 is shown. The cross-sectional example in the middle of the process of the semiconductor substrate 900 is shown. An example of a cross section of a high electron mobility transistor 1100 manufactured using a semiconductor substrate 900 is shown. An example of a cross section of a semiconductor substrate 1200 is shown. A cross-sectional example of a solar cell 1300 manufactured using a semiconductor substrate 1200 is shown. An example of a cross section of a semiconductor substrate 1400 is shown. A cross-sectional example of a light-emitting diode 1500 manufactured using a semiconductor substrate 1400 is shown.

  Hereinafter, the present invention will be described through embodiments of the invention, but prior to the description of the embodiments, the background and idea behind the present invention by the present inventors will be outlined.

At the interface where a semiconductor made of a phosphorus compound (for example, InGaP; hereinafter referred to as “P-based material”) and a semiconductor made of an arsenic compound (for example, AlGaAs; hereinafter referred to as “As-based material”) are stacked, a P-based material and A transition layer of As-based material may be formed. For example, at the interface between InGaP and AlGaAs, Al _α In _β Ga _γ As _δ P _φ (α + β + γ = 1, δ + φ = 1, 1 ≧ α ≧ 0, 1 ≧ β ≧ 0, 1 ≧ γ ≧ 0, 1 ≧ δ ≧ 0 1 ≧ φ ≧ 0) is formed. Since the transition layer has etching resistance to both phosphoric acid and hydrochloric acid, etching of the As-based material such as AlGaAs is stopped with a P-based material such as InGaP, and the P-based material is removed using hydrochloric acid. Even if the material is to be etched with phosphoric acid, the transition layer (for example, Al _α In _β Ga _γ As _δ P _φ ) remains, which causes an etching failure. In addition, when the etching of the As-based material is stopped with the P-based material and the P-based material is removed using hydrochloric acid and then an electrode is formed on the As-based material, the transition layer remains, so that the electrode This increases the contact resistance between the As-based material and the As-based material.

The present inventors have studied how a transition layer that can cause etching failure and contact resistance increase is formed. It has been found that when an AlGaAs layer and an InGaP layer are continuously formed by MOCVD, the generation of a transition layer can be suppressed by improving the switching sequence of As gas and P gas (see JP 2006-310547 A). ). Furthermore, when the AlGaAs layer contains a large amount of Si as an n-type dopant, it has been found that defects existing in the AlGaAs layer may cause a transition layer. That is, when a large amount of Si is contained, particularly when Si is contained in an amount of 4 × 10 ¹⁸ [pieces / cm ³ ] or more, the Si atom enters a position where the Ga atom should exist (substitution) or the position where the As atom should exist. A state in which As does not exist (vacancies) is likely to occur, and these substitutions or vacancies, and complex defects due to these are likely to occur. As a result of forming the InGaP layer on the AlGaAs layer containing many complex defects, there is a possibility that In or P diffuses into the AlGaAs layer and a transition layer is formed. The present invention has been made based on the inventors' knowledge, and even when the AlGaAs layer contains a large amount of Si, by introducing impurity atoms that suppress complex defects, the transition layer Suppresses the occurrence of

  FIG. 1 shows a cross-sectional example of a semiconductor substrate 100 according to an embodiment of the present invention. Examples of the semiconductor substrate 100 include a support substrate 102, a first semiconductor layer 104 made of an arsenic compound, a second semiconductor layer 106 made of an arsenic compound, and a third semiconductor layer 108 made of a phosphorus compound. The first semiconductor layer 104 is an example of a first semiconductor made of an arsenic compound. The second semiconductor layer 106 is an example of a second semiconductor made of an arsenic compound. The third semiconductor layer 108 is an example of a third semiconductor made of a phosphorus compound. As illustrated, the first semiconductor layer 104, the second semiconductor layer 106, and the third semiconductor layer 108 are formed on the support substrate 102, and the first semiconductor layer 104 and the third semiconductor layer 108 are interposed between the first semiconductor layer 104 and the third semiconductor layer 108. Two semiconductor layers 106 are located.

  The support substrate 102 supports the first semiconductor layer 104, the second semiconductor layer 106, and the third semiconductor layer 108. The support substrate 102 is made of, for example, GaAs. An example of the support substrate 102 is a single crystal GaAs wafer. The support substrate 102 is preferably an epitaxial growth substrate used when the first semiconductor layer 104, the second semiconductor layer 106, and the third semiconductor layer 108 are epitaxially grown.

The first semiconductor layer 104 is a semiconductor made of an arsenic compound. The first semiconductor layer 104 is, for example, Al _x Ga _y As (x + y = 1, 1 ≧ x ≧ 0, 1 ≧ y ≧ 0). The first semiconductor layer 104 contains first atoms at a first concentration. The first concentration is a concentration equal to or higher than the concentration of the first atoms at which the increasing number of carriers starts to saturate as the amount of the first atoms doped into the first semiconductor layer 104 increases. That is, the first concentration is a concentration equal to or higher than the carrier saturation concentration in the first semiconductor layer 104. When the first semiconductor layer 104 is an AlGaAs crystal, the carrier saturation concentration is, for example, 4 × 10 ¹⁸ [pieces / cm ³ ].

  The first atoms generate carriers of the first conductivity type, for example, N type. The first atom is one or more atoms selected from, for example, Si, Ge, Se, and Te.

The carrier saturation concentration corresponds to the impurity concentration at which the carrier number starts to be saturated. FIG. 2 shows the relationship between the supply amount of silicon doped into the AlGaAs crystal and the carrier concentration. When the silicon supply amount is small, the carrier concentration increases as the silicon supply amount increases. However, when the silicon supply amount reaches a concentration of 110 (4 × 10 ¹⁸ [pieces / cm ³ ]), the carrier concentration starts to saturate as shown by the solid line. The concentration 110 corresponds to the carrier saturation concentration.

Since the first semiconductor layer 104 is doped at a concentration higher than the carrier saturation concentration, the first semiconductor layer 104 has as many carriers as possible. Therefore, the first semiconductor layer 104 has a low resistivity, and is a useful semiconductor layer particularly for use in a high-power element. On the other hand, since impurities are doped at a very high concentration, substitution, vacancies, or complex defects thereof are likely to occur, and in the past, a transition layer composed of Al _α In _β Ga _γ As _δ P _φ is generated. It's easy to do. However, in this embodiment, since the second semiconductor layer 106 is located between the first semiconductor layer 104 and the third semiconductor layer 108, generation of a transition layer can be effectively suppressed.

The second semiconductor layer 106 is made of an arsenic compound and is in contact with the third semiconductor layer 108. The second semiconductor layer 106 is made of, for example, Al _x1 Ga _y1 As (x1 + y1 = 1, 0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1). The second semiconductor layer 106 contains the first atoms at the second concentration and the second atoms. The second concentration is a concentration equal to or higher than the concentration of the first atoms at which the increasing number of carriers starts to saturate as the amount of the first atoms doped into the second semiconductor layer 106 increases. That is, the second concentration is a concentration equal to or higher than the carrier saturation concentration in the second semiconductor layer 106.

  The second atom reduces the difference between the Fermi level and the charge neutral level in the second semiconductor. The second atom preferably has an ionization energy of 0.03 eV or less. The ionization energy of the second atom is energy required when the second atom is introduced into the second semiconductor layer 106 to generate a carrier of the second conductivity type such as P type opposite to the first conductivity type such as N type. is there. Examples of the second atom include one or more atoms selected from C, B, Be, O, N, and F.

The second semiconductor layer 106 preferably contains the second atom at a concentration equal to or lower than the second concentration. The second semiconductor layer 106 preferably contains the second atom at a concentration of 1 × 10 ¹⁷ [pieces / cm ³ ] or more. The thickness of the second semiconductor layer 106 is preferably 5 nm or more and 100 nm or less.

That is, the second semiconductor layer 106 includes N-type impurity atoms that generate electrons at a concentration of 4 × 10 ¹⁸ [pieces / cm ³ ] or more, and is selected from C, B, Be, O, N, and F One or more atoms are preferably contained at a concentration of 1 × 10 ¹⁷ [pieces / cm ³ ] or more and 4 × 10 ¹⁸ [pieces / cm ³ ] or less.

Since the second semiconductor layer 106 includes the second atom, the semiconductor substrate 100 of the present embodiment is made of Al _α In _β Ga _γ As _δ P _φ between the second semiconductor layer 106 and the third semiconductor layer 108. It becomes difficult to form a transition layer. In particular, even if the first semiconductor layer 104 is doped with a very high amount of first atoms, the second semiconductor layer 106 containing the second atoms is formed between the first semiconductor layer 104 and the third semiconductor layer 108. Therefore, the formation of a transition layer that hinders selective etching can be suppressed. As a result, good selective etching with no etching residue can be performed, and contact resistance can be reduced even when electrodes are formed.

The third semiconductor layer 108 is a semiconductor made of a phosphorus compound. The third semiconductor layer 108 is made of, for example, In _x2 Ga _y2 P (x2 + y2 = 1, 0 ≦ x2 ≦ 1, 0 ≦ y2 ≦ 1). The third semiconductor layer 108 may be doped with impurities, or may be non-doped without being doped with impurities. The conductivity type of the impurity may be P-type or N-type. The second semiconductor layer 106 and the third semiconductor layer 108 contain atoms belonging to Group IIIB, for example, Ga. The bond energy between the second atom and the atom belonging to Group IIIB is preferably larger than the bond energy between the first atom and an atom belonging to Group IIIB.

  3 to 5 show cross-sectional examples when processing a semiconductor layer in the semiconductor substrate 100 in the order of processing. First, the first semiconductor layer 104, the second semiconductor layer 106, and the third semiconductor layer 108 are sequentially epitaxially grown on the support substrate 102. For epitaxial growth, MOCVD or molecular beam epitaxy may be used, and MOCVD is preferred.

For the epitaxial growth of the first semiconductor layer 104 and the second semiconductor layer 106, an organic gallium gas such as trimethyl gallium (Ga (CH ₃ ) ₃ ), triethyl gallium (Ga (C ₂ H ₅ ) ₃ ) is used as a Ga material. be able to. Arsine (AsH ₃ ) can be used as the As raw material. When a part of gallium is replaced with aluminum, an organoaluminum gas such as trimethylaluminum (Al (CH ₃ ) ₃ ) or triethylaluminum (Al (C ₂ H ₅ ) ₃ ) can be used as the Al material.

When the first semiconductor layer 104 and the second semiconductor layer 106 are doped with Si as an impurity material for generating N-type carriers, silanes such as silane (SiH ₄ ) and disilane (Si ₂ H ₆ ) are used as Si raw materials. Gas can be used. Instead of silane or the like, a halogenated silane such as chlorosilane can be used. The doping amount of silicon atoms (atom supply amount) can be adjusted by changing the supply amount of Si raw material gas (molar ratio to Ga raw material and As raw material). Silicon atoms are introduced at a concentration equal to or higher than the carrier saturation concentration.

When carbon (C) is introduced as the second impurity into the second semiconductor layer 106, a halogenated carbon such as CBrCl ₃ can be used as the C raw material. The amount of carbon atoms introduced as the second impurity can be controlled by controlling the amount of carbon halide supplied. The amount of C introduced can also be adjusted by adjusting the supply amount (molar ratio) of the organic gallium gas as the Ga raw material and the arsine as the As raw material. If the ratio of organic Ga gas to arsine (V / III ratio) is increased, the amount of introduction of C atoms can be increased. The introduction amount of C atoms is adjusted to 1 × 10 ¹⁷ [pieces / cm ³ ] or more and 4 × 10 ¹⁸ [pieces / cm ³ ] or less.

For the epitaxial growth of the third semiconductor layer 108, an organic gallium gas such as trimethylgallium (Ga (CH ₃ ) ₃ ) or triethyl gallium (Ga (C ₂ H ₅ ) ₃ ) can be used as a Ga material. Phosphine (PH ₃ ) can be used as the P raw material. When a part of gallium is substituted with indium, an organic indium gas such as trimethylindium (In (CH ₃ ) ₃ ) can be used as the In raw material. In the case of introducing an impurity into the third semiconductor layer 108, an impurity gas corresponding to the conductivity type is supplied, and the doping amount of impurity atoms is adjusted by the supply amount of the impurity gas.

  The semiconductor substrate 100 can be manufactured as described above. That is, the method includes a step of forming a second semiconductor layer 106 made of an arsenic compound on the support substrate 102 and a step of forming a third semiconductor layer 108 made of a phosphorus compound in contact with the second semiconductor layer 106. In the step of forming the second semiconductor layer 106, first atoms (for example, Si) that generate carriers of the first conductivity type are introduced at a concentration equal to or higher than the carrier saturation concentration corresponding to the impurity concentration at which the number of carriers begins to saturate. In addition, a method for manufacturing a semiconductor substrate is disclosed in which a second atom (for example, C) in which the difference between the Fermi level and the charge neutral level in the second semiconductor layer 106 is reduced is introduced.

  Such a semiconductor substrate 100 can be applied to selective etching in the processing of the AlGaAs layer 120 formed thereon. As shown in FIG. 3, an AlGaAs layer 120 is formed on the semiconductor substrate 100, and a mask 122 corresponding to the processing pattern is formed on the AlGaAs layer 120. The mask 122 can be exemplified by a material resistant to phosphoric acid and hydrochloric acid, such as a resist, silicon nitride, or silicon oxide.

  Next, as shown in FIG. 4, the whole is immersed in a phosphoric acid solution, and the AlGaAs layer 120 is etched. At this time, since the third semiconductor layer 108 is resistant to phosphoric acid, it functions as an etching stopper.

Next, as shown in FIG. 5, the whole is immersed in a hydrochloric acid solution, and the third semiconductor layer 108 is etched. Since the AlGaAs layer 120 and the second semiconductor layer 106 are resistant to hydrochloric acid, they are not etched at this stage. Here, since a transition layer made of Al _α In _β Ga _γ As _δ P _φ is not formed at the interface between the second semiconductor layer 106 and the third semiconductor layer 108, etching failure does not occur, and the second semiconductor layer Even when an electrode is formed on 106, the contact resistance can be reduced.

  Further, when the second semiconductor layer 106 and the first semiconductor layer 104 are processed, wet etching can be applied using a phosphoric acid solution. In the above example, the AlGaAs-based layer processing method using the third semiconductor layer 108 as a stopper has been described. However, an example in which the third semiconductor layer 108 is processed using the second semiconductor layer 106, which is an AlGaAs-based material, as a stopper can also be given. .

  As described above, an electronic device can be manufactured using the semiconductor substrate 100. That is, the semiconductor device includes a second semiconductor layer 106 made of an arsenic compound and a third semiconductor layer 108 made of a phosphorus compound, and the second semiconductor layer 106 and the third semiconductor layer 108 are in contact with each other. Contains a first atom (for example, Si) having a carrier saturation concentration or more and a second atom (for example, C), and the first atom is a carrier of the first conductivity type (for example, N type) in the second semiconductor layer 106. A step of preparing the semiconductor substrate 100 in which the second atoms reduce the difference between the Fermi level and the charge neutral level in the second semiconductor layer 106, and from the third semiconductor layer 108 and the second semiconductor layer 106. Disclosed is a method for manufacturing an electronic device, the method comprising: etching any one selected semiconductor using the other semiconductor as an etch stop material; and etching the other semiconductor. .

  Various electronic devices can be formed by applying the third semiconductor layer 108 and the second semiconductor layer 106 in the semiconductor substrate 100 described above. That is, an electronic device including an electronic element obtained using one or more semiconductors selected from the third semiconductor layer 108 and the second semiconductor layer 106 as an active region can be manufactured.

  FIG. 6 shows a cross-sectional example of the semiconductor substrate 600. The semiconductor substrate 600 can be used for manufacturing a heterojunction bipolar transistor. The semiconductor substrate 600 includes a support substrate 602, a buffer layer 604, a subcollector layer 606, a second semiconductor layer 608, a third semiconductor layer 610, a subcollector layer 612, a collector layer 614, a base layer 616, a subemitter layer 618, and an emitter layer. 620.

  The support substrate 602 is similar to the support substrate 102. The buffer layer 604, the sub-collector layer 612, the collector layer 614, the base layer 616, the sub-emitter layer 618, and the emitter layer 620 are similar to semiconductor crystal layers that can be applied to a general heterojunction bipolar transistor. For example, the buffer layer 604, the subcollector layer 612, the collector layer 614, and the base layer 616 can be made of GaAs, the subemitter layer 618 can be made of AlGaAs, and the emitter layer 620 can be made of InGaAs. The conductivity type, impurity amount, layer thickness, and the like of each layer can be optimized with values required from device characteristics.

The subcollector layer 606 is similar to the first semiconductor layer 104 described above. The second semiconductor layer 608 is similar to the second semiconductor layer 106 described above. The third semiconductor layer 610 is the same as the third semiconductor layer 108 described above. However, since the third semiconductor layer 610 preferably has high conductivity, Si atoms of 1 × 10 ¹⁸ [/ cm ³ ] or more are introduced as carrier generation impurities. Each of these layers can be manufactured by epitaxial growth using the MOCVD method, as in the case of the semiconductor substrate 100.

  FIG. 7 shows a cross-sectional example during the processing of the semiconductor substrate 600. The subcollector layer 612, the collector layer 614, the base layer 616, the subemitter layer 618, and the emitter layer 620 can be etched using a phosphoric acid solution. In this case, the third semiconductor layer 610 functions as an etching stopper. A second semiconductor layer 608 is formed between the third semiconductor layer 610 and the subcollector layer 606, and a second impurity (for example, C) is added to the second semiconductor layer 608 in the same manner as the second semiconductor layer 106. As a result, the transition layer is not formed. Therefore, after removing the third semiconductor layer 610 with hydrochloric acid, a good etching surface is obtained, and the contact resistance does not increase even when the electrode is formed.

  FIG. 8 shows an example of a cross section of a heterojunction bipolar transistor 800 manufactured using a semiconductor substrate 600. In the step described with reference to FIG. 7, the collector contact region is exposed, and then the base contact region is processed. A collector electrode 802, a base electrode 804, and an emitter electrode 806 are formed to manufacture a heterojunction bipolar transistor 800. That is, it is disclosed that the heterojunction bipolar transistor 800 is an example of a bipolar transistor, and the second semiconductor layer 608 is a sub-collector of the bipolar transistor.

  In the heterojunction bipolar transistor 800, etching is favorably performed in forming the collector contact region. Therefore, the contact resistance between the collector electrode 802 and the subcollector layer can be reduced.

  FIG. 9 shows a cross-sectional example of the semiconductor substrate 900. The semiconductor substrate 900 can be used in the manufacture of heterojunction field effect transistors, such as high electron mobility transistors. The semiconductor substrate 900 includes a supporting substrate 902, a buffer layer 904, an electron supply layer 906, a spacer layer 908, a channel layer 910, a spacer layer 912, an electron supply layer 914, a second semiconductor layer 916, a third semiconductor layer 918, and a contact layer 920. Have

  The support substrate 902 is similar to the support substrate 102. The buffer layer 904, the electron supply layer 906, the spacer layer 908, the channel layer 910, the spacer layer 912, and the contact layer 920 are similar to semiconductor crystal layers that can be applied to a general high electron mobility transistor. For example, the buffer layer 904 can be made of GaAs, the electron supply layer 906, the spacer layers 908 and 912, and the contact layer 920 can be made of AlGaAs, and the channel layer 910 can be made of InGaAs. The conductivity type, impurity amount, thickness, and the like of each layer can be optimized with values required from device characteristics.

The electron supply layer 914, the second semiconductor layer 916, and the third semiconductor layer 918 are the same as the first semiconductor layer 104, the second semiconductor layer 106, and the third semiconductor layer 108, respectively. However, examples in which the third semiconductor layer 918 is not doped or Si of 1 × 10 ¹⁶ [/ cm ³ ] or more is introduced. Each of these layers can be manufactured by epitaxial growth using the MOCVD method, as in the case of the semiconductor substrate 100.

  FIG. 10 shows an example of a cross section during the processing of the semiconductor substrate 900. The contact layer 920 can be etched using a phosphoric acid solution. In this case, the third semiconductor layer 918 functions as an etching stopper. A second semiconductor layer 916 is formed between the third semiconductor layer 918 and the electron supply layer 914, and the second impurity (for example, C) is added to the second semiconductor layer 916 in the same manner as the second semiconductor layer 106. As a result, the transition layer is not formed. Therefore, after removing the third semiconductor layer 918 with hydrochloric acid, a good etching surface is obtained, and contact resistance does not increase even when an electrode is formed.

  FIG. 11 shows a cross-sectional example of a high electron mobility transistor 1100 manufactured using a semiconductor substrate 900. In the process described with reference to FIG. 10, the gate electrode region is exposed, and then the formation of the gate electrode 1106 and the formation of the source electrode 1102 and the drain electrode 1104 over the contact layer 920 are performed, whereby the high electron mobility transistor 1100 is manufactured. The That is, it is disclosed that the high electron mobility transistor 1100 is an example of a field effect transistor, and the second semiconductor layer is an electron supply layer of the field effect transistor.

  In the high electron mobility transistor 1100, etching is favorably performed in the formation of the gate electrode region. Accordingly, traps under the gate electrode 1106 can be reduced.

FIG. 12 shows an example of a cross section of the semiconductor substrate 1200. The semiconductor substrate 1200 can be used for manufacturing a solar cell. The semiconductor substrate 1200 includes a support substrate 1202, an n-AlGaAs layer 1204, a second semiconductor layer 1206, a third semiconductor layer 1208, a p-AlInGaP layer 1210, and a p-GaAs layer 1212. The support substrate 1202 is similar to the support substrate 102. The p-AlInGaP layer 1210 and the p-GaAs layer 1212 are the same as semiconductor crystal layers applicable to general compound semiconductor solar cells. The n-AlGaAs layer 1204, the second semiconductor layer 1206, and the third semiconductor layer 1208 are the same as the first semiconductor layer 104, the second semiconductor layer 106, and the third semiconductor layer 108, respectively. However, examples where the third semiconductor layer 1208 is not doped or Si of 1 × 10 ¹⁶ [/ cm ³ ] or more is introduced. Each of these layers can be manufactured by epitaxial growth using the MOCVD method, as in the case of the semiconductor substrate 100. The conductivity type, impurity amount, thickness, and the like of each layer can be optimized with values required from device characteristics.

  FIG. 13 shows a cross-sectional example of a solar cell 1300 manufactured using a semiconductor substrate 1200. The second semiconductor layer 1206 can be exposed using the third semiconductor layer 1208 as an etching stopper. The solar cell 1300 can be manufactured by forming the cathode 1302 on the exposed second semiconductor layer 1206 and forming the anode 1304 on the p-GaAs layer 1212. In the solar cell 1300, since the exposed second semiconductor layer 1206 is etched well, the contact resistance between the second semiconductor layer 1206 and the cathode 1302 can be reduced.

FIG. 14 shows a cross-sectional example of the semiconductor substrate 1400. The semiconductor substrate 1400 can be used for manufacturing a light emitting diode or a laser diode. The semiconductor substrate 1400 includes a support substrate 1402, an n-AlGaAs layer 1404, a second semiconductor layer 1406, a third semiconductor layer 1408, an active layer 1410, a p-InGaP layer 1412, and a p-GaAs layer 1414. The support substrate 1402 is similar to the support substrate 102. The active layer 1410, the p-InGaP layer 1412, and the p-GaAs layer 1414 are similar to semiconductor crystal layers applicable to general light emitting diodes or laser diodes. The n-AlGaAs layer 1404, the second semiconductor layer 1406, and the third semiconductor layer 1408 are the same as the first semiconductor layer 104, the second semiconductor layer 106, and the third semiconductor layer 108, respectively. However, examples in which the third semiconductor layer 1408 is not doped or Si of 1 × 10 ¹⁶ [/ cm ³ ] or more is introduced. Each of these layers can be manufactured by epitaxial growth using the MOCVD method, as in the case of the semiconductor substrate 100. The conductivity type, impurity amount, thickness, and the like of each layer can be optimized with values required from device characteristics.

  FIG. 15 shows a cross-sectional example of a light emitting diode 1500 manufactured using a semiconductor substrate 1400. The second semiconductor layer 1406 can be exposed using the third semiconductor layer 1408 as an etching stopper. The light emitting diode 1500 can be manufactured by forming the cathode 1502 on the exposed second semiconductor layer 1406 and forming the anode 1504 on the p-GaAs layer 1414. The laser diode can be manufactured in the same manner as the light emitting diode. In the light emitting diode 1500, the exposed second semiconductor layer 1406 is etched well, so that the contact resistance between the second semiconductor layer 1406 and the cathode 1502 can be reduced. 12 to 15, a light receiving element and a light emitting element are disclosed as electronic elements, and it is disclosed that the second semiconductor layer is a semiconductor layer constituting the light receiving element or the light emitting element.

(Experimental example)
The first semiconductor layer 104, the second semiconductor layer 106, and the third semiconductor layer 108 shown in FIG. 1 were formed with the thickness (film thickness), Si concentration, and carbon concentration shown in Table 1. In Table 1 and the following description, the first semiconductor layer 104, the second semiconductor layer 106, and the third semiconductor layer 108 are referred to as a layer 104, a layer 106, and a layer 108, respectively.

That is, on the GaAs support substrate 102, a GaAs epitaxial layer as the layer 104, a GaAs epitaxial layer as the layer 106, and an In _0.48 Ga _0.52 P epitaxial layer as the layer 108 were formed by MOCVD. The layer 104 had a thickness of 500 nm and a Si concentration of 4 × 10 ¹⁸ [pieces / cm ³ ]. The layer 106 has a film thickness of 5 nm in Example 1, 10 nm in Example 2, and 20 nm in Example 3, a Si concentration of 4 × 10 ¹⁸ [pieces / cm ³ ], and a carbon concentration of 1.3 × 10 ^17. [Pieces / cm ³ ]. The carbon concentration is a ratio (V / III ratio) of arsine (AsH ₃ ), which is a source gas of atoms belonging to Group VB, and trimethylgallium (Ga (CH ₃ ) ₃ ), which is a source gas of atoms belonging to Group IIIB, to 1. .3 to adjust to the carbon concentration. The layer 108 had a thickness of 10 nm and a Si concentration of 3 × 10 ¹⁸ [pieces / cm ³ ].

As Comparative Example 1, a GaAs epitaxial layer as the layer 104 and an In _0.48 Ga _0.52 P epitaxial layer as the layer 108 were formed on the GaAs support substrate 102 by the MOCVD method. Example 1 is the same as Example 3 except that the second semiconductor layer 106 is not formed. As Comparative Example 2 and Comparative Example 3, a GaAs epitaxial layer as the layer 104, a GaAs epitaxial layer as the layer 106, and an In _0.48 Ga _0.52 P epitaxial layer as the layer 108 are _MOCVDed on the GaAs support substrate 102. Formed by the method. The carbon concentration introduced into the layer 106 is 8 × 10 ¹⁶ [pieces / cm ³ ] in the comparative example 1 and 4.5 × 10 ¹⁶ [pieces / cm ³ ] in the comparative example 2, and is carried out from the example 1. Same as Example 3.

For each sample of Example 1 to Example 3 and Comparative Example 1 to Comparative Example 3, the In _0.48 Ga _0.52 P epitaxial layer as the layer 108 was etched with hydrochloric acid. Then, the surface of the GaAs epitaxial layer which is the layer 106 (the GaAs epitaxial layer which is the layer 104 in the comparative example 1) was analyzed using an X-ray photoelectron spectroscopy (XPS) method. According to X-ray photoelectron spectroscopy, the degree of In and P remaining on the surface can be evaluated by the signal intensity ratio of In3d / Ga3d and the signal intensity ratio of P2p / As3d. Here, the XPS signal intensity ratio is obtained by converting the area ratio of each peak into a composition ratio using a sensitivity coefficient. Further, the GaAs epitaxial layer which is the layer 106 (the GaAs epitaxial layer which is the layer 104 in the comparative example 1) was etched with phosphoric acid, and the etching state of the surface was evaluated by the quality determination.

  As shown in Table 1, in Examples 1 to 3, the signal intensity ratio of In3d / Ga3d and the signal intensity ratio of P2p / As3d are smaller than those in Comparative Examples 1 to 3, and the In and P signal intensity ratios are smaller. It was found that there was little residue. Further, in Examples 1 to 3, it was found that the surface of phosphoric acid etching was better than in Comparative Examples 1 to 3, and no transition layer was formed.

  The execution order of each process such as operation, procedure, step, and stage in the apparatus and method shown in the claims, the description, and the drawings is clearly indicated as “before”, “prior”, etc. It should be noted that, unless the output of the previous process is used in the subsequent process, it can be realized in any order. Regarding the order of operations in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 102 Support substrate 104 First semiconductor layer made of arsenic compound 106 Second semiconductor layer made of arsenic compound 108 Third semiconductor layer made of phosphorus compound 120 AlGaAs layer 122 Mask 600 Semiconductor substrate 602 Support substrate 604 Buffer layer 606 Subcollector Layer 608 Second semiconductor layer made of arsenic compound 610 Third semiconductor layer made of phosphorus compound 612 Subcollector layer 614 Collector layer 616 Base layer 618 Subemitter layer 620 Emitter layer 800 Heterojunction bipolar transistor 802 Collector electrode 804 Base electrode 806 Emitter electrode 900 Semiconductor substrate 902 Support substrate 904 Buffer layer 906 Electron supply layer 908 Spacer layer 910 Channel layer 912 Spacer layer 914 Electron supply layer 916 Arsenic compound Second semiconductor layer made of 918 Third semiconductor layer made of phosphorus compound 920 Contact layer 1100 High electron mobility transistor 1102 Source electrode 1104 Drain electrode 1106 Gate electrode 1200 Semiconductor substrate 1202 Support substrate 1204 n-AlGaAs layer 1206 First layer made of arsenic compound 2 semiconductor layer 1208 third semiconductor layer made of phosphorus compound 1210 p-AlInGaP layer 1212 p-GaAs layer 1300 solar cell 1302 cathode 1304 anode 1400 semiconductor substrate 1402 support substrate 1404 n-AlGaAs layer 1406 second semiconductor layer 1408 made of arsenic compound Third semiconductor layer made of phosphorus compound 1410 Active layer 1412 p-InGaP layer 1414 p-GaAs layer 1500 Light emitting diode 1502 Cathode 504 anode

Claims (18)

A second semiconductor comprising an arsenic compound;
A third semiconductor composed of a phosphorus compound,
The second semiconductor and the third semiconductor are in contact;
The second semiconductor contains a first atom at a second concentration and contains a second atom;
The first atoms generate carriers of the first conductivity type in the second semiconductor;
The second concentration is a concentration equal to or higher than the concentration of the first atom, where the number of carriers that increase as the amount of the first atom doped into the second semiconductor increases,
The semiconductor substrate, wherein the second atom reduces a difference between a Fermi level and a charge neutral level in the second semiconductor. The semiconductor substrate according to claim 1, wherein the ionization energy of the second atom is 0.03 eV or less. The second semiconductor and the third semiconductor contain a third atom belonging to group IIIB;
The semiconductor substrate according to claim 1, wherein a binding energy between the second atom and the third atom is larger than a binding energy between the first atom and the third atom. The semiconductor substrate according to claim 3, wherein the third atom is Ga. A first semiconductor composed of an arsenic compound;
The second semiconductor is located between the first semiconductor and the third semiconductor;
The first semiconductor contains the first atom in a first concentration;
The first concentration is a concentration equal to or higher than the concentration of the first atom, in which the number of carriers that increase as the amount of the first atom doped into the first semiconductor increases increases. The semiconductor substrate in any one. The semiconductor substrate according to claim 1, wherein the first conductivity type is an N type. The second semiconductor is Al _x1 Ga _y1 As (x1 + y1 = 1, 0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1);
The semiconductor substrate according to claim 1, wherein the third semiconductor is In _x2 Ga _y2 P (x2 + y2 = 1, 0 ≦ x2 ≦ 1, 0 ≦ y2 ≦ 1). The first atom is one or more atoms selected from Si, Ge, Se and Te;
The semiconductor substrate according to claim 1, wherein the second atom is one or more atoms selected from C, B, Be, O, N, and F. The semiconductor substrate according to claim 1, wherein the second semiconductor contains the second atom having a concentration lower than the second concentration. The semiconductor substrate according to claim 9, wherein the second semiconductor contains the second atom at a concentration of 1 × 10 ¹⁷ [pieces / cm ³ ] or more. The second semiconductor is layered;
The semiconductor substrate according to any one of claims 1 to 10, wherein a thickness of the layered second semiconductor is 5 nm or more and 100 nm or less. Including a second semiconductor made of an arsenic compound and a third semiconductor made of a phosphorus compound,
The second semiconductor and the third semiconductor are in contact;
The second semiconductor contains N-type impurity atoms at a concentration of 4 × 10 ¹⁸ [pieces / cm ³ ] or more, and one or more atoms selected from C, B, Be, O, N, and F are 1 × A semiconductor substrate containing 10 ¹⁷ [pieces / cm ³ ] or more and 4 × 10 ¹⁸ [pieces / cm ³ ] or less. An electronic device comprising: an electronic element obtained by using, as an active region, one or more semiconductors selected from the third semiconductor and the second semiconductor in the semiconductor substrate according to claim 1. The electronic device according to claim 13, wherein the electronic element is a bipolar transistor, and the second semiconductor is a subcollector of the bipolar transistor. The electronic device according to claim 13, wherein the electronic element is a field effect transistor, and the second semiconductor is an electron supply layer of the field effect transistor. The electronic device according to claim 13, wherein the electronic element is a light receiving element or a light emitting element, and the second semiconductor is a semiconductor layer constituting the light receiving element or the light emitting element. Forming a second semiconductor made of an arsenic compound on the substrate, and forming a third semiconductor made of a phosphorus compound;
In the step of forming the second semiconductor, first atoms for generating carriers of the first conductivity type are introduced at a second concentration, and the difference between the Fermi level and the charge neutral level in the second semiconductor is reduced. Introducing a second atom to
Forming the third semiconductor in contact with the second semiconductor in the step of forming the third semiconductor;
The method of manufacturing a semiconductor substrate, wherein the second concentration is a concentration equal to or higher than the concentration of the first atoms, where the number of carriers that increase as the amount of the first atoms doped into the second semiconductor increases. A second semiconductor made of an arsenic compound and a third semiconductor made of a phosphorus compound, wherein the second semiconductor and the third semiconductor are in contact with each other, and the second semiconductor contains a first atom at a second concentration And containing a second atom, wherein the first atom generates carriers of the first conductivity type in the second semiconductor, and the second concentration is an amount of the first atom doped into the second semiconductor. A semiconductor substrate that has a concentration equal to or higher than the concentration of the first atom, where the increasing number of carriers starts to saturate, and the second atom reduces the difference between the Fermi level and the charge neutral level in the second semiconductor. And the stage of preparing
Etching any one semiconductor selected from the third semiconductor and the second semiconductor using the other semiconductor as an etching stop material;
Etching the other semiconductor. A method of manufacturing an electronic device.

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