CN103107096B - Method for producing silicon-based III-V group nMOS device - Google Patents
Method for producing silicon-based III-V group nMOS device Download PDFInfo
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- CN103107096B CN103107096B CN201310068781.3A CN201310068781A CN103107096B CN 103107096 B CN103107096 B CN 103107096B CN 201310068781 A CN201310068781 A CN 201310068781A CN 103107096 B CN103107096 B CN 103107096B
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Abstract
The invention discloses a method for producing a silicon-based III-V group nMOS device, which comprises the following steps of: step 1: growing a germanium layer on the silicon substrate; step 2: putting the grown germanium layer in a MOCVD reaction chamber, and growing into a low-temperature nucleation GaAs layer and a high-temperature GaAs layer respectively; step 3: stopping the growth, replacing the substrate jig and the reaction chamber tube, and growing a semi insulating InGaP layer on the high-temperature GaAs layer after high annealing for 30 minutes; step 4: growing a thin GaAs layer and a GaAs based nMOS structure on the semi insulating InGaP layer; and step 5: preparing a gate oxide, a source electrode, a grid electrode and a drain electrode, so as to complete the production of the silicon-based III-V group nMOS device.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to a kind of manufacture method of silica-based iii-v nMOS device.
Background technology
According to the prediction of international semiconductor industrial technology development blueprint (ITRS2009), the physical gate of MPU in 2012 is long will narrow down to 22 nanometers.But, along with integrated circuit technique develop into 22 nm technology node and following time, silicon integrated circuit technology will be subject to the restriction of a series of Basic Physical Problems and technology problem in speed, power consumption, integrated level, reliability etc., and the building of production line of costliness and manufacturing cost make IC industry face huge investment risk, traditional silicon CMOS technology adopt " minification " realize less, sooner, the development model of more cheap logical AND memory device has been difficult to continue.Therefore, ITRS clearly points out, " rear 22 nanometers " CMOS technology will adopt brand-new material, device architecture and integrated technology, and integrated circuit technique will face important technical in " the rear 22 nanometers " epoch and cross over and transition.
Much larger than silicon, (electron mobility of GaAs, InAs can reach 9000cm2/ (Vs), 40000cm2/ (Vs) to the electron mobility of Group III-V semiconductor respectively, and silicon only has 1300cm2/ (Vs)), they all have excellent electron transport performance under low field and High-Field, are the desired channel materials of ultrahigh speed, low-power consumption nMOS.In order to tackle the severe challenge that integrated circuit technique faces, adopt and replace silicon raceway groove, significantly to improve the switching speed of logical circuit and to realize foreword and the focus that low-power consumption work sutdy has become recent global microelectronic with the high mobility III-V group semi-conductor material of silicon technology compatibility.
The high-quality III-V group semi-conductor material of extension is the prerequisite of preparation Si base high mobility nMOS on a si substrate.GaAs studies comparatively ripe III-V group semi-conductor material.The lattice adaptation comparatively large (4.1%) of Si and GaAs, thermal mismatching is comparatively large (thermal coefficient of expansion of Si and GaAs is respectively 2.59 × 10-6K-1,5.75 × 10-6K-1) also, therefore can produce a large amount of dislocations when heteroepitaxy.Simultaneously, due to the existence of polar material extension and substrate level on non-polar substrate, a large amount of antiphase domain (Anti-phase domain can be produced in epitaxial loayer, APD), antiphase domain border (Anti-phaseboundary, APB) be scattering and the complex centre of charge carrier, introduce defect level in forbidden band simultaneously.These dislocations and antiphase domain border can extend to the surface of epitaxial loayer, have had a strong impact on the quality of epitaxial loayer.The growth of Si base III-V group semi-conductor material must solve this two problems.Meanwhile, for semi-insulated III-V substrate, its high resistivity makes it become the indispensable performance of high-speed microelectronic device.But be lack SI-substrate for another difficult problem Si base III-V high speed device.The resistivity that silicon substrate is higher generally reaches 103 ohmcms, apart from semi-insulated index 107 ohmcm, has differed four orders of magnitude, have impact on the performance of high speed device greatly.
Summary of the invention
For solving the problem, the invention provides a kind of solution of the silica-based high mobility iii-v nMOS device based on semi-insulating InGaP layer, namely the InGaP layer by mixing iron obtains semi-insulating layer, cut off substrate to exchange with the electric charge of top device, thus establish material foundation for traditional SI-GaAs substrate-based microelectronic component with being connected of silicon substrate.
The invention provides a kind of manufacture method of silica-based iii-v nMOS device, comprise the following steps,
Step 1: on a silicon substrate, growth of Germanium layers;
Step 2: the silicon substrate that grown germanium layer is put into MOCVD reative cell, respectively growing low temperature nucleation gallium arsenide layer and high temperature gallium arsenide layer;
Step 3: stop growing, changes substrate boat and reaction indoor pipe, after high annealing certain hour, and growing semi-insulated InGaP layer on high temperature gallium arsenide layer;
Step 4: grow thin gallium arsenide layer and GaAs based nMOS structure on semi-insulating InGaP layer;
Step 5: make gate oxide, source electrode, grid and drain electrode, complete the preparation of silica-based iii-v nMOS device.
Feature of the present invention is:
1, adopt germanium layer to be transitioned into III-V layer from silicon, then obtain high lattice quality by the gallium arsenide layer of low temperature;
2, adopt the InGaP layer mixing iron, obtain the iii-v layer of high resistant, the nMOS with is afterwards combined and obtains the effect of electric charge partition.
Accompanying drawing explanation
Fig. 1 is the schematic diagram in the present invention after silicon substrate epitaxial germanium layer;
Fig. 2 is the schematic diagram in the present invention after MOCVD epitaxy low temperature nucleation gallium arsenide layer and high temperature gallium arsenide layer;
Fig. 3 be in the present invention extension semi-insulating InGaP layer and thin gallium arsenide layer as the schematic diagram after cap rock;
Fig. 4 is the schematic diagram in the present invention after the GaAs based nMOS structure of extension;
Fig. 5 is the nMOS device schematic diagram after completing making in the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The invention discloses the manufacture method of a kind of silica-based iii-v nMOS, comprise the following steps,
Step 1: on cleaned silicon substrate 1, adopts the germanium layer 2 of ultra-high vacuum CVD growing high-quality, as shown in Figure 1;
Step 2: silicon substrate 1 is put into MOCVD reative cell immediately, respectively at low temperature and high growth temperature low temperature nucleation gallium arsenide layer 3 and high temperature gallium arsenide layer 4, as shown in Figure 2;
Step 3: after high temperature gallium arsenide layer 4 growth terminates, substrate boat and reaction indoor pipe are changed in cooling, to reduce the germanium atmosphere of reative cell; Keep high temperature, after annealing certain hour, preferably 30 minutes, at the growing semi-insulated InGaP layer 5 of high temperature gallium arsenide layer 4, this layer improves resistivity by mixing Fe source, as shown in Figure 3;
Step 4: grow thin gallium arsenide layer 6 as cap rock, as shown in Figure 3, and grows GaAs based nMOS structure 7, as shown in Figure 4;
Step 5: carry out the microelectronic techniques such as multistep etching, photoetching, makes gate oxide 8, source electrode 9, grid 10, and drain electrode 11, as shown in Figure 5, completes the preparation of nMOS device.
Wherein the succession of nMOS structure 7 comprises: Al0.3Ga0.7As barrier layer, In0.25Ga0.75As channel layer, In0.49Ga0.51P etching stop layer and GaAs doped contact layers.
In a preferred embodiment of the present invention, when using said method to prepare silica-based semi-insulating III-V material, select silicon (100) substrate in 4 °, [011] direction partially, the temperature of high annealing and growth high temperature gallium arsenide layer, semi-insulating InGaP layer are all identical, it is 620 DEG C, growing semi-insulated InGaP layer and germanium layer are Lattice Matchings, and its growth rate is 0.1nm/s, V/III is 75; Dopant when growing semi-insulated InGaP layer is ferrocene, and the ratio of the flow sum of III source TMIn and TMGa that its flow is used with semi-insulating InGaP layer is approximately 1: 1000, and the order of magnitude is 1 × 10
-8mol/min; Thin gallium arsenide layer thickness is 10nm.
In another preferred embodiment of the present invention, when using said method to prepare silica-based semi-insulating III-V material, select silicon (100) substrate in 4 °, [011] direction partially, the temperature of high annealing and growth high temperature gallium arsenide layer, semi-insulating InGaP layer are all identical, it is 660 DEG C, growing semi-insulated InGaP layer and germanium layer are Lattice Matchings, and its growth rate is 0.25nm/s, V/III is 125; Dopant when growing semi-insulated InGaP layer is ferrocene, and the ratio of the flow sum of III source TMIn and TMGa that its flow is used with semi-insulating InGaP layer is approximately 1: 1000, and the order of magnitude is 1 × 10
-8mol/min; Thin gallium arsenide layer thickness is 20nm.
In another preferred embodiment of the present invention, when using said method to prepare silica-based semi-insulating III-V material, select silicon (100) substrate in 4 °, [011] direction partially, the temperature of high annealing and growth high temperature gallium arsenide layer, semi-insulating InGaP layer are all identical, it is 650 DEG C, growing semi-insulated InGaP layer and germanium layer are Lattice Matchings, and its growth rate is 0.4nm/s, V/III is 100; Dopant when growing semi-insulated InGaP layer is ferrocene, and the ratio of the flow sum of III source TMIn and TMGa that its flow is used with semi-insulating InGaP layer is approximately 1: 1000, and the order of magnitude is 1 × 10
-8mol/min; Thin gallium arsenide layer thickness is 20nm.
The present invention provides high resistant or semi-insulating layer by the InGaP layer mixing iron.Ultra-high vacuum CVD is adopted to be transitioned into germanium layer from silicon substrate in the present invention, the strain of 4% is eliminated by the relaxation of bottom germanium, because the lattice mismatch of GaAs and germanium only has 800ppm, from germanium layer to GaAs, avoid the generation of misfit dislocation, adopt the cooperation of high/low temperature gallium arsenide layer to solve the problem on reverse farmland.Simultaneously in order to reach the object cutting off electric charge, adding semi-insulating layer InGaP, solving the parasitic capacitance effect of high-speed microelectronic device.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a manufacture method for silica-based iii-v nMOS device, comprises the following steps,
Step 1: on a silicon substrate, adopts ultra-high vacuum CVD growth of Germanium layers;
Step 2: the silicon substrate that grown germanium layer is put into MOCVD reative cell, respectively growing low temperature nucleation gallium arsenide layer and high temperature gallium arsenide layer;
Step 3: after the growth of high temperature gallium arsenide layer terminates, substrate boat and reaction indoor pipe are changed in cooling, after high annealing certain hour, growing semi-insulated InGaP layer on high temperature gallium arsenide layer; Wherein, when growing semi-insulated InGaP layer, dopant is ferrocene, and semi-insulating InGaP layer III source used is TMIn and TMGa; The flow of described dopant ferrocene is 1:1000 with the ratio of the flow sum of described TMIn and TMGa, and the order of magnitude is 1 × 10
-8mol/min;
Step 4: grow thin gallium arsenide layer and GaAs based nMOS structure on semi-insulating InGaP layer;
Step 5: make gate oxide, source electrode, grid and drain electrode, complete the preparation of silica-based iii-v nMOS device.
2. the manufacture method of silica-based iii-v nMOS device according to claim 1, is characterized in that, silicon substrate is (100) substrate in 4 °, [011] direction partially.
3. the manufacture method of silica-based iii-v nMOS device according to claim 1, it is characterized in that, the semi-insulating InGaP layer grown and described germanium layer are Lattice Matchings, and its growth rate is 0.1nm/s ~ 0.4nm/s, V/III is 75 ~ 125 molar flow ratios.
4. the manufacture method of silica-based iii-v nMOS device according to claim 1, is characterized in that, described thin gallium arsenide layer thickness is 10 ~ 20nm.
5. the manufacture method of silica-based iii-v nMOS device according to claim 1, it is characterized in that, described nMOS structure comprises: Al0.3Ga0.7As barrier layer, In0.25Ga0.75As channel layer, In0.49Ga0.51P etching stop layer and GaAs doped contact layers.
6. the manufacture method of silica-based iii-v nMOS device according to claim 1, is characterized in that, in step 3, the temperature of high annealing is identical with the temperature of growth high temperature gallium arsenide layer, semi-insulating InGaP layer, is 620 ~ 660 DEG C.
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| CN103390591B (en) | 2013-07-22 | 2015-11-25 | 中国科学院半导体研究所 | The CMOS preparation method of silica-based high mobility III-V/Ge raceway groove |
| CN103346092B (en) * | 2013-07-22 | 2015-12-09 | 中国科学院半导体研究所 | The surrounding-gate MOSFET preparation method of silica-based high mobility InGaAs raceway groove |
| CN107785418A (en) * | 2016-08-25 | 2018-03-09 | 西北大学 | Based on LRC technique Ge PMOS devices and preparation method thereof |
| CN107452682A (en) * | 2016-08-25 | 2017-12-08 | 西北大学 | Laser crystallization Ge cmos devices and preparation method thereof again |
| CN107452681A (en) * | 2016-08-25 | 2017-12-08 | 西北大学 | Laser crystallization GeNMOS devices and preparation method thereof again |
| CN108565209A (en) * | 2018-05-22 | 2018-09-21 | 北京工业大学 | A kind of GaAs epitaxial films and its preparation method and application based on SOI substrate |
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| CN102842578A (en) * | 2011-06-23 | 2012-12-26 | 寇平公司 | Bipolar high electron mobility transistor and methods of forming same |
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