CN102534768B - Method for preparing silicon-based gallium arsenide material - Google Patents
Method for preparing silicon-based gallium arsenide material Download PDFInfo
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- CN102534768B CN102534768B CN201210032751.2A CN201210032751A CN102534768B CN 102534768 B CN102534768 B CN 102534768B CN 201210032751 A CN201210032751 A CN 201210032751A CN 102534768 B CN102534768 B CN 102534768B
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Abstract
The invention discloses a method for preparing a silicon-based gallium arsenide material. The method comprises the following steps of: growing a silicon dioxide layer on a silicon substrate 1; and etching a groove on the silicon dioxide layer along the <110> direction of the silicon substrate by a holographic exposure method and an inductively coupled plasma (ICP) method; cleaning by using piranha, SC2, HF and deionized water, and removing the residual silicon dioxide layer at the bottom of the groove to expose the silicon substrate; by a metal-organic chemical vapor deposition (MOCVD) method, growing a first buffer layer in the groove, and growing a second buffer layer on the first buffer layer in the groove, wherein the thickness of the second buffer layer is greater than that of the silicon dioxide layer; growing a third buffer layer on the second buffer layer and the silicon dioxide layer, and growing a top layer on the third buffer layer; doping each layer with SiH4; and polishing the top layer by a chemical mechanical polishing method to obtain the material, wherein the roughness of the polished material is less than 1nm. By the method, high-quality silicon-based gallium arsenide material can be prepared, substrate basis is established for a silicon-based gallium arsenide material device, and specifically, a feasible scheme is provided for a high-mobility microelectronic device and solving the problem about silicon-based luminescence.
Description
Technical field
The present invention relates to a kind of a kind of method preparing silicon-based gallium arsenide material MOCVD and selective area epitaxial combined.
Background technology
The preparation of silica-based Group III-V compound semiconductor material starts from the eighties in last century, and is the Focal point and difficult point of heteroepitaxy always.Particularly enter 21 century, along with the development of microelectronics and photoelectronic industry, prepare high-quality silica-based Group III-V compound semiconductor material and become particularly important.
Integrated circuit technique based on silicon CMOS technology is followed Moore's Law and is improved operating rate, the increase integrated level of chip by the characteristic size of reduction of device and reduce costs, the characteristic size of integrated circuit evolves to nanoscale by micro-meter scale, achieves huge economic benefit and scientific and technical major progress.According to the prediction of international semiconductor industrial technology development blueprint (ITRS2009), the physical gate of MPU in 2012 is long will narrow down to 22 nanometers.But, along with integrated circuit technique develop into 22 nm technology node and following time, silicon integrated circuit technology will be subject to the restriction of a series of Basic Physical Problems and technology problem in speed, power consumption, integrated level, reliability etc., and the building of production line of costliness and manufacturing cost make IC industry face huge investment risk, traditional silicon CMOS technology adopt " minification " realize less, sooner, the development model of more cheap logical AND memory device has been difficult to continue.Therefore, ITRS clearly points out, " rear 22 nanometers " CMOS technology will adopt brand-new material, device architecture and integrated technology, and integrated circuit technique will face important technical in " the rear 22 nanometers " epoch and cross over and transition.
Much larger than silicon, (electron mobility of GaAs, InAs can reach 9000cm to the electron mobility of Group III-V semiconductor respectively
2/ (Vs), 40000cm
2/ (Vs), and silicon only has 1300cm
2/ (Vs)), they all have excellent electron transport performance under low field and High-Field, are the desired channel materials of ultrahigh speed, low-power consumption nMOS.In order to tackle the severe challenge that integrated circuit technique faces, adopt and replace silicon raceway groove, significantly to improve the switching speed of logical circuit and to realize foreword and the focus that low-power consumption work sutdy has become recent global microelectronic with the high mobility III-V group semi-conductor material of silicon technology compatibility.
Meanwhile, silicon materials, as the basis of microelectric technique, are the semi-conducting materials of the most extensively research; The maturity of silicon processing technique is far above Group III-V compound semiconductor material.But silicon base luminescence problem is never solved well.Consider the photoelectron technology of the maturation based on GaAs, InP substrate, the preparation of silica-based Group III-V compound semiconductor laser is the feasible scheme solving silicon-based optical interconnection problem.
The high-quality III-V group semi-conductor material of extension is the prerequisite of preparation Si base microelectronic component and luminescent device on a si substrate.GaAs studies comparatively ripe III-V material, and this method adopts GaAs to study extension problem as the representative of III-V.The lattice mismatch comparatively large (4.1%) of Si and GaAs, thermal mismatching is comparatively large, and (thermal coefficient of expansion of Si and GaAs is respectively 2.59 × 10
-6k
-1, 5.75 × 10
-6k
-1), therefore can produce a large amount of dislocations when heteroepitaxy.Simultaneously, due to the existence of polar material extension and substrate level on non-polar substrate, a large amount of antiphase domain (Anti-phase domain can be produced in epitaxial loayer, APD), antiphase domain border (Anti-phase boundary, APB) be scattering and the complex centre of charge carrier, introduce defect level in forbidden band simultaneously.These dislocations and antiphase domain border can extend to the surface of epitaxial loayer, have had a strong impact on the quality of epitaxial loayer.The growth of Si base III-V material must address these problems.
Adopt tert-butyl group dihydro arsenic and triethyl-gallium to replace arsine and the trimethyl gallium of employing usually in this method, reduce growth temperature, reduce growth rate, promote the generation from elimination effect of APB; Meanwhile, adopt high-aspect-ratio restriction technologies, utilize the SiO of AR > 1
2groove limits adaptive dislocation and APB.The decomposition temperature of tert-butyl group dihydro arsenic and triethyl-gallium, far below arsine and trimethyl gallium, therefore can carry out the epitaxial growth of material at a lower temperature, and lower temperature can limit the issue of inter-diffusion at Si and GaAs interface.Adopt MOCVD method, at SiO
2in groove, extension GaAs is along { 311} and { crystal face (being parallel to the direction of groove) of 111} class composition carries out growing, the misfit dislocation of Si/GaAs interface, and APD extends along with the direction of growth of epitaxial loayer.Like this, when these misfit dislocations and APD run into SiO
2just stopped during wall, the GaAs of top layer can not be extended to.And change epitaxial conditions when the GaAs monocrystalline grown in adjacent silica trench meets, form good combination, obtain the silica-based GaAs monocrystal thin films of fabricating low-defect-density.
Summary of the invention
The object of the invention is to, a kind of method preparing silicon-based gallium arsenide material is provided, the method can prepare high-quality Si base GaAs material, and for substrate basis established by Si base GaAs device, particularly high migration microelectronic component and solution silicon base luminescence provide a kind of feasible program.The method, by feed change and in conjunction with high aspect ratio trench quite restriction technologies, inhibits the extension of GaAs/Si interface misfit dislocation and APD epitaxial layers; Effectively can control nucleation with the control of low growth rate twice, thus obtain high-quality silicon-based gallium arsenide material.
The invention provides a kind of method preparing silicon-based gallium arsenide material, comprise the following steps:
Step 1: grow silicon dioxide layer on silicon substrate 1;
Step 2: adopt holographic exposure and the <110> direction of ICP method along silicon substrate on silicon dioxide layer to etch groove;
Step 3: use piranha, SC respectively
2, HF and washed with de-ionized water, the remaining silicon dioxide layer of removing channel bottom, exposes silicon substrate;
Step 4: the method adopting MOCVD, first in groove, grow the first resilient coating, the first resilient coating then in groove grows the second resilient coating, and its thickness exceeds silicon dioxide layer; Then growth regulation three buffer layer on the second resilient coating and silicon dioxide layer, then grows top layer on three buffer layer; Each layer adopts SiH
4doping;
Step 5: the method adopting chemico-mechanical polishing, by top layer polishing, the roughness after polishing is less than 1nm, completes the preparation of material.
Feature of the present invention is:
1, with the methods combining that metal-organic chemical vapor extension and high aspect ratio trench quite limit, at the high-quality GaAs epitaxially deposited layer of Si substrate growth, the misfit dislocation at GaAs/Si interface and antiphase domain border is made to terminate in SiO
2on wall.
2, by changing growth raw material, reducing growth temperature, other parameters such as Optimal Growing speed, reducing the defect of heterogeneous interface, improve the quality of epitaxial loayer.
3, the control of growth conditions, especially bradyauxesis step are the key steps controlling defect.
Accompanying drawing explanation
For further illustrating concrete technology contents of the present invention, be described in detail as follows below in conjunction with example and accompanying drawing, wherein:
Fig. 1-Fig. 7 is the flow chart that the present invention prepares silicon-based gallium arsenide material method.
Embodiment
Refer to Fig. 1 to Fig. 7, the invention provides a kind of method preparing silicon-based gallium arsenide material, comprise the following steps:
Step 1: grow silicon dioxide layer 2 on silicon substrate 1, wherein, silicon substrate 1 is n-type low-resistance (001) silicon, and resistivity is at 0.01-0.1 ohmcm, and the thickness of silicon dioxide layer 2 is 500nm-600nm.
Step 2: adopt holographic exposure and the <110> direction of ICP method along silicon substrate 1 on silicon dioxide layer 2 to etch groove 3; wherein the width of groove 3 is 200-300nm; the degree of depth is identical with the thickness of silicon dioxide layer 2, and the silicon dioxide layer 2 of about the 10nm that this groove is left is the infringement in order to protect silicon substrate not etched.The object that preparation depth-to-width ratio is greater than the groove of 2 changes Material growth direction, suppresses dislocation and reverse farmland.
Step 3: use piranha, SC respectively
2, HF and washed with de-ionized water, remaining silicon dioxide layer 2 bottom removing groove 3, exposes silicon substrate 1.
Step 4: the method adopting MOCVD, chamber pressure is 100mBar, when growing each layer GaAs material, using tert-butyl group dihydro arsenic and triethyl-gallium as raw material, in growth course the input molar flow of tert-butyl group dihydro arsenic and triethyl-gallium than V/III between 10 and 30.First in groove 3, grow the first resilient coating 4, growth temperature is between 450-550 DEG C, and growth rate is 0.1-0.5nm/s, and growth thickness is 150 to 200nm; Then the first resilient coating 4 in groove 3 grows the second resilient coating 5, and growth temperature is between 600-650 DEG C, and growth rate is 0.8-1.2nm/s, and growth thickness is higher than the degree of depth of groove 3, and the second resilient coating 5 in adjacent trenches 3 does not combine; Then growth regulation three buffer layer 6 on the second resilient coating 5 and silicon dioxide layer 2, the condition of three buffer layer 6 controls to be emphasis, object is in order to the GaAs material of adjacent trenches 3 is combined into single crystalline layer, then on three buffer layer 6, grow top layer 7, three buffer layer 6 is identical with the first resilient coating 4, second resilient coating 5 respectively with the growth conditions of top layer 7; The growth thickness of three buffer layer 6 and top layer 7 is respectively 200nm-300nm, 300nm-500nm.Each layer adopts SiH
4doping, obtains the carrier concentration of each layer in 5-10 × 10
17cm
-3.
Step 5: the method adopting chemico-mechanical polishing, by top layer 7 polishing, the roughness after polishing is less than 1nm, completes the preparation of material.
Above-described specific embodiment; more detailed specific description has been carried out to object of the present invention, technical scheme and beneficial effect; be understood that; above-describedly be only specific embodiments of the invention; be not limited to the present invention; all in spirit of the present invention, thought and spirit, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. prepare a method for silicon-based gallium arsenide material, comprise the following steps:
Step 1: grow silicon dioxide layer on a silicon substrate;
Step 2: adopt holographic exposure and the <110> direction of ICP method along silicon substrate on silicon dioxide layer to etch groove;
Step 3: use piranha, SC respectively
2, HF and washed with de-ionized water, the remaining silicon dioxide layer of removing channel bottom, exposes silicon substrate;
Step 4: the method adopting MOCVD, first in groove, grow the first resilient coating, the first resilient coating then in groove grows the second resilient coating, and its thickness exceeds silicon dioxide layer; Then growth regulation three buffer layer on the second resilient coating and silicon dioxide layer, then grows top layer on three buffer layer; Each layer adopts SiH
4doping, the material of this first resilient coating is GaAs, and the material of the second resilient coating is GaAs, and its thickness exceeds silicon dioxide layer; The material of three buffer layer is GaAs, and the material of top layer is GaAs;
When wherein growing the first resilient coating in groove, growth temperature is between 450-550 DEG C, and growth rate is 0.1-0.5nm/s, and growth thickness is 150 to 200nm;
When wherein growing the second resilient coating on the first resilient coating, growth temperature is between 600-650 DEG C, and growth rate is 0.8-1.2nm/s, and growth thickness is higher than the degree of depth of groove, and the second resilient coating in adjacent trenches does not combine;
Wherein the growth conditions of three buffer layer and top layer is identical with the first resilient coating, the second resilient coating respectively; The growth thickness of three buffer layer and top layer is respectively 200nm-300nm, 300nm-500nm;
Step 5: the method adopting chemico-mechanical polishing, by top layer polishing, the roughness after polishing is less than 1nm, completes the preparation of material.
2. the method preparing silicon-based gallium arsenide material according to claim 1, wherein silicon substrate is n-type low-resistance (001) silicon, and resistivity is at 0.01-0.1 ohmcm.
3. the method preparing silicon-based gallium arsenide material according to claim 1, wherein the width of groove is 200300nm, and the degree of depth is identical with the thickness of silicon dioxide layer.
4. the method preparing silicon-based gallium arsenide material according to claim 1, wherein the thickness of silicon dioxide layer is 500nm 600nm.
5. the method preparing silicon-based gallium arsenide material according to claim 1, wherein adopt the method for MOCVD, its pressure is 100mBar, using tert-butyl group dihydro arsenic and triethyl-gallium as raw material, in growth course the input molar flow of tert-butyl group dihydro arsenic and triethyl-gallium than V/III between 10 and 30.
6. the method preparing silicon-based gallium arsenide material according to claim 1, wherein SiH
4doping make the carrier concentration of each layer in 5-10 × 10
17cm
-3.
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| CN104465918B (en) * | 2014-10-31 | 2017-06-27 | 华灿光电(苏州）有限公司 | A kind of LED epitaxial slice and preparation method thereof |
| CN106435721A (en) * | 2016-09-22 | 2017-02-22 | 东莞市联洲知识产权运营管理有限公司 | GaAs/Si epitaxial material preparation method |
| CN111146320A (en) * | 2018-11-02 | 2020-05-12 | 华为技术有限公司 | Silicon-based substrate, substrate base plate and manufacturing method thereof, and photoelectric device |
| CN114300556B (en) * | 2021-12-30 | 2024-05-28 | 中国科学院苏州纳米技术与纳米仿生研究所 | Epitaxial structure, epitaxial growth method and photoelectric device |
| CN118404492A (en) * | 2024-07-01 | 2024-07-30 | 万华化学集团电子材料有限公司 | Polishing pad and preparation method and application thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102160145A (en) * | 2008-09-19 | 2011-08-17 | 台湾积体电路制造股份有限公司 | Formation of devices by epitaxial layer overgrowth |
| CN102263015A (en) * | 2011-07-22 | 2011-11-30 | 中国科学院半导体研究所 | Method for preparing silica-based gallium arsenide material structure applied to n-channel metal oxide semiconductor (nMOS) |
-
2012
- 2012-02-14 CN CN201210032751.2A patent/CN102534768B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102160145A (en) * | 2008-09-19 | 2011-08-17 | 台湾积体电路制造股份有限公司 | Formation of devices by epitaxial layer overgrowth |
| CN102263015A (en) * | 2011-07-22 | 2011-11-30 | 中国科学院半导体研究所 | Method for preparing silica-based gallium arsenide material structure applied to n-channel metal oxide semiconductor (nMOS) |
Non-Patent Citations (1)
| Title |
|---|
| Defect reduction of GaAs/Si epitaxy by aspect ratio trapping;J.Z.Li et al;《JOURNAL OF APPLIED PHYSICS》;20080519;第103卷;106102 * |
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