CN107785418A - Based on LRC technique Ge PMOS devices and preparation method thereof - Google Patents

Based on LRC technique Ge PMOS devices and preparation method thereof Download PDF

Info

Publication number
CN107785418A
CN107785418A CN201610726484.7A CN201610726484A CN107785418A CN 107785418 A CN107785418 A CN 107785418A CN 201610726484 A CN201610726484 A CN 201610726484A CN 107785418 A CN107785418 A CN 107785418A
Authority
CN
China
Prior art keywords
layers
layer
laser
crystallization
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610726484.7A
Other languages
Chinese (zh)
Inventor
汪霖
张万绪
彭瑶
刘成
陈晓璇
姜博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northwest University
Original Assignee
Northwest University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northwest University filed Critical Northwest University
Priority to CN201610726484.7A priority Critical patent/CN107785418A/en
Publication of CN107785418A publication Critical patent/CN107785418A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

The present invention relates to one kind based on LRC technique Ge PMOS devices and preparation method thereof.This method includes：Si substrates are chosen, grow Ge inculating crystal layers；Grow Ge body layers；Deposit SiO2Material；Backing material is heated to 700 DEG C, continuously uses whole backing material described in laser technology crystallization, wherein, optical maser wavelength 808nm, spot size 10mm × 1mm, power 1.5kW/cm2, translational speed 25mm/s, form crystallization Ge layers；Etch SiO2Material；Grow gate dielectric layer；Grow grid layer；Source-drain area is formed, ultimately forms PMOS device.PMOS device provided by the invention is that crystallization (Laser Re Crystallization, abbreviation LRC) technique is realized again by using laser, can effectively reduce the dislocation density of Ge/Si void substrates；Crystallization process selectivity is high again for continuous laser, acts only on Ge epitaxial layers, control is accurate, avoids the problem of Si Ge mutually expand；Crystallization process auxiliary prepares Ge/Si void substrates to continuous laser again, and crystallization rate is fast, thus also has the advantages of processing step is simple, and process cycle is short, and heat budget is low.

Description

Based on LRC technique Ge PMOS devices and preparation method thereof
Technical field
It is more particularly to a kind of to be based on LRC technique Ge PMOS devices and its preparation the present invention relates to technical field of integrated circuits Method.
Background technology
Since Jack Kilby in 1958 have invented first piece of integrated circuit, integrated circuit is always with Moore laws Advance, i.e., open ended transistor size on integrated circuit, will double within about every 18 months, performance boost one Times, and price reduction half.Until today, Moore laws, which still play, to be acted on.
It is continuous however as the further development of microelectric technique, the continuous diminution of device feature size, the speed of circuit Speeding, the physics limit such as static leakage, short-channel effect, power dissipation density increase, mobil-ity degradation makes device performance constantly deteriorate, Its physics of the gradual convergence of IC chip and technological limits, traditional Si base device and integrated circuit gradually show its defect and deficiency, So that Si base integrated circuit techniques are difficult to continue development according still further to Moore's Law to go down.
Therefore, under current technological level, to continue to Moore laws development, it is necessary to study new device structure, New device material, exploitation new device technique are explored, so as to improve constantly the performance of device and integrated circuit.To PMOS device For, a kind of method for effectively solving these physical problems and technological challenge is undoubtedly using new channel material.
In recent years, as the development of epitaxy technology, Si base Ge materials cause the extensive concern of people.In order to improve Si bases Device hole mobility, device channel can be done using Ge materials.Because Ge materials have larger carrier mobility, it is empty Cave mobility is 4.2 times of Si materials, and be it is higher in all semiconductors, particularly can with existing Si process compatibles, The advantages such as preparation method is simple, it has also become the emphasis and focus of present semicon industry research and development.
PMOS, on a si substrate typically epitaxial growth Ge are made using Ge materials, then PMOS device is made.However, Ge Material differs larger with the lattice constant of Si materials, and lattice mismatch is up to 4.2%, is easily formed in Si bases Ge epitaxial thin-film layer Higher surface roughness and higher dislocation density, which greatly limits the performance of PMOS device.Therefore, using on Si substrates The technique for preparing high quality Ge epitaxial layers makes PMOS, is one of hot subject researched and solved in semiconductor applications.
The content of the invention
Therefore, to solve technological deficiency and deficiency existing for prior art, the present invention proposes that one kind is based on LRC techniques Ge PMOS device and preparation method thereof.
Specifically, a kind of preparation method based on LRC technique Ge PMOS devices that one embodiment of the invention proposes, bag Include：
S101, choose single crystal Si substrate；
S102, at a temperature of 275 DEG C~325 DEG C, grow 40~50nm's on the single crystal Si substrate using CVD techniques First Ge inculating crystal layers；
S103, at a temperature of 500 DEG C~600 DEG C, using CVD techniques the first Ge seed crystal surfaces grow 150 ~250nm the 2nd Ge body layers；
S104, using CVD techniques 150nm SiO are deposited in the 2nd Ge main body layer surfaces2Layer；
S105, the single crystal Si substrate, the first Ge inculating crystal layers, the 2nd Ge body layers and described will be included SiO2The whole backing material of layer is heated to 700 DEG C, continuously uses whole backing material described in laser technology crystallization, wherein, swash Light wave a length of 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s；
The whole backing material of S106, natural cooling；
S107, utilize the dry etch process etching SiO2Layer, obtains the Ge/Si void backing material；
S108, at a temperature of 500~600 DEG C, using CVD epitaxy techniques in the Ge/Si void substrate surface deposition thickness For 900~950nm N-type Ge layers, doping concentration is 1 × 1016~5 × 1016cm-3；
S109, at a temperature of 250~300 DEG C, use atomic layer deposition processes the N-type Ge layer surfaces deposition thickness for 2~3nm HfO2Material；
S110, using electron beam evaporation process in the HfO2Material surface deposition thickness is 10~20nm Al-Cu materials Material；
S111, the Al-Cu materials using etching technics quarter selective eating away designated area and the HfO2Material shape Into PMOS gate regions；
S112, using self-registered technology, carry out boron ion injection in whole substrate surface, at a temperature of 250~300 DEG C, Rapid thermal annealing 30s in a nitrogen environment, form PMOS source drain region；
S113, the BPSG formation dielectric layers using CVD techniques in whole substrate surface deposition thickness for 200~300nm；
S114, utilize BPSG formation source and drain contact hole described in nitric acid and hf etching；
S115, the metal W material shape using electron beam evaporation process in whole substrate surface deposition thickness for 10~20nm Contacted into source and drain；
S116, the metal W using etching technics quarter selective eating away designated area, and carried out using CMP works at planarization Reason；
S117, using CVD techniques in the SiN that whole substrate surface deposition thickness is 20~30nm to form described be based on LRC technique Ge PMOS devices.
One kind that another embodiment of the present invention proposes is based on LRC technique Ge PMOS devices, including：Single crystal Si substrate, One Ge inculating crystal layers, the 2nd Ge body layers, N-type Ge layers, HfO2Layer and Al-Cu layers；Wherein, the PMOS device is by above-described embodiment Described method prepares to be formed.
A kind of preparation method based on LRC technique Ge PMOS devices that further embodiment of the present invention proposes, including：
Choose single crystal Si substrate；
At the first temperature, in the Ge inculating crystal layers of Si Growns the first；
At the second temperature, in the Ge body layers of the first Ge seed crystal surfaces growth regulation two；
SiO is deposited in the 2nd Ge main body layer surfaces2Material；
Whole backing material is heated to 700 DEG C, continuously uses whole backing material described in laser technology crystallization, wherein, Optical maser wavelength is 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/ S, form crystallization Ge layers；
Etch the SiO2Material, obtain Ge/Si void backing materials；
N-type Ge layers are grown in the Ge/Si void substrate material surface；
Gate dielectric layer, grid layer are grown in the N-type Ge layer surfaces, etching forms grid；
Source and drain injection is carried out using self-registered technology, forms source-drain area, ultimately forms and described is based on LRC technique Ge PMOS Device.
In one embodiment of the invention, the first temperature is 275 DEG C~325 DEG C, and second temperature is 500 DEG C~600 DEG C.
In one embodiment of the invention, N-type Ge layers are grown in the Ge/Si void substrate material surface, including：
At a temperature of 500~600 DEG C, the N-type Ge is deposited in the Ge/Si void substrate surface using CVD epitaxy techniques Layer.
In one embodiment of the invention, gate dielectric layer, grid layer are grown in the N-type Ge layer surfaces, etching is formed Grid, including：
In the N-type Ge layer surfaces using atomic layer deposition processes deposit HfO2Material, form the gate dielectric layer；
Using electron beam evaporation process in the HfO2Material surface deposits Al-Cu materials；
The Al-Cu materials of selective eating away designated area and the HfO are carved using etching technics2Material forms described Grid.
In one embodiment of the invention, formed after source-drain area, in addition to：
Using CVD techniques dielectric layer is formed in whole substrate surface deposit BPSG；
Source and drain contact hole is formed using BPSG described in nitric acid and hf etching；
Using electron beam evaporation process source and drain contact is formed in whole substrate surface deposit metal W；
The metal W of selective eating away designated area is carved using etching technics.
In one embodiment of the invention, after the metal W that selective eating away designated area is carved using etching technics, also Including：
Planarization process is carried out to whole substrate using CMP；
Using CVD techniques SiN materials are deposited in substrate surface.
One kind that another embodiment of the invention proposes is based on LRC technique Ge PMOS devices, including：Si substrates, the first Ge Inculating crystal layer, the 2nd Ge body layers, crystallization Ge layers, N-type Ge layers, gate dielectric layer and grid layer；Wherein, the PMOS device is by by upper The method described in embodiment is stated to prepare to be formed.
Above-described embodiment, the present invention use laser crystallization (Laser Re-Crystallization, abbreviation LRC) technique again I.e. by the continuous laser thin Ge/Si void substrate of crystallization again, the dislocation density of Ge/Si void substrates can be effectively reduced；Continuous laser is again Crystallization process selectivity is high, acts only on Ge epitaxial layers, control is accurate, avoids the problem of Si-Ge mutually expands；Continuous laser is brilliant again Chemical industry skill auxiliary prepares Ge/Si void substrates, and crystallization rate is fast, thus also simple with processing step, and process cycle is short, heat budget The advantages of low.
Based on this, the present invention possesses following advantage：
1st, based on Ge/Si void substrates prepare Ge materials formation PMOS device, preparation technology with existing Si process compatibles, There is fairly obvious advantage in terms of technique manufactures, reduces cost；
2nd, for the present invention by continuous laser auxiliary crystallization Ge/Si void substrates, the dislocation that can effectively reduce Ge/Si void substrates is close Degree and surface roughness.Continuous laser crystallization process selectivity is high, acts only on Ge epitaxial layers, is easy to control accurate；
3rd, for the present invention using Ge materials as PMOS device raceway groove, its carrier mobility is significantly higher than Si carrier mobilities, Device operating rate is high, frequency characteristic is good.
By the detailed description below with reference to accompanying drawing, other side of the invention and feature become obvious.But it should know Road, the accompanying drawing is only the purpose design explained, not as the restriction of the scope of the present invention, because it should refer to Appended claims.It should also be noted that unless otherwise noted, it is not necessary to which scale accompanying drawing, they only try hard to concept Ground illustrates structure and flow described herein.
Brief description of the drawings
Below in conjunction with accompanying drawing, the embodiment of the present invention is described in detail.
Fig. 1 is a kind of process flow diagram based on LRC technique Ge PMOS devices provided in an embodiment of the present invention；
Fig. 2 is a kind of schematic diagram of laser crystallization technique provided in an embodiment of the present invention；
Fig. 3 is the phase transition temperature relation schematic diagram in a kind of thin film actuated light irradiation process provided in an embodiment of the present invention；
Fig. 4 is that a kind of FEM Numerical Simulation of technique of Ge/Si void backing material provided in an embodiment of the present invention is illustrated Figure；
Fig. 5 is a kind of continuous laser provided in an embodiment of the present invention crystallization process effect diagram again；
Fig. 6 a- Fig. 6 n are a kind of schematic diagram based on LRC technique Ge PMOS device techniques provided in an embodiment of the present invention.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention Embodiment be described in detail.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of technological process based on LRC technique Ge PMOS devices provided in an embodiment of the present invention Schematic diagram.This method comprises the following steps：
Step a, single crystal Si substrate is chosen；
Step b, at the first temperature, in the Ge inculating crystal layers of Si Growns the first；
Step c, at the second temperature, in the Ge body layers of the first Ge seed crystal surfaces growth regulation two；
Step d, SiO is deposited in the 2nd Ge main body layer surfaces2Material；
Step e, whole backing material is heated to 700 DEG C, continuously uses whole backing material described in laser technology crystallization, Wherein, optical maser wavelength 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed is 25mm/s, form crystallization Ge layers；
Step f, the SiO is etched2Material, obtain Ge/Si void backing materials；
Step g, N-type Ge layers are grown in the Ge/Si void substrate material surface；
Step h, gate dielectric layer, grid layer are grown in the N-type Ge layer surfaces, etching forms grid；
Step i, source and drain injection is carried out using self-registered technology, forms source-drain area, ultimately formed and described be based on LRC techniques Ge PMOS device.
In step b and step c, the first temperature is 275 DEG C~325 DEG C, and second temperature is 500 DEG C~600 DEG C.
Wherein, step g can include：
At a temperature of 500~600 DEG C, the N-type Ge is deposited in the Ge/Si void substrate surface using CVD epitaxy techniques Layer
Wherein, step h can include：
Step h1, in the N-type Ge layer surfaces using atomic layer deposition processes deposit HfO2Material, form the gate medium Layer；
Step h2, using electron beam evaporation process in the HfO2Material surface deposits Al-Cu materials；
Step h3, the Al-Cu materials of selective eating away designated area and the HfO are carved using etching technics2Material Form the grid.
In step i, formed after source-drain area, in addition to：
Step j, dielectric layer is formed in whole substrate surface deposit BPSG using CVD techniques；
Step k, source and drain contact hole is formed using BPSG described in nitric acid and hf etching；
Step l, source and drain contact is formed in whole substrate surface deposit metal W using electron beam evaporation process；
Step m, the metal W of selective eating away designated area is carved using etching technics.
Further, after step m, can include：
Step n, planarization process is carried out to whole substrate using CMP；
Step o, SiN materials are deposited in substrate surface using CVD techniques.
The present invention working principle and beneficial effect be specially：
Relaxation Ge cushion relative maturities are prepared on Si substrates, and most common method is two-step growth method.This method First low-temperature epitaxy a thin layer Ge, suppresses the island growth caused by big lattice mismatch.Afterwards again outside high growth temperature main body Ge Prolong layer.Compared with traditional graded buffer layer growth method, graded layer thickness is this approach reduce, and cause Ge epi-layer surfaces Roughness significantly reduces.
But two-step growth method still can not solve the appearance of a large amount of helical dislocations in Ge epitaxial layers, so also often needing to tie Cycle annealing technique is closed to reduce Ge epitaxial layer threading dislocation densities.However, cycle annealing technique is only applicable to several micron thickness Ge epitaxial layers, for thin Ge epitaxial layers, it may appear that Si-Ge exclusive problems.In addition, the introducing of cycle annealing technique is subtracting While small dislocation density, the increase of Ge/Si buffer-layer surface roughness is also resulted in.Meanwhile also there is technique week in this method The shortcomings of phase is grown, and heat budget is high.
The essence for being difficult to acquisition low-dislocation-density Ge/Si void substrates is due to that the misfit dislocation between Si and Ge is big, interface Dislocation defects can extend longitudinally to Ge surface during epitaxial layer progressive additive, and then cause Ge/Si void substrate crystals Quality reduces.Therefore, in order to eliminate dislocation defects caused by longitudinal extension, the fast speed heats of Ge/Si can be used to melt the side of recrystallization Method, the dislocation mismatch between Ge and Si is laterally discharged, and then obtain the Ge/Si void substrates of high quality.
Therefore, referring to Fig. 2, Fig. 2 is a kind of schematic diagram of laser crystallization technique provided in an embodiment of the present invention.First use magnetic Control sputtering technology or CVD techniques form thin Ge epitaxial layers through two-step method, then laterally discharge Ge and Si with continuous laser crystallization Between dislocation mismatch, so as to reduce the dislocation caused by lattice mismatch in epitaxial layer, it is empty to prepare Ge/Si best in quality Substrate.
Fig. 3 is referred to, Fig. 3 is that the phase transition temperature in a kind of thin film actuated light irradiation process provided in an embodiment of the present invention closes It is schematic diagram；The invention is characterized in that continuous laser crystallization.The principle of laser crystallization is the high-energy using laser to material Material surface transient heating is allowed to melt crystallization, and its essence is the process of thermal induced phase transition, and this point also has with traditional laser thermal anneal Essential distinction.Therefore, laser crystallization can be regarded as fuel factor of the laser to film, i.e. laser will be illuminated by fuel factor Film melts, and the process of crystallization is allowed to cool in the shorter time.Laser crystallization is broadly divided into following three phases：
1) interaction stage of laser and material.This stage material absorbing laser energy is changed into heat energy, reaches fusing State.During high-order harmonics spectrum, the electric property of material, optical property, constructional aspect etc. change.
2) the heat transfer stage of material.According to thermodynamics basic law, laser action in will occur on material conduction, it is right Three kinds of heat transfer types of stream and radiation, now firing rate is fast, and thermograde is big.
3) mass transfer stage of the material under laser action.Mass transfer, i.e. material move to separately from a certain position in space or space The phenomenon at one position.In this stage, the particle setting in motion through laser emission acquisition energy.Two kinds of forms be present in mass transfer：Diffusion Mass transfer and convective mass transfer.What diffusion mass transfer represented is the microscopic motion of atom or molecule；Convective mass transfer is then the macroscopic view fortune of fluid It is dynamic.Exemplified by melting crystallization mechanism completely, the temperature variations of laser crystallization rear film are as shown in Figure 3.
Using laser, crystallization LRC technologies auxiliary prepares high quality void Ge substrates again, it is desirable to empty Ge layers temperature under laser action At least up to fusing point, and close proximity to scorification point, reach the nearly complete molten condition of preferable crystallization, ensure the follow-up complete of Ge crystal grain U.S.'s crystallization.Meanwhile the Si substrate layers below epitaxial layer can not reach fusing point, it ensure that laser crystallization does not have an impact to substrate. Accordingly, it is determined that rational laser crystallization related process parameters (such as laser power density, translational speed), control epitaxial layer temperature Distribution, will be the key of the technique success or failure.Fig. 4 is referred to, Fig. 4 is a kind of Ge/Si void substrate material provided in an embodiment of the present invention The FEM Numerical Simulation schematic diagram of the technique of material.In figure, ordinate represents Ge/Si system thickness, in Ge epitaxy layer thickness Laser traverse speed is used on 200nm Ge/Si void substrates as 25mm/s, laser power 1.5kW/cm2Process conditions can be real Existing Ge melts crystallization and Si does not melt.
Fig. 5 is referred to, Fig. 5 is a kind of continuous laser provided in an embodiment of the present invention crystallization process effect diagram again.This Invention can use 808nm semiconductor lasers such as to complete laser crystallization process again.Laser is pointed into sample by total reflection prism Platform, and by convex lens focus to sample, so as to prevent the liquid after film melts in thermal histories to be affected by gravity And flow on influence caused by crystallization.Laser again crystallization when, stepper motor drive sample stage movement, be often moved to a position and enter Laser irradiation of row, makes the position turn into the blockage with high-energy, then stops laser irradiation, sample stage is moved to down Laser irradiation is further continued for during one position.So circulation causes laser to be irradiated to whole film surface successively, so far completes continuously to swash Light crystallization process again.
The present embodiment, by above-mentioned processing technology, at least possesses following advantage：
1) present invention is first using magnetron sputtering or the method for CVD techniques, the empty linings of Ge/Si obtained by two-step method Bottom, material surface roughness is good, and the high cost of deposition rate is low, and large-scale production potentiality are big；
2) present invention aids in crystallization Ge/Si void substrate again by continuous laser, can effectively reduce the dislocation of Ge/Si void substrates Density.Continuous laser crystallization process selectivity is high, acts only on Ge epitaxial layers, and control is accurate；Simultaneously with conventional furnace annealing technique Compare, crystallization rate is fast, thus also has the advantages of processing step is simple, and process cycle is short, and heat budget is low；
3) for the present invention using Ge materials as PMOS device raceway groove, its carrier mobility is significantly higher than Si carrier mobilities, Device operating rate is high, frequency characteristic is good.
In addition, it is necessary to emphasize, laser of the invention crystallization (Laser Re-Crystallization, letter again Claiming LRC) technique and laser annealing (laser annealing) technique has significant difference.Laser annealing technique, belong to thermal annealing work Skill category.It uses laser only to heat to semiconductor as thermal source, do not produce phase transition process.And laser of the present invention Again in crystallization process processing procedure, phase transformation twice can occur for semi-conducting material -- melt the solid-phase crystallization again that liquefies then.Thus, Technique has significant difference in itself both this.
Embodiment two
It is a kind of laser provided in an embodiment of the present invention crystallization Ge PMOS devices again to refer to Fig. 6 a- Fig. 6 n, Fig. 6 a- Fig. 6 n The schematic diagram of part technique.This method includes：
S101, such as Fig. 6 a, choose single crystal Si substrate 001；
S102, such as Fig. 6 b, at a temperature of 275 DEG C~325 DEG C, grow 40 on the single crystal Si substrate using CVD techniques ~50nm the first Ge inculating crystal layers 002；
S103, such as Fig. 6 b, at a temperature of 500 DEG C~600 DEG C, using CVD techniques in the first Ge seed crystal surfaces 150~250nm the 2nd Ge body layers 002 are grown (for the ease of checking in figure, by the first Ge inculating crystal layers and the 2nd Ge body layers It is unified for numbering 002)；
S104, such as Fig. 6 c, 150nm SiO are deposited in the 2nd Ge main body layer surfaces using CVD techniques2Layer 003；
S105, the single crystal Si substrate, the first Ge inculating crystal layers, the 2nd Ge body layers and the SiO will be included2 The whole backing material of layer is heated to 700 DEG C, continuously uses whole backing material described in laser technology crystallization, wherein, laser wave A length of 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s；
The whole backing material of S106, natural cooling；
S107, such as Fig. 6 d, the SiO is etched using dry etch process2Layer 003, obtains the Ge/Si void substrate material Material；
S108, such as Fig. 6 e, at a temperature of 500~600 DEG C, formed sediment using CVD epitaxy techniques in the Ge/Si void substrate surface The N-type Ge layers 004 that product thickness is 900~950nm, doping concentration are 1 × 1016~5 × 1016cm-3；
S109, such as Fig. 6 f, at a temperature of 250~300 DEG C, formed sediment using atomic layer deposition processes in the N-type Ge layer surfaces Product thickness is 2~3nm HfO2Material 005；
S110, such as Fig. 6 g, using electron beam evaporation process in the HfO2Material surface deposition thickness is 10~20nm's Al-Cu materials 006；
S111, such as Fig. 6 h, the Al-Cu materials 006 that selective eating away designated area is carved using etching technics are formed PMOS gate regions；
S112, such as Fig. 6 i, using self-registered technology, boron ion injection is carried out in whole substrate surface, at 250~300 DEG C At a temperature of, rapid thermal annealing 30s, forms PMOS source drain region 007 in a nitrogen environment；
S113, such as Fig. 6 j, using CVD techniques in the BPSG materials that whole substrate surface deposition thickness is 200~300nm 008 forms dielectric layer；Moving iron can be captured by mixing BPSG, and device performance is damaged to prevent them to be diffused into grid；
S114, such as Fig. 6 k, source and drain contact hole is formed using BPSG materials 008 described in nitric acid and hf etching；
S115, such as Fig. 6 l, using electron beam evaporation process in the metal W that whole substrate surface deposition thickness is 10~20nm Material 009 forms source and drain contact；
S116, such as Fig. 6 m, the metal W material 009 of selective eating away designated area is carved using etching technics, and utilizes CMP Work carries out planarization process；
S117, such as Fig. 6 n, using CVD techniques whole substrate surface deposition thickness be 20~30nm SiN materials 010 with Formation is based on LRC technique Ge PMOS devices.
In summary, specific case used herein is based on LRC technique Ge PMOS devices and its preparation side to the present invention The principle and embodiment of method are set forth, the explanation of above example be only intended to help the method for understanding the present invention and its Core concept；Meanwhile for those of ordinary skill in the art, according to the thought of the present invention, in embodiment and application There will be changes in scope, in summary, this specification content should not be construed as limiting the invention, guarantor of the invention Shield scope should be defined by appended claim.

Claims (9)

  1. A kind of 1. preparation method based on LRC technique Ge PMOS devices, it is characterised in that including：
    S101, choose single crystal Si substrate；
    S102, at a temperature of 275 DEG C~325 DEG C, the first of 40~50nm is grown on the single crystal Si substrate using CVD techniques Ge inculating crystal layers；
    S103, at a temperature of 500 DEG C~600 DEG C, using CVD techniques the first Ge seed crystal surfaces grow 150~ 250nm the 2nd Ge body layers；
    S104, using CVD techniques 150nm SiO are deposited in the 2nd Ge main body layer surfaces2Layer；
    S105, the single crystal Si substrate, the first Ge inculating crystal layers, the 2nd Ge body layers and the SiO will be included2Layer Whole backing material is heated to 700 DEG C, continuously uses whole backing material described in laser technology crystallization, wherein, optical maser wavelength is 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s；
    The whole backing material of S106, natural cooling；
    S107, utilize the dry etch process etching SiO2Layer, obtains the Ge/Si void backing material；
    S108, at a temperature of 500~600 DEG C, using CVD epitaxy techniques the Ge/Si void substrate surface deposition thickness be 900 ~950nm N-type Ge layers, doping concentration are 1 × 1016~5 × 1016cm-3；
    S109, at a temperature of 250~300 DEG C, use atomic layer deposition processes the N-type Ge layer surfaces deposition thickness for 2~ 3nm HfO2Material；
    S110, using electron beam evaporation process in the HfO2Material surface deposition thickness is 10~20nm Al-Cu materials；
    S111, the Al-Cu materials using etching technics quarter selective eating away designated area and the HfO2Material forms PMOS Gate regions；
    S112, using self-registered technology, boron ion injection is carried out in whole substrate surface, at a temperature of 250~300 DEG C, in nitrogen Rapid thermal annealing 30s under compression ring border, form PMOS source drain region；
    S113, the BPSG formation dielectric layers using CVD techniques in whole substrate surface deposition thickness for 200~300nm；
    S114, utilize BPSG formation source and drain contact hole described in nitric acid and hf etching；
    S115, the metal W material formation source using electron beam evaporation process in whole substrate surface deposition thickness for 10~20nm Drain contact；
    S116, the metal W using etching technics quarter selective eating away designated area, and utilize CMP works to carry out planarization process；
    S117, using CVD techniques described it is based on LRC works in the SiN that whole substrate surface deposition thickness is 20~30nm to be formed Skill Ge PMOS devices.
  2. 2. one kind is based on LRC technique Ge PMOS devices, it is characterised in that including：Single crystal Si substrate, the first Ge inculating crystal layers, second Ge body layers, N-type Ge layers, HfO2Layer and Al-Cu layers；Wherein, the PMOS device prepares shape as the method described in claim 1 Into.
  3. A kind of 3. preparation method based on LRC technique Ge PMOS devices, it is characterised in that including：
    Choose single crystal Si substrate；
    At the first temperature, in the Ge inculating crystal layers of Si Growns the first；
    At the second temperature, in the Ge body layers of the first Ge seed crystal surfaces growth regulation two；
    SiO is deposited in the 2nd Ge main body layer surfaces2Material；
    Whole backing material is heated to 700 DEG C, continuously uses whole backing material described in laser technology crystallization, wherein, laser Wavelength is 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s, shape Into crystallization Ge layers；
    Etch the SiO2Material, obtain Ge/Si void backing materials；
    N-type Ge layers are grown in the Ge/Si void substrate material surface；
    Gate dielectric layer, grid layer are grown in the N-type Ge layer surfaces, etching forms grid；
    Source and drain injection is carried out using self-registered technology, forms source-drain area, ultimately forms and described is based on LRC technique Ge PMOS devices.
  4. 4. according to the method for claim 3, it is characterised in that the first temperature is 275 DEG C~325 DEG C, second temperature 500 DEG C~600 DEG C.
  5. 5. according to the method for claim 3, it is characterised in that in Ge/Si void substrate material surface growth N-type Ge Layer, including：
    At a temperature of 500~600 DEG C, the N-type Ge layers are deposited in the Ge/Si void substrate surface using CVD epitaxy techniques.
  6. 6. according to the method for claim 3, it is characterised in that grow gate dielectric layer, grid in the N-type Ge layer surfaces Layer, etching form grid, including：
    In the N-type Ge layer surfaces using atomic layer deposition processes deposit HfO2Material, form the gate dielectric layer；
    Using electron beam evaporation process in the HfO2Material surface deposits Al-Cu materials；
    The Al-Cu materials of selective eating away designated area and the HfO are carved using etching technics2Material forms the grid.
  7. 7. according to the method for claim 3, it is characterised in that formed after source-drain area, in addition to：
    Using CVD techniques dielectric layer is formed in whole substrate surface deposit BPSG；
    Source and drain contact hole is formed using BPSG described in nitric acid and hf etching；
    Using electron beam evaporation process source and drain contact is formed in whole substrate surface deposit metal W；
    The metal W of selective eating away designated area is carved using etching technics.
  8. 8. according to the method for claim 7, it is characterised in that the gold of selective eating away designated area is carved using etching technics After belonging to W, in addition to：
    Planarization process is carried out to whole substrate using CMP；
    Using CVD techniques SiN materials are deposited in substrate surface.
  9. 9. one kind is based on LRC technique Ge PMOS devices, it is characterised in that including：Si substrates, the first Ge inculating crystal layers, the 2nd Ge master Body layer, crystallization Ge layers, N-type Ge layers, gate dielectric layer and grid layer；Wherein, the PMOS device is by any one of claim 3~8 Described method prepares to be formed.
CN201610726484.7A 2016-08-25 2016-08-25 Based on LRC technique Ge PMOS devices and preparation method thereof Pending CN107785418A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610726484.7A CN107785418A (en) 2016-08-25 2016-08-25 Based on LRC technique Ge PMOS devices and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610726484.7A CN107785418A (en) 2016-08-25 2016-08-25 Based on LRC technique Ge PMOS devices and preparation method thereof

Publications (1)

Publication Number Publication Date
CN107785418A true CN107785418A (en) 2018-03-09

Family

ID=61438619

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610726484.7A Pending CN107785418A (en) 2016-08-25 2016-08-25 Based on LRC technique Ge PMOS devices and preparation method thereof

Country Status (1)

Country Link
CN (1) CN107785418A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090224285A1 (en) * 2003-09-09 2009-09-10 Sang Han THREADING-DISLOCATION-FREE NANOHETEROEPITAXY OF Ge ON Si USING SELF-DIRECTED TOUCH-DOWN OF Ge THROUGH A THIN SiO2 LAYER
CN101866835A (en) * 2010-05-19 2010-10-20 中国科学院半导体研究所 Method for preparing high-germanium-content germanium-silicon virtual substrate
CN102163619A (en) * 2010-02-19 2011-08-24 三星电子株式会社 Methods of manufacturing transistors
CN103107096A (en) * 2013-03-05 2013-05-15 中国科学院半导体研究所 Method for producing silicon-based III-V group nMOS device
CN105244320A (en) * 2015-08-28 2016-01-13 西安电子科技大学 SOI-based CMOS integrated device with strain Ge channel and inverted trapezoidal grid and preparation method of integrated device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090224285A1 (en) * 2003-09-09 2009-09-10 Sang Han THREADING-DISLOCATION-FREE NANOHETEROEPITAXY OF Ge ON Si USING SELF-DIRECTED TOUCH-DOWN OF Ge THROUGH A THIN SiO2 LAYER
CN102163619A (en) * 2010-02-19 2011-08-24 三星电子株式会社 Methods of manufacturing transistors
CN101866835A (en) * 2010-05-19 2010-10-20 中国科学院半导体研究所 Method for preparing high-germanium-content germanium-silicon virtual substrate
CN103107096A (en) * 2013-03-05 2013-05-15 中国科学院半导体研究所 Method for producing silicon-based III-V group nMOS device
CN105244320A (en) * 2015-08-28 2016-01-13 西安电子科技大学 SOI-based CMOS integrated device with strain Ge channel and inverted trapezoidal grid and preparation method of integrated device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
彭英才，赵新为，傅广生: "《硅基纳米光电子技术》", 30 April 2009, 河北大学出版社 *
黄志伟等: "《激光退火改善Si外延Ge晶体质量》", 《第十一届全国硅基光电子材料及器件研讨会》 *

Similar Documents

Publication Publication Date Title
Wang et al. Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method
Prucnal et al. Doping by flash lamp annealing
TWI384556B (en) Microwave activation annealing process
CN102498552B (en) Methods of solid phase recrystallization of thin film using pulse train annealing method
CN104752419B (en) Integrated circuit and its manufacture method
Huet et al. Laser thermal annealing: A low thermal budget solution for advanced structures and new materials
CN107452681A (en) Laser crystallization GeNMOS devices and preparation method thereof again
CN107785418A (en) Based on LRC technique Ge PMOS devices and preparation method thereof
CN107785454A (en) GeSn photodetectors based on Ge/Si void substrates and preparation method thereof
Choi et al. Study of phosphorus-doped Si annealed by a multi-wavelength laser
Fiory Rapid thermal processing for silicon nanoelectronics applications
Alvarez Alonso et al. Optimization of solid-phase epitaxial regrowth performed by UV nanosecond laser annealing
CN107818978A (en) Strain GeSn nmos devices and preparation method thereof
CN107785408A (en) Ge/Si void backing materials and preparation method thereof
CN107452682A (en) Laser crystallization Ge cmos devices and preparation method thereof again
Ram et al. Performance investigation of single grain boundary junctionless field effect transistor
Morimoto et al. An advanced 405-nm laser diode crystallization method of a-Si film for fabricating microcrystalline-Si TFTs
CN103733306B (en) For manufacture the method and apparatus of layer at semi-conducting material
CN107785234A (en) Strain Ge based on Si substrates1‑xSnxThin-film material and preparation method thereof
Fan et al. An Emerging Local Annealing Method for Simultaneous Crystallization and Activation in Xtacking 3-D NAND Flash
Huet Laser annealing applications for semiconductor devices manufacturing
Semiconductor Mosfets
Tabata et al. 3D Simulation for Melt Laser Anneal Integration in FinFET’s Contact
Xuehao et al. Research progress of excimer laser annealing in semiconductor integrated circuit manufacturing
CN107845686A (en) PMOS device based on SiGe

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20180309

RJ01 Rejection of invention patent application after publication