CN103123932B - Semiconductor device - Google Patents
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- CN103123932B CN103123932B CN201210458371.5A CN201210458371A CN103123932B CN 103123932 B CN103123932 B CN 103123932B CN 201210458371 A CN201210458371 A CN 201210458371A CN 103123932 B CN103123932 B CN 103123932B
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Abstract
The invention provides and a kind ofly work under normally off and possess the semiconductor device of high withstand voltage and low on-resistance.In semiconductor device (1), drain electrode (21) is configured to be electrically connected with the Two-dimensional electron gas-bearing formation being formed at the first heterojunction interface (32), source electrode (29) is configured to be configured to can be electrically connected with the Two-dimensional electron gas-bearing formation being formed at the second heterojunction interface (34) with the Two-dimensional electron gas-bearing formation electric insulation being formed at the first heterojunction interface (32), gate portion (28) and the second heterojunction interface (34) are in opposite directions, conduction electrode (25) is configured to be electrically connected with the Two-dimensional electron gas-bearing formation being formed at the first heterojunction interface (32) and both the Two-dimensional electron gas-bearing formations being formed at the second heterojunction interface (34).The electron concentration that the electron concentration ratio being formed at the Two-dimensional electron gas-bearing formation of the first heterojunction interface (32) is formed at the Two-dimensional electron gas-bearing formation of the second heterojunction interface (34) is large.
Description
Technical field
The present invention relates to the semiconductor device with heterojunction.
Background technology
Developing the semiconductor device of the Two-dimensional electron gas-bearing formation of the heterojunction interface being formed at the different electron transit layer in forbidden band and electron supply layer at present.In this semiconductor device, electric current flows between the drain and source via Two-dimensional electron gas-bearing formation.Preset gate portion between the drain and source, according to the magnitude of current that the voltage control applied this gate portion is moved at two-dimensional electron gas laminar flow.One of such semiconductor device example is disclosed in patent documentation 1.
Patent documentation
Patent documentation 1:(Japan) JP 2007-96203 publication
Summary of the invention
In this semiconductor device, work under being desirably in normally off and possess low on-resistance and height is withstand voltage.Such as, in order to make to work under normally off, by the reduced thickness of electron supply layer, by known for technology thinning for the electron concentration of Two-dimensional electron gas-bearing formation.When utilizing this technology by time thinning for the electron concentration of Two-dimensional electron gas-bearing formation, when not applying voltage to gate portion, can make to disappear with gate portion Two-dimensional electron gas-bearing formation in opposite directions.Thus, semiconductor device can be made to work under normally off.
But, when the electron concentration of Two-dimensional electron gas-bearing formation is thinning, also thinning with the electron concentration of the Two-dimensional electron gas-bearing formation beyond gate portion part in opposite directions, therefore, there is the problem that conducting resistance increases.Especially obtain high withstand voltage, need the distance between drain electrode and source electrode to increase, its result is, also elongated with the distance of the Two-dimensional electron gas-bearing formation beyond gate portion part in opposite directions, the problem that conducting resistance increases will become remarkable.
Technical purpose disclosed in present specification is to provide a kind of and works under normally off and possess the semiconductor device of high withstand voltage and low on-resistance.
Semiconductor device feature disclosed in this specification is to be provided with two heterojunction interfaces.The electron concentration of the Two-dimensional electron gas-bearing formation being formed at a heterojunction interface is adjusted to relatively dense, the electron concentration of the Two-dimensional electron gas-bearing formation being formed at another heterojunction interface is adjusted to relatively thin.Be adjusted to relatively thin heterojunction interface with the electron concentration of Two-dimensional electron gas-bearing formation and gate portion is set in opposite directions.Thus, achieve and work under normally off.And, in this semiconductor device, utilize the electron concentration of Two-dimensional electron gas-bearing formation to be adjusted to relatively dense heterojunction interface, guarantee the distance between drain electrode and source electrode.Therefore, can guarantee to drain and distance between source electrode and obtain high withstand voltage, and the increase of conducting resistance can be suppressed.Like this, semiconductor device disclosed in this specification, by utilizing two heterojunction interfaces, can work and possess high withstand voltage and low on-resistance under normally off.
That is, semiconductor device disclosed in this specification possesses semiconductor multilayer body, drain electrode, source electrode, gate portion and conduction electrode.Drain electrode is located on semiconductor multilayer body.Source electrode is located on semiconductor multilayer body, and leaves configuration from drain electrode.Gate portion is located on semiconductor multilayer body, and is configured between drain electrode and source electrode.In addition, gate portion also can be insulated gate electrode type, also can be Schottky type.Conduction electrode is located on semiconductor multilayer body, and is located between drain electrode and gate portion.Semiconductor multilayer body has the first semiconductor layer, the second semiconductor layer, the 3rd semiconductor layer and the 4th semiconductor layer.First semiconductor layer is different with the forbidden band of the second semiconductor layer, forms the first heterojunction interface by the first semiconductor layer and the second semiconductor layer.3rd semiconductor layer is different with the forbidden band of the 4th semiconductor layer, forms the second heterojunction interface by the 3rd semiconductor layer and the 4th semiconductor layer.Drain electrode is configured to be electrically connected with the Two-dimensional electron gas-bearing formation being formed at the first heterojunction interface.Source electrode is configured to the Two-dimensional electron gas-bearing formation electric insulation being formed at the first heterojunction interface, and to be configured to be electrically connected with the Two-dimensional electron gas-bearing formation being formed at the second heterojunction interface.Gate portion and the second heterojunction interface are in opposite directions.Conduction electrode is configured to be electrically connected with the Two-dimensional electron gas-bearing formation being formed at the first heterojunction interface and both the Two-dimensional electron gas-bearing formations being formed at the second heterojunction interface.The electron concentration being formed at the Two-dimensional electron gas-bearing formation of the first heterojunction interface is larger than the electron concentration of the Two-dimensional electron gas-bearing formation being formed at the second heterojunction interface.In the semiconductor device of aforesaid way, electric current flows between drain electrode and source electrode via the first heterojunction interface, conduction electrode and the second heterojunction interface.The second heterojunction interface being adjusted to relative thin with the electron concentration of Two-dimensional electron gas-bearing formation is provided with gate portion in opposite directions.Thus, realize working under normally off.And, in the semiconductor device of aforesaid way, be adjusted to the first relatively dense heterojunction interface by the electron concentration of Two-dimensional electron gas-bearing formation, guarantee that the distance between drain electrode and source electrode is longer.Therefore, can guarantee to drain and distance between source electrode longer and obtain high withstand voltage, and the increase of conducting resistance can be suppressed.Like this, the semiconductor device of aforesaid way can work and possess high withstand voltage and low on-resistance under normally off.
The semiconductor device of aforesaid way also can also possess auxiliary grid portion.Auxiliary grid portion is located on semiconductor multilayer body, and is located between drain electrode and conduction electrode.The mode that when auxiliary grid portion is not applied to voltage with gate portion, this auxiliary grid portion is not applied to voltage is formed.In the semiconductor device of aforesaid way, when gate portion is not applied to voltage, auxiliary grid portion is also not applied to voltage.Thus, auxiliary grid portion, when semiconductor device disconnects, utilizes field plate effect to relax the electric field of drain electrode and conduction electrode.In addition, auxiliary grid portion can be insulated gate electrode type, also can be Schottky type.
First semiconductor layer, the second semiconductor layer, the 3rd semiconductor layer and the 4th semiconductor layer also can be stacked according to this order.In the semiconductor device of which, the first heterojunction and the second heterojunction through-thickness are formed abreast.
The forbidden band of the second semiconductor layer also can be wider than the forbidden band of the first semiconductor layer.And the forbidden band of the 4th semiconductor layer also can be wider than the forbidden band of the 3rd semiconductor layer.The semiconductor device of which is by by alternately laminated for relative with forbidden band for layer relatively narrow for forbidden band wide layer and formed.
Drain electrode also can be filled in and be formed in the first groove of semiconductor multilayer body.By adjusting the degree of depth of the first groove, the electrical connection of drain electrode and the first heterojunction interface can be realized simply.
Conduction electrode also can be filled in and be formed in the second groove of semiconductor multilayer body.By adjusting the degree of depth of the second groove, the electrical connection of conduction electrode and the first heterojunction interface and the electrical connection of conduction electrode and the second heterojunction interface can be realized simply.
Invention effect
According to technology disclosed in this specification, can provide a kind of and work under normally off and possess the semiconductor device of high withstand voltage and low on-resistance.
Accompanying drawing explanation
Fig. 1 schematically shows the important part profile of the semiconductor device of embodiment;
Fig. 2 A represents one of the equivalent circuit diagram of the semiconductor device of embodiment example;
Fig. 2 B represents another example of the equivalent circuit diagram of the semiconductor device of embodiment;
Fig. 3 represents the glide path of the electric current flowed in the semiconductor device of embodiment.
Symbol description
10: semiconductor multilayer body
11: substrate
12: resilient coating
13: the first semiconductor layers
14: the second semiconductor layers
15: the three semiconductor layers
16: the four semiconductor layers
21: drain electrode
22: the first grooves
23: auxiliary grid portion
24: the second grooves
25: conduction electrode
28: gate portion
29: source electrode
32: the first heterojunction interfaces
34: the second heterojunction interfaces
Embodiment
Arrange the feature of technology disclosed in this specification below.
Disclosed in (fisrt feature) this specification, technology is not defined for the material of semiconductor device.Typically, nitride based compound semiconductor is used to be desirable.Such as, it is desirable that the semi-conducting material of the first semiconductor layer is In
xaga
yaal
1-Xa-Yan(0≤Xa≤1,0≤Ya≤1,0≤Xa+Ya≤1), the semi-conducting material of the second semiconductor layer is In
xbga
ybal
1 -Xb-Ybn(0≤Xb≤1,0≤Yb≤1,0≤Xb+Yb≤1), (1-Xa-Ya) < (1-Xb-Yb).In addition, it is desirable that the semi-conducting material of the 3rd semiconductor layer is In
xcga
ycal
1-Xc-Ycn(0≤Xc≤1,0≤Yc≤1,0≤Xc+Yc≤1), the semi-conducting material of the 4th semiconductor layer is In
xdga
ydal
1-Xd-Ydn(0≤Xd≤1,0≤Yd≤1,0≤Xd+Yd≤1), (1-Xc-Yc) < (1-Xd-Yd).
In technology disclosed in (second feature) this specification, the electron concentration being formed at the Two-dimensional electron gas-bearing formation of the first heterojunction interface of the first semiconductor layer and the second semiconductor layer is adjusted to larger than the electron concentration of the Two-dimensional electron gas-bearing formation of the second heterojunction interface being formed at the 3rd semiconductor layer and the 4th semiconductor layer.Such as, in order to embody, it is desirable that the thickness of Thickness Ratio second semiconductor layer of the 4th semiconductor layer is thin.In addition, it is desirable that the ratio of components of the aluminium of the 4th semiconductor layer is less than the ratio of components of the aluminium of the second semiconductor layer.Particularly desirably, by these Feature Combinations.
The degree of depth of the first groove that (third feature) drain electrode is filled does not limit especially, but in one example, it is desirable that its through 4th semiconductor layer and the 3rd semiconductor layer.More preferably, the first grooves extend second semiconductor layer and arrive the first semiconductor layer.
The degree of depth of the second groove that (fourth feature) conduction electrode is filled does not limit especially, but in one example, it is desirable that its through 4th semiconductor layer and the 3rd semiconductor layer.More preferably, the second grooves extend second semiconductor layer and arrive the first semiconductor layer.
[embodiment]
As shown in Figure 1, semiconductor device 1 possesses semiconductor multilayer body 10.Semiconductor multilayer body 10 has substrate 11, resilient coating 12, first semiconductor layer 13, second semiconductor layer 14, the 3rd semiconductor layer 15, the 4th semiconductor layer 16.Resilient coating 12, first semiconductor layer 13, second semiconductor layer 14, the 3rd semiconductor layer 15, the 4th semiconductor layer 16 are laminated in that order on substrate 11.
The material of the crystallizable growth of semi-conducting material that the materials'use of substrate 11 is nitride based.
In one example, the materials'use gallium nitride of substrate 11, sapphire, carborundum or silicon.
The materials'use undoped gallium nitride (GaN) of resilient coating 12.
Resilient coating 12 utilizes organometallic vapor deposition method (MOCVD:Metal OrganicChemical Vapor Deposition) to be laminated at low temperatures on substrate 11.
The materials'use undoped gallium nitride (GaN) of the first semiconductor layer 13.First semiconductor layer 13 utilizes organometallic vapor deposition method to be laminated on resilient coating 12.It is desirable that the thickness of the first semiconductor layer 13 is about 1 ~ 2 μm.In one example, the thickness of the first semiconductor layer 13 is about 1.5 μm.
The materials'use undoped aluminium gallium nitride alloy (AlGaN) of the second semiconductor layer 14.It is desirable that the ratio of components of the aluminium of the second semiconductor layer 14 is about 10 ~ 30%, its thickness is about 10 ~ 100nm.In one example, the ratio of components of the aluminium of the second semiconductor layer 14 is about 25%, and its thickness is about 25nm.Second semiconductor layer 14 utilizes organometallic vapor deposition method to be laminated on the first semiconductor layer 13.The forbidden band of the second semiconductor layer 14 is larger than the forbidden band of the first semiconductor layer 13.Therefore, two-dimensional electron gas (2DEG) is formed at the first heterojunction interface 32 of the first semiconductor layer 13 and the second semiconductor layer 14.
The materials'use undoped gallium nitride (GaN) of the 3rd semiconductor layer 15.It is desirable that the thickness of the 3rd semiconductor layer 15 is about 0.02 ~ 2 μm.In one example, the thickness of the 3rd semiconductor layer 15 is about 40nm.3rd semiconductor layer 15 utilizes organometallic vapor deposition method to be laminated on the second semiconductor layer 14.
The aluminium gallium nitride alloy (AlGaN) of the materials'use undoped of the 4th semiconductor layer 16.It is desirable that the ratio of components of the aluminium of the 4th semiconductor layer 16 is about 5 ~ 30%, its thickness is about 2 ~ 50nm.In one example, the ratio of components of the aluminium of the 4th semiconductor layer 16 is about 10%, and its thickness is about 5nm.4th semiconductor layer 16 utilizes organometallic vapor deposition method to be laminated on the 3rd semiconductor layer 15.The forbidden band of the 4th semiconductor layer 16 is larger than the forbidden band of the 3rd semiconductor layer 15.Therefore, two-dimensional electron gas (2DEG) is formed at the second heterojunction interface 34 of the 3rd semiconductor layer 15 and the 4th semiconductor layer 16.
As mentioned above, if compare the second semiconductor layer 14 and the 4th semiconductor layer 16, so the thickness of the second semiconductor layer 14 is formed relatively thick.And if compare the second semiconductor layer 14 and the 4th semiconductor layer 16, the ratio of components of the aluminium so contained by the second semiconductor layer 14 is adjusted to relatively large.Its result is, being formed at the first semiconductor layer 13 is adjusted to relative dense with the electron concentration of the Two-dimensional electron gas-bearing formation of the heterojunction interface 32 of the second semiconductor layer 14, and the electron concentration being formed at the Two-dimensional electron gas-bearing formation of the heterojunction interface 34 of the 3rd semiconductor layer 15 and the 4th semiconductor layer 16 is adjusted to relative thin.
Semiconductor device 1 also possesses drain electrode 21, auxiliary grid portion 23, conduction electrode 25, gate portion 28 and source electrode 29.These electrode structures are configured to striated when viewed in plan.
Drain electrode 21 is located on semiconductor multilayer body 10, separates predetermined distance be configured with source electrode 29.Predetermined distance between drain electrode 21 and source electrode 29 is according to the withstand voltage suitable adjustment expected.Drain electrode 21 is filled in and is formed in the first groove 22 of semiconductor multilayer body 10.Through 4th semiconductor layer 16 of first groove 22 and the 3rd semiconductor layer 15.Also can replace this example, the first groove 22 can be formed as darker, also can through second semiconductor layer 14 and arrive the first semiconductor layer 13.It is desirable that drain electrode 21 materials'use can with the material of nitride based semi-conducting material ohmic contact.In one example, drain electrode 21 uses multilayer electrode vanadium (V), aluminium (Al) and molybdenum (Mo) are laminated.Thus, draining 21, be configured to can with the Two-dimensional electron gas-bearing formation ohmic contact of the first heterojunction interface 32 being formed at the first semiconductor layer 13 and the second semiconductor layer 14.In addition, it is desirable that drain electrode 21 utilizes sintering processes (being 600 DEG C, 5 minutes in one example) to improve ohmic properties.
Auxiliary grid portion 23 is located on semiconductor multilayer body 10, is configured between drain electrode 21 and conduction electrode 25.It is desirable that the materials'use in auxiliary grid portion 23 can with the material of nitride based semi-conducting material Schottky contacts.In one example, auxiliary grid portion 23 uses the multilayer electrode of nickel (Ni) or nickel (Ni) and gold (Au).
Conduction electrode 25 is located on semiconductor multilayer body 10, is configured between auxiliary grid portion 23 and gate portion 28.Conduction electrode 25 is filled in and is formed in the second groove 24 of semiconductor multilayer body 10.Through 4th semiconductor layer 16 of second groove 24 and the 3rd semiconductor layer 15.Also can replace this example, the second groove 24 also can be formed as darker, also can through second semiconductor layer 14 and arrive the first semiconductor layer 13.It is desirable that the materials'use of conduction electrode 25 can with the material of nitride based semi-conducting material ohmic contact.In one example, conduction electrode 25 uses multilayer electrode vanadium (V), aluminium (Al) and molybdenum (Mo) are laminated.Thus, conduction electrode 25 be configured to can be formed at the Two-dimensional electron gas-bearing formation of the first heterojunction interface 32 and be formed at both Two-dimensional electron gas-bearing formations ohmic contact of the second heterojunction interface 34.In addition, it is desirable that conduction electrode 25 utilizes sintering processes (being 600 DEG C, 5 minutes in one example) to improve ohmic properties.
Gate portion 28 is located on semiconductor multilayer body 10, is configured between conduction electrode 25 and source electrode 29.Gate portion 28 has gate insulating film 26 and gate electrode 27.Gate electrode 27 via gate insulating film 26 with semiconductor multilayer body 10 in opposite directions.In one example, materials'use silicon nitride (SiN), the silica (SiO of gate insulating film 26
2) or aluminium oxide (Al
2o
3), the materials'use nickel (Ni) of gate electrode 27 and the multilayer electrode of aluminium (Al).In addition, gate portion 28 is overlapping with conduction electrode 25 with local when viewed in plan, and locally also overlapping with source electrode 29 mode and being formed.Therefore, gate portion 28 is located at the entirety between conduction electrode 25 and source electrode 29, and the second heterojunction interface 34 entirety existed between conduction electrode 25 and source electrode 29 in opposite directions.
Source electrode 29 is located on semiconductor multilayer body 10.It is desirable that the materials'use of source electrode 29 can with the material of nitride based semi-conducting material ohmic contact.In one example, source electrode 29 uses multilayer electrode vanadium (V), aluminium (Al) and molybdenum (Mo) are laminated.Thus, be configured to can with the Two-dimensional electron gas-bearing formation ohmic contact of the second heterojunction interface 34 being formed at the 3rd semiconductor layer 15 and the 4th semiconductor layer 16 for source electrode 29.In addition, it is desirable that source electrode 29 utilizes sintering processes (being 600 DEG C, 5 minutes in one example) to improve ohmic properties.In addition, source electrode 29, owing to leaving the first heterojunction interface 32 of the first semiconductor layer 13 and the second semiconductor layer 14, therefore, is configured to insulate with the Two-dimensional electron gas-bearing formation being formed at the first heterojunction interface 32.
Semiconductor device 1 can be evaluated as and the structure equivalence two kinds of High Electron Mobility Transistor be connected in series.In this situation, High Electron Mobility Transistor by draining 21, auxiliary grid portion 23 and conduction electrode 25 form, another High Electron Mobility Transistor is made up of conduction electrode 25, gate portion 28 and source electrode 29.
As shown in Figure 2 A, in an example of semiconductor device 1, also auxiliary grid portion 23 and source electrode 29 can be carried out short circuit and use.Or as shown in Figure 2 B, in another example of semiconductor device 1, also auxiliary grid portion 23 and gate portion 28 can be carried out short circuit and use.All be configured in either case when not applying voltage to gate portion 28, voltage is not applied to auxiliary grid portion 23 yet.
Below, be described with reference to the switching action of Fig. 1 and Fig. 3 to semiconductor device 1.In addition, as shown in Figure 2 A, in the following description, be described by the example of auxiliary grid portion 23 and source electrode 29 short circuit.
Semiconductor device 1 applies positive voltage to drain electrode 21, applies earthed voltage and use source electrode 29.When not applying voltage to the gate electrode 27 of gate portion 28, do not form Two-dimensional electron gas-bearing formation at the second heterojunction interface 34 of the 3rd semiconductor layer 15 and the 4th semiconductor layer 16.Therefore, the current flowing route between drain electrode 21 and source electrode 29 is blocked at this gate portion 28 the second heterojunction interface 34 in opposite directions, and semiconductor device 1 is off.In addition, now, voltage is not applied to auxiliary grid portion 23 yet.
When applying positive voltage to the gate electrode 27 of gate portion 28, form Two-dimensional electron gas-bearing formation at the second heterojunction interface 34 of the 3rd semiconductor layer 15 and the 4th semiconductor layer 16.As shown in Figures 1 and 3, from source electrode 29 injected electrons via be formed at the 3rd semiconductor layer 15 and the 4th semiconductor layer 16 the second heterojunction interface 34 Two-dimensional electron gas-bearing formation arrive conduction electrode 25.Electronics utilizes conduction electrode 25 through-thickness to flow, and the Two-dimensional electron gas-bearing formation then via the first heterojunction interface 32 being formed at the first semiconductor layer 13 and the second semiconductor layer 14 flows to drain electrode 21.
In semiconductor device 1, the Two-dimensional electron gas-bearing formation being adjusted to the second heterojunction interface 34 of relative thin with electron concentration is provided with gate portion 28 in opposite directions.Therefore, in semiconductor device 1, work under realizing normally off.In addition, in semiconductor device 1, turn to object so that height is withstand voltage, the distance between drain electrode 21 and source electrode 29 is formed as longer.In such cases, current flowing route major part is moved via the two-dimensional electron gas laminar flow being formed at the first relatively dense heterojunction interface 32 of electron concentration, and therefore the increase of conducting resistance is suppressed.Like this, semiconductor device 1 can work and possess high withstand voltage and low on-resistance under normally off.
The further feature of semiconductor device 1 is arranged.
(1) as shown in Figure 2, semiconductor device 1 can be evaluated as the structure equivalence of connecting with by two kinds of High Electron Mobility Transistor.A High Electron Mobility Transistor is high withstand voltage open type, and another transistor is low withstand voltage closed type.That is, semiconductor device 1 also can be evaluated as and obtain successfully by making two kinds of High Electron Mobility Transistor economical space saving be configured offset by thickness direction two heterojunction interface electrical connections via conduction electrode.
(2) by arranging auxiliary grid portion 23, when semiconductor device 1 disconnects, the electric field between drain electrode 21 and conduction electrode 25 is relaxed.
(3) semiconductor device 1 also can possess the protective layer of the undoped gallium nitride as the 5th semiconductor layer on the 4th semiconductor layer 16.By arranging protective layer, suppress avalanche phenomenon.
Above, concrete example of the present invention is illustrated in detail, but these are example, do not limit the scope of claim.The technology being recorded in the scope of claim comprises carries out various distortion, change by above illustrative concrete example.
In addition, this specification or the technology essential factor illustrated by accompanying drawing separately or by the technical practicality of various combination performance, the combination of right item record when being not limited to application.In addition, this specification or the technology illustrated in accompanying drawing can realize multiple object simultaneously, realize one of them object itself possess skills on practicality.
Claims (11)
1. a semiconductor device, possesses:
Semiconductor multilayer body;
Drain electrode, is located on described semiconductor multilayer body;
Source electrode, is located on described semiconductor multilayer body, and leaves configuration from described drain electrode;
Gate portion, is located on described semiconductor multilayer body, and is configured between described drain electrode and described source electrode; And
Conduction electrode, is located on described semiconductor multilayer body, and is located between described drain electrode and described gate portion,
Described semiconductor multilayer body has the first semiconductor layer, the second semiconductor layer, the 3rd semiconductor layer and the 4th semiconductor layer,
Described first semiconductor layer is different with the forbidden band of described second semiconductor layer, forms the first heterojunction interface by described first semiconductor layer and described second semiconductor layer,
Described 3rd semiconductor layer is different with the forbidden band of described 4th semiconductor layer, forms the second heterojunction interface by described 3rd semiconductor layer and described 4th semiconductor layer,
Described drain electrode is configured to be electrically connected with the Two-dimensional electron gas-bearing formation being formed at described first heterojunction interface,
Described source electrode is configured to can with the Two-dimensional electron gas-bearing formation electric insulation being formed at described first heterojunction interface, and described source electrode is configured to be electrically connected with the Two-dimensional electron gas-bearing formation being formed at described second heterojunction interface,
Described gate portion and described second heterojunction interface in opposite directions,
Described conduction electrode is configured to be electrically connected with the Two-dimensional electron gas-bearing formation being formed at described first heterojunction interface and both the Two-dimensional electron gas-bearing formations being formed at described second heterojunction interface,
The electron concentration being formed at the Two-dimensional electron gas-bearing formation of described first heterojunction interface is larger than the electron concentration of the Two-dimensional electron gas-bearing formation being formed at described second heterojunction interface.
2. semiconductor device as claimed in claim 1, wherein,
Also possess auxiliary grid portion, be located on described semiconductor multilayer body, and be located between described drain electrode and described conduction electrode,
The mode that when described auxiliary grid portion is not applied to voltage with described gate portion, this auxiliary grid portion is not applied to voltage is formed.
3. semiconductor device as claimed in claim 1, wherein,
Described first semiconductor layer, described second semiconductor layer, described 3rd semiconductor layer and described 4th semiconductor layer stack gradually.
4. semiconductor device as claimed in claim 2, wherein,
Described first semiconductor layer, described second semiconductor layer, described 3rd semiconductor layer and described 4th semiconductor layer stack gradually.
5. semiconductor device as claimed in claim 3, wherein,
The forbidden band of described second semiconductor layer is wider than the forbidden band of described first semiconductor layer,
The forbidden band of described 4th semiconductor layer is wider than the forbidden band of described 3rd semiconductor layer.
6. semiconductor device as claimed in claim 4, wherein,
The forbidden band of described second semiconductor layer is wider than the forbidden band of described first semiconductor layer,
The forbidden band of described 4th semiconductor layer is wider than the forbidden band of described 3rd semiconductor layer.
7. semiconductor device as claimed in claim 3, wherein,
Described drain electrode be filled in be formed at described semiconductor multilayer body the first groove in.
8. semiconductor device as claimed in claim 4, wherein,
Described drain electrode be filled in be formed at described semiconductor multilayer body the first groove in.
9. semiconductor device as claimed in claim 5, wherein,
Described drain electrode be filled in be formed at described semiconductor multilayer body the first groove in.
10. semiconductor device as claimed in claim 6, wherein,
Described drain electrode be filled in be formed at described semiconductor multilayer body the first groove in.
11. semiconductor devices according to any one of claim 3 ~ 10, wherein,
Described conduction electrode be filled in be formed at described semiconductor multilayer body the second groove in.
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| JP2011251261A JP5494622B2 (en) | 2011-11-17 | 2011-11-17 | Semiconductor device |
| JP2011-251261 | 2011-11-17 |
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| JP6223729B2 (en) * | 2013-06-25 | 2017-11-01 | 株式会社東芝 | Semiconductor device |
| JP6216559B2 (en) * | 2013-07-23 | 2017-10-18 | トランスフォーム・ジャパン株式会社 | Compound semiconductor device and manufacturing method thereof |
| CN103400854B (en) * | 2013-07-24 | 2016-02-03 | 中国电子科技集团公司第十三研究所 | A kind of grid-control semiconductor device with novel grid structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011118098A1 (en) * | 2010-03-26 | 2011-09-29 | 日本電気株式会社 | Field effect transistor, method of manufacture for field effect transistor, and electronic device |
| CN102239551A (en) * | 2008-12-05 | 2011-11-09 | 松下电器产业株式会社 | Field effect transistor and method for manufacturing same |
| CN102239550A (en) * | 2008-12-05 | 2011-11-09 | 松下电器产业株式会社 | Field effect transistor |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS57147283A (en) * | 1981-03-06 | 1982-09-11 | Fujitsu Ltd | Semiconductor device |
| JPS60244075A (en) * | 1984-05-18 | 1985-12-03 | Fujitsu Ltd | Manufacture of e/d structure integrated circuit |
| JPS61147577A (en) * | 1984-12-21 | 1986-07-05 | Toshiba Corp | Complementary semiconductor device |
| JPH0194676A (en) * | 1987-10-06 | 1989-04-13 | Nec Corp | Semiconductor device and manufacture thereof |
| JP2000195871A (en) * | 1998-12-28 | 2000-07-14 | Sony Corp | Semiconductor device and manufacture thereof |
| US7898047B2 (en) * | 2003-03-03 | 2011-03-01 | Samsung Electronics Co., Ltd. | Integrated nitride and silicon carbide-based devices and methods of fabricating integrated nitride-based devices |
| JP5489698B2 (en) * | 2009-12-22 | 2014-05-14 | トヨタ自動車株式会社 | Insulator, rotating electric machine, and method of manufacturing rotating electric machine |
-
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102239551A (en) * | 2008-12-05 | 2011-11-09 | 松下电器产业株式会社 | Field effect transistor and method for manufacturing same |
| CN102239550A (en) * | 2008-12-05 | 2011-11-09 | 松下电器产业株式会社 | Field effect transistor |
| WO2011118098A1 (en) * | 2010-03-26 | 2011-09-29 | 日本電気株式会社 | Field effect transistor, method of manufacture for field effect transistor, and electronic device |
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| JP5494622B2 (en) | 2014-05-21 |
| JP2013106018A (en) | 2013-05-30 |
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