CN103400854B - A kind of grid-control semiconductor device with novel grid structure - Google Patents
A kind of grid-control semiconductor device with novel grid structure Download PDFInfo
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- CN103400854B CN103400854B CN201310313080.1A CN201310313080A CN103400854B CN 103400854 B CN103400854 B CN 103400854B CN 201310313080 A CN201310313080 A CN 201310313080A CN 103400854 B CN103400854 B CN 103400854B
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Abstract
The invention discloses a kind of grid-control semiconductor device with novel grid structure, belong to semiconductor high-frequency power device and high tension apparatus.In the present invention, grid structure alternately connects to form by along grid width direction Dielectric and Schottky gate.Compare with conventional gate structure, main innovation of the present invention adopts the novel grid structure alternately occurred along grid width direction Schottky gate and Dielectric; Utilize Dielectric to reduce Leakage Current, utilize Schottky gate to improve grid-control ability simultaneously, alleviate the contradictory relation of semiconductor device puncture voltage and frequency characteristic; Meanwhile, compared with conventional media grid technique, the present invention only need change the reticle of etching gate medium, does not increase processing step and cost.
Description
Technical field
The present invention relates to semiconductor high-frequency power device and high tension apparatus, particularly the high frequency power field of grid-control semiconductor device.
Background technology
The grid-control ability of Schottky gate is comparatively strong, and device frequency characteristic is better, but its grid leak is electric and breakdown characteristics is poor, is widely used in microwave regime; The grid leak electricity of Dielectric is less, and breakdown characteristics is better, but its grid-control ability, and frequency characteristic is poor, is widely used in high pressure field.
Schottky gate directly controls raceway groove by barrier layer, strong to the control ability of raceway groove, and mutual conductance is comparatively large, thus frequency characteristic is better, and Schottky gate group III-nitride High Electron Mobility Transistor (HEMT) structure as shown in Figure 1.From document: M.A.Khan, J.N.Kuznia, D.T.Olson, etal., Microwaveperformanceofa0.25mmgateAlGaN/GaNheterostructur efieldeffecttransistor, Appl.Phs.Lett., 1994,65 (9): 1121-1123 proposition 0.25mm grid are long, the AlGaN/GaNHEMT that cut-off frequency (fT) and maximum oscillation frequency (fmax) are respectively 11GHz and 35GHz starts, and the continuous reduction of device size of each scholar etc. are optimized parasitic parameter and improved AlGaN/GaNHEMT frequency.The device architecture pursuing Frequency Index is all that application Schottky gate controls raceway groove, document: K.Shinohara, D.Regan, A.Brown, etal., Self-Aligned-GateGaN-HEMTswithHeavily-Dopedn+-GaNOhmicCo ntactsto2DEG, IEDM., 2012:617-620 are by GaN base HEMT
f twith
f maxbring up to 342GHz and 518GHz respectively.
But the grid Leakage Current of Schottky gate is comparatively large, and breakdown characteristics is poor; Introducing Dielectric is one of effective ways reducing Leakage Current, and Dielectric HEMT-structure as shown in Figure 2.Document: 1.8kVAlGaN/GaNHEMTswithHigh-k/Oxide/SiNMISStructure(Yagi S, ShimizuM, OkumuraH, etal, 200719thInternationalSymposiumonPowerSemiconductorDevice sandIC's (ISPSD'07), 261-264) respectively with HfO
2/ SiO
2/ SiN and ZrO
2/ SiO
2the HMET puncture voltage of grid leak spacing 28mm, as insulated gate medium, has been brought up to 1.8kV and 1.7kV by/SiN.
But insulated gate medium adds the distance of grid to raceway groove, and mutual conductance can reduce, thus affects the frequency characteristic of device.
Summary of the invention
In order to alleviate the contradictory relation of semiconductor device puncture voltage and frequency, the invention provides a kind of grid-control semiconductor device with novel grid structure, adopt the novel grid structure alternately occurred along grid width direction Schottky gate and Dielectric, Dielectric is utilized to reduce Leakage Current, utilize Schottky gate to improve grid-control ability simultaneously, thus improve the overall performance of device.
For solving the problems of the technologies described above, the technical solution used in the present invention is: a kind of grid-control semiconductor device with novel grid structure, comprise substrate, intermediate layer and grid structure from bottom to top, the grid structure of described grid-control semiconductor device is alternately connected to form along grid width direction by Dielectric and Schottky gate; The number n1 of described Dielectric and the number n2 of Schottky gate is the integer being more than or equal to 1.
The width d1 scope of described Dielectric is: 1nm≤d1≤10mm.
The described width d2 scope for Schottky gate is: 1nm≤d2≤10mm.
Described Schottky gate is planar gate or notched gates, and described Dielectric is planar gate or notched gates.
The thickness h of the gate medium of each Dielectric is equal, and h is greater than 0nm and is less than or equal to 1mm.
Described Dielectric and Schottky gate metal used are same metal.
Described grid-control semiconductor device is Si gated device, group III-nitride gated device, GaAs gated device, diamond gated device, Graphene gated device, Ge gated device or InP gated device.
The technological progress adopting technique scheme to obtain is: the present invention well solves the contradiction between semiconductor device puncture voltage and operating frequency, in the bar state, utilizes Dielectric to reduce grid Leakage Current, improves the puncture voltage of device; In working order, utilize Schottky gate to increase grid-control ability, improve device operating frequencies; Puncture voltage and the operating frequency of such device have been enhanced simultaneously, also just improve the overall performance of device; Manufacture craft of the present invention is identical with conventional media grid technique, only need change the reticle of etching gate medium, not increase processing step and cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of Schottky gate group III-nitride HEMT;
Fig. 2 is the structural representation of Dielectric group III-nitride HEMT;
Fig. 3 is the structural representation of the embodiment of the present invention 1;
Fig. 4 is the structural representation of grid structure in Fig. 3;
Fig. 5 be Fig. 4 along A-A to cutaway view;
Fig. 6 is the structural representation of embodiment 2;
Fig. 7 is the structural representation of embodiment 3;
Wherein, 1, substrate; 2, resilient coating; 3, channel layer; 4, barrier layer; 5, source electrode; 6, drain electrode; 7, gate medium; 8, Dielectric grid metal; 9, Schottky gate grid metal; 10, the semiconductor of N-type or P type delta doping; D1, Dielectric width; D2, Schottky gate width; The thickness of h, gate medium.
Embodiment
Embodiment 1
As shown in Fig. 3 to Fig. 5, a kind of group III-nitride HEMT with novel grid structure, comprise substrate 1, resilient coating 2, channel layer 3 and barrier layer 4 from bottom to top, resilient coating 2, channel layer 3 and barrier layer 4 are equivalent to intermediate layer, barrier layer 4 makes source electrode 5 and drain electrode 6, between source electrode 5 and drain electrode 6, be provided with grid structure, grid structure is made up of the Dielectric alternately connected along grid width direction and Schottky gate, and described Dielectric is made up of the Dielectric grid metal 8 be arranged above and below and gate medium 7.In the present embodiment, have 4 Dielectrics and 3 Schottky gates, the two ends of grid structure are Dielectric.
Described substrate 1 is Si or sapphire or SiC or GaN or diamond.
Described resilient coating 2 is AlN or GaN or AlN and Al
xga
1-xor AlN and In N(0<x<1)
xal
1-xn(0<x<1).
Described channel layer 3 is GaN.
Described barrier layer 4 is In
xal
yga
1-x-yn(0≤x≤1,0≤y≤1, x+y≤1).
In the present embodiment, 4 Dielectric width d1 are different, but all meet certain scope: 1nm≤d
1≤ 10mm; 3 Schottky gate width d2 are not identical yet, but its scope is: 1nm≤d2≤10mm.
The length range of Dielectric and Schottky gate is for being greater than 0nm and being less than 50mm.
The thickness h of described gate medium 7 is for being greater than 0nm and being less than 1mm.
The dielectric that the gate medium 7 of each Dielectric all can be greater than 1 by same dielectric constant is made, or is greater than 1 dielectric by n kind dielectric constant and makes, wherein, and 1 < n≤n
1, namely each gate medium can adopt not same material to make.
In the present embodiment, Dielectric and Schottky gate are all planar gate.
Embodiment 2
Known as shown in Figure 6, as different from Example 1, the present embodiment is that one has novel grid structure delta doped gate controlled semiconductor device, and intermediate layer is the semiconductor 10 that N-type or P type delta adulterate, one end, two ends of grid structure is Dielectric, and one end is Schottky gate.
In this embodiment, the width of each Dielectric is equal, and the width of each Schottky gate is equal, but both width are not etc.
The present embodiment medium grid and Schottky gate are planar gate.
Embodiment 3
Known as shown in Figure 7, as different from Example 1, the present embodiment medium grid are notched gates, and Schottky gate is planar gate.Certainly, Schottky gate also can be notched gates, and namely Dielectric and Schottky gate are all notched gates.The depth of groove of each Dielectric or Schottky gate can be equal, also can be unequal.
In the present invention, the width of Dielectric and Schottky gate, length and thickness etc. do not have strict restrictive condition, as long as meet respective number range.Both separately width, there is no restrictive condition between length and thickness, can be equal, can not wait.
The semi-conducting material that medium grid of the present invention adopt also is not particularly limited, and can adopt identical material between adjacent Dielectric, also can adopt different materials.The metal material that each Dielectric grid metal 8 adopts can be the same or different, and Schottky gate grid metal 9 is also like this.
The grid structure of original same type is mainly changed into the form alternately connected by two kinds of grid structures along grid width direction by the present invention.The present invention mainly adopts conventional media grid to be alternately connected with Schottky gate.So just well solve the contradiction between semiconductor device puncture voltage and operating frequency, in the bar state, utilize Dielectric to reduce grid Leakage Current, improve the puncture voltage of device; In working order, utilize Schottky gate to increase grid-control ability, improve device operating frequencies; Puncture voltage and the operating frequency of resulting devices have been enhanced simultaneously, also just improve the overall performance of device.
The invention provides the data area of thickness of the length of Dielectric and Schottky gate, gate medium 7, this only there is provided a preferred scope.Those skilled in the art can select suitable length and thickness as required, reach ideal characterisitics.
Claims (7)
1. have a grid-control semiconductor device for novel grid structure, it is characterized in that comprising substrate (1), intermediate layer and grid structure from bottom to top, the grid structure of described grid-control semiconductor device is alternately connected to form along grid width direction by Dielectric and Schottky gate; The number n1 of described Dielectric and the number n2 of Schottky gate is the integer being more than or equal to 1.
2. a kind of grid-control semiconductor device with novel grid structure according to claim 1, is characterized in that described Dielectric grid width d1 scope is: 1nm≤d1≤10mm.
3. a kind of grid-control semiconductor device with novel grid structure according to claim 1 and 2, is characterized in that described Schottky gate grid width d2 scope is: 1nm≤d2≤10mm.
4. a kind of grid-control semiconductor device with novel grid structure according to claim 1, it is characterized in that described Schottky gate is planar gate or notched gates, described Dielectric is planar gate or notched gates.
5. a kind of grid-control semiconductor device with novel grid structure according to claim 1 or 4, it is characterized in that the thickness h of the gate medium (7) of each Dielectric is equal, and h is greater than 0nm and is less than or equal to 1mm.
6. a kind of grid-control semiconductor device with novel grid structure according to claim 1 or 4, is characterized in that described Dielectric and Schottky gate metal used are same metal.
7. a kind of grid-control semiconductor device with novel grid structure according to claim 1, is characterized in that described grid-control semiconductor device is Si gated device, group III-nitride gated device, GaAs gated device, diamond gated device, Graphene gated device, Ge gated device or InP gated device.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101378062A (en) * | 2007-08-30 | 2009-03-04 | 古河电气工业株式会社 | Ed inverting circuit and integrated circuit element including the same |
| CN101789445A (en) * | 2008-12-22 | 2010-07-28 | 三垦电气株式会社 | Semiconductor device |
| CN203351602U (en) * | 2013-07-24 | 2013-12-18 | 中国电子科技集团公司第十三研究所 | Grid-control semiconductor device having novel grid composition |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7629627B2 (en) * | 2006-04-18 | 2009-12-08 | University Of Massachusetts | Field effect transistor with independently biased gates |
| JP5481103B2 (en) * | 2009-06-11 | 2014-04-23 | 株式会社東芝 | Nitride semiconductor device |
| JP5494622B2 (en) * | 2011-11-17 | 2014-05-21 | 株式会社豊田中央研究所 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101378062A (en) * | 2007-08-30 | 2009-03-04 | 古河电气工业株式会社 | Ed inverting circuit and integrated circuit element including the same |
| CN101789445A (en) * | 2008-12-22 | 2010-07-28 | 三垦电气株式会社 | Semiconductor device |
| CN203351602U (en) * | 2013-07-24 | 2013-12-18 | 中国电子科技集团公司第十三研究所 | Grid-control semiconductor device having novel grid composition |
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