CN103094072B - Improve the method for gate lithography critical dimension uniformity on wafer - Google Patents
Improve the method for gate lithography critical dimension uniformity on wafer Download PDFInfo
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- CN103094072B CN103094072B CN201110341214.1A CN201110341214A CN103094072B CN 103094072 B CN103094072 B CN 103094072B CN 201110341214 A CN201110341214 A CN 201110341214A CN 103094072 B CN103094072 B CN 103094072B
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000001459 lithography Methods 0.000 title claims abstract description 18
- 239000006117 anti-reflective coating Substances 0.000 claims abstract description 33
- 239000013078 crystal Substances 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 5
- 230000008021 deposition Effects 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 23
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 15
- 230000006872 improvement Effects 0.000 abstract description 14
- 238000001259 photo etching Methods 0.000 abstract description 9
- 229920005591 polysilicon Polymers 0.000 description 18
- 230000008569 process Effects 0.000 description 5
- 238000002474 experimental method Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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Abstract
The present invention relates to a kind of method improving gate lithography critical dimension uniformity on wafer, comprise the following steps: wafer is provided, form grid layer at described crystal column surface; At described grid layer surface deposition silicon oxynitride, form dielectric anti-reflective coating, any thickness at a place of described dielectric anti-reflective coating and the deviation of target thickness are all less than 2%; Described dielectric anti-reflective coating applies photoresist, and exposure forms the photoengraving pattern of grid.The invention still further relates to the dielectric anti-reflective coating after a kind of improvement.The above-mentioned method improving gate lithography critical dimension uniformity on wafer, use the dielectric anti-reflective coating (DARC) after a kind of improvement, by improving the uniformity of the thickness of SiON in DARC, the uniformity of controlling and adjustment critical size of polycrystalline silicon grid electrode effectively, reaches the object solving crystal round fringes electric leakage.Compared by the method for adjustment photoetching formula with traditional, do not need again to make a plate and verify, shorten time and the cost of yield improvement.
Description
[technical field]
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of method improving gate lithography critical dimension uniformity on wafer, also relate to a kind of dielectric anti-reflective coating.
[background technology]
In CMOSFET pipe (CMOS) chip manufacturing, the processing procedure of polysilicon (poly) grid is one very important operation, and the size of polysilicon gate critical size (polyCD) directly can affect the various electrical parameters of device.Therefore the control of the uniformity of polysilicon gate critical size become extremely important.
In a kind of traditional 0.16 micron gate length (LG) processing procedure, after polysilicon gate photoetching, the uniformity of critical size is bad, especially in the edge of wafer, polysilicon gate critical size 10nm more than less of place of crystal circle center, cause at wafer probing (ChipProbing, CP) time, crystal round fringes occurs that the electric leakage of special pattern was lost efficacy, and has a strong impact on the confidence of product yield and client, therefore solves very important that crystal round fringes electric leakage Problem of Failure becomes.
At present in order to solve crystal round fringes polysilicon gate critical size problem less than normal, main way is controlled by the debugging of parameter in the formula (recipe) to polysilicon gate photoetching process, the parameter such as the focal length in photoetching process, NA (numerical aperture), sigma, energy, photoresist thickness generally can be regulated to do and improve.
But the adjustment of these parameters can have influence on the size of PR profile (PRprofile) and critical size, corresponding impact is also had on optical approach effect correction (OPC), therefore high to the method cost of parameter adjustment in photoetching process formula, efficiency is low.
[summary of the invention]
Based on this, be necessary to provide a kind of cost lower, the method for gate lithography critical dimension uniformity on the improvement wafer that efficiency is high.
Improve a method for gate lithography critical dimension uniformity on wafer, comprise the following steps: wafer is provided, form grid layer at described crystal column surface; At described grid layer surface deposition silicon oxynitride, form dielectric anti-reflective coating, any thickness at a place of described dielectric anti-reflective coating and the deviation of target thickness are all less than 2%; Described dielectric anti-reflective coating applies photoresist, and exposure forms the photoengraving pattern of grid.
Preferably, the THICKNESS CONTROL of described dielectric anti-reflective coating exists
in, N value controls in 2.09 ~ 2.11, and K value controls in 0.62 ~ 0.66.
Preferably, described deposit is chemical vapor deposition, and reacting gas comprises SiH
4, N
2o and He, SiH
4flow be 69 ~ 89sccm, N
2the flow of O is the flow of 130 ~ 230sccm, He is 1800 ~ 2200sccm, and the reaction pressure of described deposit is 4 ~ 7Torr, and the reaction power of described deposit is 80 ~ 120W.
Preferably, described SiH
4flow be 75sccm.
Preferably, described N
2the flow of O is 210sccm.
Preferably, the flow of described He is 1900sccm.
Preferably, the reaction pressure of described deposit is 5.5Torr.
Preferably, the reaction power of described deposit is 95W.
Preferably, the board model that described deposit uses is Producer.
There is a need to the dielectric anti-reflective coating after a kind of improvement is provided.
A kind of dielectric anti-reflective coating, be located at the surface of grid layer, material is silicon oxynitride, and any thickness at a place of described dielectric anti-reflective coating and the deviation of target thickness are all less than 2%.
The above-mentioned method improving gate lithography critical dimension uniformity on wafer, use the dielectric anti-reflective coating (DARC) after a kind of improvement, by improving the uniformity of the thickness of SiON in DARC, the uniformity of controlling and adjustment critical size of polycrystalline silicon grid electrode effectively, reaches the object solving crystal round fringes electric leakage.Compared by the method for adjustment photoetching formula with traditional, do not need again to make a plate and verify, shorten time and the cost of yield improvement.
[accompanying drawing explanation]
Fig. 1 is the flow chart of the method improving gate lithography critical dimension uniformity on wafer in an embodiment;
Fig. 2 be a kind of use AMAT5000 board traditional handicraft deposit SiON dielectric anti-reflective coating after form by follow-up technique the curve chart that the wafer critical size of polycrystalline silicon grid electrode of polysilicon gate changes with wafer back gauge;
Fig. 3 is the comparison diagram of the response curve that the parameter of curve shown in Fig. 2 and employing Producer board and the first preferred embodiment obtains;
Fig. 4 is the curve chart of the thickness evenness before and after SiON depositing technics improves;
Fig. 5 is the curve chart of the N value uniformity before and after SiON depositing technics improves;
Fig. 6 is the curve chart of the K value uniformity before and after SiON depositing technics improves;
Fig. 7 is the electric leakage fail data figure of wafer before and after SiON depositing technics improves.
[embodiment]
For enabling object of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
In traditional photoetching process, generally use antireflecting coating (ARC) technique to reduce standing wave effect.The material one that to be the dielectric anti-reflective coating (DielectricAnti-reflectiveCoating, DARC) of SiON (silicon oxynitride) be in ARC, is usually used in the photoetching process of polysilicon gate.Find through inventor's research and experiment, by improving the uniformity of the dielectric anti-reflective coating on polysilicon gate, effectively can solve the problem that the critical size of the polysilicon gate of crystal round fringes is less than normal than design load, thus solve edge current leakage Problem of Failure, the yields of improving product.
Good uniformity can be obtained to make dielectric anti-reflective coating, found by a large amount of experiments, in the technique of deposit SiON, the thickness of the change of each technological parameter and dielectric anti-reflective coating, N value, K value, the scope of N value, the scope of K value have close relationship.Such as within the specific limits, thickness and reaction pressure, reaction power, N
2the flow of O, SiH
4flow be directly proportional, be inversely proportional to the flow of He; N value, K value and SiH
4flow, He flow be directly proportional, with reaction pressure, reaction power, N
2the flow of O is inversely proportional to; N value, K value are directly proportional to the flow of reaction power, He, with reaction pressure, SiH
4flow, N
2the flow of O is inversely proportional to.
Be aided with great many of experiments according to above-mentioned relation, as shown in Figure 1, the invention provides a kind of method improving gate lithography critical dimension uniformity on wafer, comprise the following steps:
S110, provides wafer, forms grid layer at crystal column surface.The material of this grid layer is polysilicon.
S120, at grid layer surface deposition silicon oxynitride, form dielectric anti-reflective coating, control any thickness at a place of dielectric anti-reflective coating and the deviation of target thickness are all less than 2%.Namely thickness is very even.
S130, dielectric anti-reflective coating applies photoresist, and exposure forms the photoengraving pattern of grid.
The mode of deposit is chemical vapor deposition (ChemicalVaporDeposition, CVD), and the reacting gas of deposit comprises SiH
4, N
2o and He, SiH
4flow be 69 ~ 89sccm, N
2the flow of O is the flow of 130 ~ 230sccm, He is 1800 ~ 2200sccm, and the reaction pressure of deposit is 4 ~ 7Torr, and the reaction power of deposit is 80 ~ 120W.
Experimental data shows in above-mentioned parameter area, the uniformity of the thickness of dielectric anti-reflective coating, N value, K value, and the problem that the critical size of polysilicon gate reduces at crystal round fringes just can significantly improve.Understandable, inventor determines separately preferred value a: SiH of each parameter on this basis by experiment
4flow be 75sccm, N
2the flow of O is the flow of 210sccm, He is 1900sccm, and the reaction pressure of deposit is 5.5Torr, and the reaction power of deposit is 95W, and the thickness of dielectric anti-reflective coating is
Following table is the value of each parameter in the first preferred embodiment.
| The reaction pressure of deposit | 5.5Torr |
| SiH 4Flow | 75sccm |
| N 2The flow of O | 210sccm |
| The reaction power of deposit | 95W |
| The flow of He | 1900sccm |
The deposit board deposit dielectric anti-reflection coating that inventor's deposit board that also uses model to be AMAT5000 respectively and model are Producer, find the dielectric anti-reflective coating using Producer board relative to the deposit of AMAT5000 board, the uniformity of N value, K value, thickness is obtained for improvement, thus makes the uniformity of the critical size of polysilicon gate have also been obtained improvement.
Fig. 2 be a kind of use AMAT5000 board traditional handicraft deposit SiON dielectric anti-reflective coating after form by follow-up technique the curve chart that the wafer critical size of polycrystalline silicon grid electrode of polysilicon gate changes with wafer back gauge.Abscissa represents the distance with crystal round fringes, and ordinate represents the critical size of polysilicon gate, can see that the critical size of polysilicon gate is larger with edge gap in the middle part of wafer.
Fig. 3 is the comparison diagram of the response curve that the parameter of curve shown in Fig. 1 and employing Producer board and the first preferred embodiment obtains.Can see that the uniformity of the critical size of polysilicon gate obtains very big improvement.Fig. 4,5,6 is the curve chart using the thickness of AMAT5000 board traditional handicraft and Producer board first preferred embodiment deposit SiON dielectric anti-reflective coating (namely SiON depositing technics improves front and back), N value, K value uniformity respectively.Can see that the uniformity of thickness, N value, K value is obtained for very big improvement.Referring to Fig. 3, although expect to obtain
siON, but reality still has close
error.Fig. 7 is the electric leakage fail data figure of wafer before and after SiON depositing technics improves.After adopting Producer board first preferred embodiment deposit SiON dielectric anti-reflective coating, the average leakage rate of DIE has dropped to less than 1%.
The above-mentioned method improving gate lithography critical dimension uniformity on wafer, use the dielectric anti-reflective coating (DARC) after a kind of improvement, by improving the uniformity of the K value of SiON in DARC, N value and thickness, the uniformity of controlling and adjustment critical size of polycrystalline silicon grid electrode effectively, reaches the object solving crystal round fringes electric leakage.Compared by the method for adjustment photoetching formula with traditional, do not need again to make a plate and verify, shorten time and the cost of yield improvement, promote client to product confidence.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (7)
1. improve a method for gate lithography critical dimension uniformity on wafer, comprise the following steps:
Wafer is provided, forms grid layer at described crystal column surface;
At described grid layer surface deposition silicon oxynitride, form dielectric anti-reflective coating, any thickness at a place of described dielectric anti-reflective coating and the deviation of target thickness are all less than 2%; The THICKNESS CONTROL of described dielectric anti-reflective coating exists
in, N value controls in 2.09 ~ 2.11, and K value controls in 0.62 ~ 0.66; Described deposit is chemical vapor deposition, and reacting gas comprises SiH
4, N
2o and He, SiH
4flow be 69 ~ 89sccm, N
2the flow of O is the flow of 130 ~ 230sccm, He is 1800 ~ 2200sccm, and the reaction pressure of described deposit is 4 ~ 7Torr, and the reaction power of described deposit is 80 ~ 120W;
Described dielectric anti-reflective coating applies photoresist, and exposure forms the photoengraving pattern of grid.
2. the method improving gate lithography critical dimension uniformity on wafer according to claim 1, is characterized in that, described SiH
4flow be 75sccm.
3. the method improving gate lithography critical dimension uniformity on wafer according to claim 1, is characterized in that, described N
2the flow of O is 210sccm.
4. the method improving gate lithography critical dimension uniformity on wafer according to claim 1, is characterized in that, the flow of described He is 1900sccm.
5. the method improving gate lithography critical dimension uniformity on wafer according to claim 1, is characterized in that, the reaction pressure of described deposit is 5.5Torr.
6. the method improving gate lithography critical dimension uniformity on wafer according to claim 1, is characterized in that, the reaction power of described deposit is 95W.
7. the method improving gate lithography critical dimension uniformity on wafer according to claim 1, is characterized in that, the board model that described deposit uses is Producer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110341214.1A CN103094072B (en) | 2011-11-01 | 2011-11-01 | Improve the method for gate lithography critical dimension uniformity on wafer |
| PCT/CN2012/083354 WO2013064025A1 (en) | 2011-11-01 | 2012-10-23 | Method for improving gate photo-etching key size uniformity on wafer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110341214.1A CN103094072B (en) | 2011-11-01 | 2011-11-01 | Improve the method for gate lithography critical dimension uniformity on wafer |
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| CN103094072B true CN103094072B (en) | 2016-03-30 |
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| CN111696849A (en) * | 2019-03-13 | 2020-09-22 | 上海新微技术研发中心有限公司 | Composite film, composite silicon wafer, and preparation method and application thereof |
| CN112802797B (en) * | 2020-12-29 | 2023-08-15 | 上海华力集成电路制造有限公司 | Method for improving uniformity of critical dimension in wafer surface |
| CN113140505B (en) * | 2021-03-18 | 2023-08-11 | 上海华力集成电路制造有限公司 | Method for manufacturing through hole |
| CN113391520A (en) * | 2021-05-14 | 2021-09-14 | 上海华力集成电路制造有限公司 | Coating method of photoresist and photoetching method thereof |
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| US7538026B1 (en) * | 2005-04-04 | 2009-05-26 | Advanced Micro Devices, Inc. | Multilayer low reflectivity hard mask and process therefor |
| KR20090124097A (en) * | 2008-05-29 | 2009-12-03 | 주식회사 하이닉스반도체 | Forming method for pattern of semiconductor device |
| JP5568340B2 (en) * | 2010-03-12 | 2014-08-06 | 東京エレクトロン株式会社 | Plasma etching method and plasma etching apparatus |
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| US6417084B1 (en) * | 2000-07-20 | 2002-07-09 | Advanced Micro Devices, Inc. | T-gate formation using a modified conventional poly process |
| CN1445818A (en) * | 2002-03-15 | 2003-10-01 | 台湾积体电路制造股份有限公司 | Multiple-layer type dielectric antireflection layer and its forming method |
| CN1385884A (en) * | 2002-06-20 | 2002-12-18 | 上海华虹（集团）有限公司 | Novel button anti-reflection film structure |
| CN1471132A (en) * | 2002-07-22 | 2004-01-28 | ����ʿ�뵼������˾ | Method for forming pattern of semiconductor device and semiconductor device |
| CN1567529A (en) * | 2003-06-13 | 2005-01-19 | 南亚科技股份有限公司 | Multi-layer type anti-reflection layer and semiconductor process adopting the same |
| CN1614754A (en) * | 2003-11-05 | 2005-05-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of silicon oxynitride |
| CN1770396A (en) * | 2004-10-06 | 2006-05-10 | 旺宏电子股份有限公司 | Silicon rich dielectric antireflective coating |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103094072A (en) | 2013-05-08 |
| WO2013064025A1 (en) | 2013-05-10 |
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