CN101441407B - Photolithography dimension ultra-specification correcting etching method - Google Patents
Photolithography dimension ultra-specification correcting etching method Download PDFInfo
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- CN101441407B CN101441407B CN2007100942421A CN200710094242A CN101441407B CN 101441407 B CN101441407 B CN 101441407B CN 2007100942421 A CN2007100942421 A CN 2007100942421A CN 200710094242 A CN200710094242 A CN 200710094242A CN 101441407 B CN101441407 B CN 101441407B
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Abstract
The invention discloses a correction etching method for the photolithographic dimensions beyond the specifications. The method is used for further etching a main dielectric film on a substrate and reaching the preset line width of the main dielectric film when the photolithographic dimensions beyond the specifications result in photolithographic dimensional deviation, wherein an etching barrier layer is arranged on the main dielectric film, and photoresist is coated on the etching barrier layer. The method comprises the following steps: (1) calculating the etching section angular correction value of the etching barrier layer according to the photolithographic dimensional deviation; (2) according to the etching section angular correction value of the etching barrier layer, adjusting the etching section angle of the etching barrier layer through changing the etching parameters; and (3) further etching the main dielectric film to obtain the preset line width of the main dielectric film. As the method changes the technological process which requires rework for the photolithographic dimensions beyond the specifications and obtains the preset line width of the main dielectric film, the method can greatly increase the photolithographic technological window and reduce the rework due to the photolithographic line width beyond the specifications and the production cost.
Description
Technical field
The present invention relates to a kind of SIC (semiconductor integrated circuit) manufacturing process, be specifically related to a kind of correction lithographic method of photolithography dimension ultra-specification.
Background technology
As shown in Figure 1, behind the lithographic line width ultra-specification, take the operation of doing over again.Technological process is as the one of which: behind the photolithography dimension ultra-specification, remove photoresist with dry method, carry out wet etching then; Then recoat photoresist and carry out photoetching; Carry out lithographic dimensioned measurement after the photoetching, if qualified then get into next step etching, if ultra-specification then the operation of doing over again again.
Said method can make the silicon chip number of defects increase, and causes yield to reduce, also increased simultaneously remove photoresist, the production cost of wet method, photoetching process, cause the wasting of resources.
Summary of the invention
Technical matters to be solved by this invention provides a kind of correction lithographic method of photolithography dimension ultra-specification; It can be used for revising behind the photolithography dimension ultra-specification; The main deielectric-coating live width that obtains setting; And then can increase considerably lithographic process window, minimizing is done over again because of the lithographic line width ultra-specification, reduces production costs.
In order to solve above technical matters; The invention provides a kind of correction lithographic method of photolithography dimension ultra-specification; When being used for photolithography dimension ultra-specification and producing lithographic dimensioned deviation, the further main deielectric-coating on the etched substrate reaches the main deielectric-coating live width of setting; On the wherein main deielectric-coating etching barrier layer is arranged, scribble photoresist on the etching barrier layer; Specifically comprise the steps: (1) etching section angle modified value according to lithographic dimensioned deviation calculation etching barrier layer; (2) according to the etching section angle modified value of etching barrier layer, adjust the etching section angle of etching barrier layer through changing etching parameters; (3) further etching master deielectric-coating, the main deielectric-coating live width that obtains setting.
Because the present invention has changed the technological process of the operation of need doing over again behind the photolithography dimension ultra-specification with said method; Through the main deielectric-coating live width that still can obtain setting after revising; And then can increase considerably lithographic process window, minimizing is done over again because of the lithographic line width ultra-specification, reduces production costs.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further explain.
Fig. 1 is the process chart of operation of need doing over again behind the existing photolithography dimension ultra-specification;
Fig. 2 is a lithographic dimensioned normal synoptic diagram after the photoetching;
Fig. 3 is lithographic dimensioned structural representation after etching when normal;
Fig. 4 is the synoptic diagram of photolithography dimension ultra-specification after the photoetching (bigger than normal);
Fig. 5 is the structural representation after photolithography dimension ultra-specification (bigger than normal) etching;
Fig. 6 is the synoptic diagram of photolithography dimension ultra-specification after the photoetching (less than normal);
Fig. 7 is the structural representation after photolithography dimension ultra-specification (less than normal) etching.
Reference numeral does among the figure, 1, and substrate; 2, main deielectric-coating; 3, etching barrier layer; 4, photoresist; L, lithographic dimensioned; δ, lithographic dimensioned deviation; D, etching deviation; T, etch stop layer thickness; S, the main deielectric-coating live width of setting; A, the etching section angle of etching barrier layer; θ, the etching section angle modified value of etching barrier layer.
Embodiment
Like Fig. 2 is the synoptic diagram under the lithographic dimensioned normal condition after the photoetching, and main deielectric-coating 2 is arranged on the substrate 1 among the figure, on the main deielectric-coating 2 etching barrier layer 3 is arranged, and etch stop layer thickness is T, and photoresist is arranged on the etching barrier layer, normal lithographic dimensioned L after the photoetching.
Like Fig. 3 is the synoptic diagram of further etching under Fig. 2 state, and wherein D is the etching deviation that can exist under the normal condition, and A is the etching section angle of etching barrier layer, and S is the main deielectric-coating live width of setting, and then satisfies formula:
S＝L+D+2*T*ctgA，
Wherein when technology one timing of etching, the main deielectric-coating live width S of the etching section angle A of lithographic dimensioned L, etching deviation D, etching barrier layer, setting is a fixed value.
Like Fig. 4 and shown in Figure 5, the correction lithographic method of photolithography dimension ultra-specification of the present invention, when being used for lithographic dimensioned L ultra-specification and producing lithographic dimensioned deviation δ, the further main deielectric-coating 2 on the etched substrate 1 reaches the main deielectric-coating live width S of setting.Mainly be lithographic dimensioned bigger than normal shown in the figure, the situation when promptly producing overgauge.
Among Fig. 4; The material of main deielectric-coating 2 can be metal or polysilicon; On the main deielectric-coating 2 etching barrier layer 3 is arranged, the material of etching barrier layer 3 can be hard mask and insulation antireflection material, specifically comprises silicon oxynitride, silicon nitride, silicon dioxide and metallic compound etc.; Scribble photoresist 4 on the etching barrier layer 3, the lithographic dimensioned L+ δ that is actually after the photoetching.
Specifically comprise the steps: according to the method for the invention
(1) according to the etching section angle modified value of lithographic dimensioned deviation calculation etching barrier layer.
Live width calculating formula owing to main deielectric-coating reality during calculating is:
L+D+2*T*ctg(A+θ)，
The main deielectric-coating live width of setting is calculated by normal condition:
S＝L+D+2*T*ctgA，
If the actual live width of main deielectric-coating need be equated above-mentioned two calculating formulas with the main deielectric-coating live width of setting, that is:
L+D+2*T*ctg(A+θ)＝L+D+2*T*ctgA；
Further abbreviation can get computing formula and be:
2*T*ctgA＝δ+2*T*ctg(A+θ)；
Wherein, The etching section angle A of lithographic dimensioned L, lithographic dimensioned deviation δ, etching barrier layer, etch stop layer thickness T are known; And the etching section angle A of etching barrier layer is spent to the scope of 90 degree 0, through calculating the etching section angle modified value θ that can confirm etching barrier layer.
In situation shown in Figure 3 because lithographic dimensioned bigger than normal, the etching section angle modified value θ that then can confirm etching barrier layer on the occasion of.
(2) according to the etching section angle modified value of etching barrier layer, adjust the etching section angle of etching barrier layer through changing etching parameters.
Calculate the etching section angle modified value θ of etching barrier layer; The etching section angle that then can confirm new etching barrier layer should be A+ θ, can realize through adjustment etching parameters (comprising chamber pressure, radio-frequency power, gas flow and reaction chamber temperature).
(3) further etching master deielectric-coating, the main deielectric-coating live width that obtains setting.
Etching section angle A+ θ according to the new etching barrier layer of adjusting carries out etching, the main deielectric-coating live width S that can obtain setting.
Fig. 6 and Fig. 7 are an alternative embodiment of the invention, and be as shown in Figure 6, and photolithography dimension ultra-specification also might be than the normal size minus deviation that promptly produces less than normal after the photoetching.In this case, the etching section angle modified value θ that can determine etching barrier layer through same method is a negative value, revises, and is as shown in Figure 7, and the main deielectric-coating live width S that still can obtain setting realizes normal etching.
Claims (6)
1. the correction lithographic method of a photolithography dimension ultra-specification; When being used for photolithography dimension ultra-specification and producing lithographic dimensioned deviation; Main deielectric-coating on the further etched substrate; Reach the main deielectric-coating live width of setting, on the wherein said main deielectric-coating etching barrier layer is arranged, scribble photoresist on the said etching barrier layer; It is characterized in that, comprise the steps:
(1) according to the etching section angle modified value of the described etching barrier layer of said lithographic dimensioned deviation calculation, computing formula is following:
2*T*ctgA＝δ+2*T*ctg(A+θ)
Wherein,
T is the thickness of said etching barrier layer;
A is the etching section angle of said etching barrier layer;
δ is said lithographic dimensioned deviation;
θ is the etching section angle modified value of said etching barrier layer, θ can be on the occasion of or negative value;
(2) according to the etching section angle modified value of said etching barrier layer, adjust the etching section angle of etching barrier layer through changing etching parameters; Said etching section angle is 0 degree～90 degree;
(3) further etching master deielectric-coating, the main deielectric-coating live width that obtains setting.
2. the correction lithographic method of photolithography dimension ultra-specification as claimed in claim 1 is characterized in that, described main deielectric-coating comprises metal and polysilicon.
3. the correction lithographic method of photolithography dimension ultra-specification as claimed in claim 1 is characterized in that, described etching barrier layer comprises hard mask and insulation antireflection material.
4. the correction lithographic method of photolithography dimension ultra-specification as claimed in claim 3 is characterized in that, described hard mask comprises with the insulation antireflection material: silicon oxynitride, silicon nitride, silicon dioxide and metallic compound.
5. the correction lithographic method of photolithography dimension ultra-specification as claimed in claim 1 is characterized in that, described lithographic dimensioned deviation comprises overgauge and minus deviation.
6. the correction lithographic method of photolithography dimension ultra-specification as claimed in claim 1 is characterized in that, the described etching parameters of step (2) comprises chamber pressure, radio-frequency power, gas flow and reaction chamber temperature.
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| CN101441407B true CN101441407B (en) | 2012-06-20 |
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| CN102270600B (en) * | 2010-06-04 | 2013-09-25 | 中芯国际集成电路制造(北京)有限公司 | Forming method of through hole |
| CN102591156B (en) * | 2011-12-05 | 2015-05-20 | 深圳市华星光电技术有限公司 | Exposure device and exposure method |
| CN103984212A (en) * | 2014-05-27 | 2014-08-13 | 上海华力微电子有限公司 | Method for improving exposure shape of photoresist and method for patterning semiconductor substrate |
| CN113741142A (en) * | 2020-05-29 | 2021-12-03 | 中芯国际集成电路制造(上海)有限公司 | Etching offset correction method and system and related equipment |
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| CN1971415A (en) * | 2005-11-24 | 2007-05-30 | 上海华虹Nec电子有限公司 | Manufacturing method of contact hole on surface of silicon chip |
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| CN1971415A (en) * | 2005-11-24 | 2007-05-30 | 上海华虹Nec电子有限公司 | Manufacturing method of contact hole on surface of silicon chip |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |