CN101740368A - Methods for forming semiconductor device and grid electrode thereof - Google Patents
Methods for forming semiconductor device and grid electrode thereof Download PDFInfo
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- CN101740368A CN101740368A CN200810225922A CN200810225922A CN101740368A CN 101740368 A CN101740368 A CN 101740368A CN 200810225922 A CN200810225922 A CN 200810225922A CN 200810225922 A CN200810225922 A CN 200810225922A CN 101740368 A CN101740368 A CN 101740368A
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Abstract
The invention discloses a method for forming a grid electrode of a semiconductor device, comprising the following steps of: providing an underlay on which a pad oxide layer is formed; forming an auxiliary medium layer on the pad oxide layer of the underlay; forming a grid electrode hole figure on the auxiliary medium layer by utilizing a photoetching process; etching the auxiliary medium layer until the pad oxide layer is exposed by taking the grid electrode hole figure as a masking film to form a grid electrode hole; depositing a polysilicon layer so as to fill the grid electrode hole; planarizing the polysilicon layer until the auxiliary medium layer is exposed; and removing the auxiliary medium layer to form a grid electrode. The invention also provides a corresponding method for forming the semiconductor device. By adopting the semiconductor device formed by the method for forming the semiconductor device and the grid electrode thereof, the problem of poor device electrical property variation caused by that ions are downwards diffused towards the grid electrode in the annealing step can be relieved, the overlap capacitance between the grid electrode and source /drain electrodes is reduced and the work speed of the device is increased.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, the formation method of particularly a kind of semiconductor device and grid thereof.
Background technology
The technology of semiconductor integrated circuit chip is made and is utilized the batch process technology, forms a large amount of various types of complex devices on same silicon substrate, and it is connected to each other to have complete electric function.Along with developing rapidly of very lagre scale integrated circuit (VLSIC), the integrated level of chip is more and more higher, and the size of components and parts is more and more littler, because of the high density of device, the influence that the various effects of small size initiation are made the result to semiconductor technology also become increasingly conspicuous.
The example that is made as with grid: along with device size constantly dwindles, the grid live width of device also reduces thereupon, this brings difficulty can on the one hand the photoetching process of grid, when the follow-up ion that source/drain electrode is injected carries out thermal anneal process, also be prone to foreign ion on the other hand and diffuse to situation below the grid, cause that distance shortens between the source/drain region of device, problems such as it is big overlap capacitance (overlapcapacitance) change to occur, and the operating rate of device is slack-off.
Fig. 1 to Fig. 3 is the device profile schematic diagram of the existing grid structure formation method of explanation, as shown in Figure 1, on substrate 101, form earlier pad silicon oxide layer 102 (Pad Oxide), deposit spathic silicon layer 103 thereon again, and utilize photoresist 110 to make gate patterns by lithography; Then, as shown in Figure 2, be mask with photoresist 110, etch polysilicon layer 103 and pad oxide 102 form polysilicon gate; Follow again, as shown in Figure 3, remove photoresist 110 after, utilize the ion injection mode, with the polysilicon gate that forms mask very, form shallow doped drain (LDD, Light-Doped Drain) 104 in these polysilicon gate both sides.
The grid of the vertical sidewall that forms among Fig. 3 is an ideal situation, and the actual common top of grid that forms is little, the bottom is big, and therefore, the size that requires photoetching to form in the actual production is littler than design load a, and when technological development was following to 65nm, the difficulty of photoetching was bigger.In addition, in the formation method of above-mentioned existing grid structure, ion injects the ion that injects when forming the LDD district, in subsequent annealing step easily to the grid diffuse underneath, make the distance between the adjacent LDD district, grid below be reduced into actual value b by design load a, this will cause the overlap capacitance (overlapcapacitance) of device between grid and source/drain electrode to become big, and the operating rate of device is slack-off.
For this reason, adopt sometimes in the prior art and earlier polysilicon gate carried out oxidation, at it outside, form layer of oxide layer, again with this polysilicon gate that is coated with oxide layer very mask carry out the method that ion injects formation LDD district.Adopt this method can form the grid of large-size first earlier, reduce the photoetching difficulty, second can alleviate the annealing steps intermediate ion spreads the device electrical performance variation that causes down to grid problem.
Fig. 4 becomes the semiconductor device generalized section of oxide layer for existing in gate shape, as shown in Figure 4, forms pad silicon oxide layer 102 and polysilicon layer 103 earlier on substrate 101; Utilize photoetching, etching technics to form the polysilicon gate of the large-size that is of a size of a ' again, again it is carried out oxidation, make the skin generation oxidation reaction of polysilicon gate form one deck silicon oxide layer 410.At this moment, the polysilicon gate construction that covers one deck silicon oxide layer 410 with this outside again is the ion implant operation that mask forms LDD district 104.After above-mentioned processing, the size of the actual polysilicon gate that forms becomes again or near desired value a, and the distance between two adjacent LDD districts also can more approach design load a.Above-mentioned improvement makes technology to the diffusion below the grid certain tolerance arranged for the annealing steps intermediate ion in making.
But, when device size further is contracted to the following technology node of 65nm, size of devices control is required tighter, the THICKNESS CONTROL that requires the grid external oxidation layer that will form usually is at 7nm and following, and this small formation thickness is difficult to realize accurately control in practical operation.At this moment, above-mentionedly become the method for oxide layer to be difficult to satisfy the making requirement of small size device in the strictness aspect the size in gate shape.
In addition, proposed a kind of method of reduction of gate live width but application number is 200410071086.3 Chinese patent application, this method has formed a larger-size grid structure earlier on substrate, and has formed metal silicide at the top of this grid structure; Then, method by photoetching defines the less area of grid of a size, utilize the method removal of etching to be positioned at this small size zone metal silicide and grid structure in addition again, this method can be improved the formation quality of silicide on the grid under the less situation of grid live width.Simultaneously, its also can be by carrying out when the large scale grid structure ion to inject in a big way in the alleviation ion under grid, spread the problem that causes.
But this method has following weak point: the one, and, the step that it has increased photoetching reduced size area of grid has not only improved production cost, has prolonged the production cycle, and fails the difficulty of avoiding photoetching small size grid to be brought; The 2nd, because the technology of the photoetching small size grid that is increased can not be utilized self-aligned technology, formed device grids is not in the middle part of source/drain electrode probably, and is unfavorable on the contrary to device performance.Therefore, in fact this method can not solve the problem that occurs in the existing grid formation method of above-mentioned proposition, does not obtain real raising aspect device performance.
Summary of the invention
The invention provides the formation method of a kind of semiconductor device and grid thereof, in annealing steps, be prone to the phenomenon of ions diffusion to the grid in existing semiconductor device and the grid formation method thereof to improve.
For achieving the above object, the formation method of a kind of grating of semiconductor element provided by the invention comprises step:
The substrate that forms pad oxide is provided;
On the pad oxide of described substrate, form supplemental dielectric;
Utilize photoetching process on described supplemental dielectric, to form the grid hole figure;
With described grid hole figure is mask, and the described supplemental dielectric of etching forms grid hole to exposing described pad oxide;
The deposit spathic silicon layer is to fill described grid hole;
The described polysilicon layer of planarization is to exposing described supplemental dielectric;
Remove described supplemental dielectric, form grid.
Wherein, the size of the grid hole that described grid hole figure is limited is identical with the top dimension of described grid, and the top dimension of described grid is by the gate bottom size identical with the grid size design load, and the shallow doped drain that forms later, be arranged in described grid both sides is determined to the degree of described grid diffuse underneath to be formed at the subsequent thermal annealing process.
Wherein, the process conditions of described etching determine that by the angle of inclination of described gate lateral wall described angle of inclination is by top dimension, the bottom size and highly definite of described grid.
The present invention has the formation method of a kind of semiconductor device of identical or relevant art feature, comprises step:
Substrate is provided;
On described substrate, form pad oxide;
On described pad oxide, form supplemental dielectric;
Utilize photoetching process on described supplemental dielectric, to form the grid hole figure;
With described grid hole figure is mask, and the described supplemental dielectric of etching forms grid hole to exposing described pad oxide;
The deposit spathic silicon layer is to fill described grid hole;
The described polysilicon layer of planarization is to exposing described supplemental dielectric;
Remove described supplemental dielectric, form grid;
Utilizing ion implantation technology, is that mask forms shallow doped drain with described grid;
Carry out thermal anneal process to activate the ion that injects in the described shallow doped drain;
Form metal silicide at described top portions of gates and described shallow doped drain surface.
Wherein, the size of the grid hole that described grid hole figure is limited is identical with the top dimension of described grid, and the top dimension of described grid is by the bottom size of the grid identical with the grid size design load, and the shallow doped drain that forms later, be arranged in described grid both sides is determined to the degree of described grid diffuse underneath at the subsequent thermal annealing process.
Wherein, the process conditions of described etching determine that by the angle of inclination of described gate lateral wall described angle of inclination is by top dimension, the bottom size and highly definite of described grid.
Compared with prior art, the present invention has the following advantages:
The formation method of semiconductor device of the present invention and grid thereof, the method that utilization is inlayed has formed the grid of semiconductor device, the characteristics of utilizing etching itself to have have formed up big and down small grid hole, and the top dimension of the grid that order forms is greater than the size of its bottom.Adopt the semiconductor device of the formation method formation of semiconductor device of the present invention and grid thereof, can reduce requirement first to photoetching, reduce the photoetching difficulty, second can alleviate the annealing steps intermediate ion spreads the device electrical performance variation that causes down to grid problem, reduce the overlap capacitance between grid and the source/drain electrode, improve the operating rate of device.In addition, because the top dimension of formed grid is bigger, it also helps follow-up at top portions of gates formation quality preferred metal silicide.
Description of drawings
Fig. 1 to Fig. 3 is the device profile schematic diagram of the existing grid structure formation method of explanation;
Fig. 4 is the existing semiconductor device generalized section that becomes oxide layer in gate shape;
Fig. 5 is the semiconductor device of specific embodiments of the invention and the flow chart of grid formation method thereof;
Fig. 6 to Figure 13 is the semiconductor device of the explanation specific embodiment of the invention and the device profile schematic diagram of grid formation method thereof.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Processing method of the present invention can be widely used in the every field; and can utilize many suitable material; be to be illustrated below by specific embodiment; certainly the present invention is not limited to this specific embodiment, and the known general replacement of one of ordinary skilled in the art is encompassed in protection scope of the present invention far and away.
Secondly, the present invention utilizes schematic diagram to describe in detail, when the embodiment of the invention is described in detail in detail, for convenience of explanation, the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, should be with this as limitation of the invention, in addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
Utilizing existing grid formation method is to form polysilicon layer earlier, photoetching again, etching form polysilicon gate, the grid of its formation is generally the structure that the top is little, the bottom is big, promptly, size when the size of the actual gate bottom that obtains is greater than photoetching, this photoetching making technology for the integrated circuit that device size dwindles day by day is totally unfavorable.And because its top dimension is less, the formation of the gate metal silicide that its top self-aligned manner forms is second-rate, can form unsettled high resistant silicide because of the live width effect usually, and is unfavorable to device performance.In addition, in the existing grid formation method, utilizing the ion injection mode after the polysilicon gate both sides form shallow doped drain, the ion that is prone to injection in subsequent annealing step is to the grid diffuse underneath, make the overlap capacitance (overlap capacitance) between device grids and the source/drain electrode become big, problem such as the operating rate of device is slack-off.
The present invention proposes a kind of formation method of new grating of semiconductor element, comprise step:
The substrate that forms pad oxide is provided;
On the pad oxide of described substrate, form supplemental dielectric;
Utilize photoetching process on described supplemental dielectric, to form the grid hole figure;
With described grid hole figure is mask, and the described supplemental dielectric of etching forms grid hole to exposing described pad oxide;
The deposit spathic silicon layer is to fill described grid hole;
The described polysilicon layer of planarization is to exposing described supplemental dielectric;
Remove described supplemental dielectric, form grid.
Wherein, the size of the grid hole that described grid hole figure is limited is identical with the top dimension of described grid, and the top dimension of described grid is by the gate bottom size identical with the grid size design load, and the shallow doped drain that forms later, be arranged in described grid both sides is determined to the degree of described grid diffuse underneath to be formed at the subsequent thermal annealing process.
Wherein, the process conditions of described etching determine that by the angle of inclination of described gate lateral wall described angle of inclination is by top dimension, the bottom size and highly definite of described grid.
Wherein, the top dimension of described grid than bottom size about 5 to 20nm.
Wherein, used etching gas is that the carbon fluorine is than high carbon containing fluorine gas during the described supplemental dielectric of etching.
Wherein, the thickness of described supplemental dielectric equals the height of described grid at least.
Wherein, described supplemental dielectric is formed by silicon nitride material or silicon oxy-nitride material.
Wherein, described supplemental dielectric utilizes the chemical gaseous phase depositing process of low temperature to form.
Wherein, described removal supplemental dielectric utilizes wet etching method to realize.
The invention allows for a kind of formation method of new semiconductor device, comprise step:
Substrate is provided;
On described substrate, form pad oxide;
On described pad oxide, form supplemental dielectric;
Utilize photoetching process on described supplemental dielectric, to form the grid hole figure;
With described grid hole figure is mask, and the described supplemental dielectric of etching forms grid hole to exposing described pad oxide;
The deposit spathic silicon layer is to fill described grid hole;
The described polysilicon layer of planarization is to exposing described supplemental dielectric;
Remove described supplemental dielectric, form grid;
Utilizing ion implantation technology, is that mask forms shallow doped drain with described grid;
Carry out thermal anneal process to activate the ion that injects in the described shallow doped drain;
Form metal silicide at described top portions of gates and described shallow doped drain surface.
Wherein, the size of the grid hole that described grid hole figure is limited is identical with the top dimension of described grid, and the top dimension of described grid is by the bottom size of the grid identical with the grid size design load, and the shallow doped drain that forms later, be arranged in described grid both sides is determined to the degree of described grid diffuse underneath at the subsequent thermal annealing process.
Wherein, the process conditions of described etching determine that by the angle of inclination of described gate lateral wall described angle of inclination is by top dimension, the bottom size and highly definite of described grid.
Wherein, the top dimension of described grid than bottom size about 5 to 20nm.
Wherein, used etching gas is that the carbon fluorine is than high carbon containing fluorine gas during the described supplemental dielectric of etching.
Wherein, the thickness of described supplemental dielectric equals the height of described grid at least.
Wherein, described supplemental dielectric is formed by silicon nitride material or silicon oxy-nitride material.
Wherein, described supplemental dielectric utilizes the chemical gaseous phase depositing process of low temperature to form.
Wherein, described removal supplemental dielectric utilizes wet etching method to realize.
The formation method of semiconductor device of the present invention and grid thereof, utilize damascene process to form the grid structure that the top is big, the bottom is little, for the technology below the 65nm node, reduced the requirement of photoetching, improve the formation quality of gate metal silicide, alleviated the problem that spreads the device performance variation that causes because of ion to grid down.
Fig. 5 is the semiconductor device of specific embodiments of the invention and the flow chart of grid formation method thereof, Fig. 6 to Figure 13 describes in detail to specific embodiments of the invention below in conjunction with Fig. 5 to Figure 13 for the semiconductor device of the explanation specific embodiment of the invention and the device profile schematic diagram of grid formation method thereof.
Step 501: the substrate that forms pad oxide is provided.
The generalized section of the substrate that provides in the specific embodiment of the invention is provided Fig. 6, as shown in Figure 6, substrate 600 in the present embodiment is except forming pad oxide 602, can also in substrate, be formed between each device, carrying out the shallow trench isolation of electricity isolation from (STI, Shallow TrenchIsolation) structure 601.Wherein, this pad oxide 602 normally utilizes thermal oxidation method to form, and its thickness and device performance are closely related, and different devices is to the specific requirement difference of this layer thickness.
Step 502: on the pad oxide of described substrate, form supplemental dielectric.
Fig. 7 is the device profile schematic diagram after the formation supplemental dielectric in the specific embodiment of the invention, as shown in Figure 7, has formed one deck supplemental dielectric 603 again on pad oxide 602.The material of this supplemental dielectric is selected to have multiple, and it is different only to need to satisfy the polycrystalline silicon material that forms grid with the silica material and the back of pad oxide 602, and and the two between have and corrode or etching selection ratio gets final product.As, can select materials such as silicon nitride, silicon oxynitride, carborundum for use, selected silicon nitride material in the present embodiment for use.
Owing to be to utilize this supplemental dielectric to form grid with damascene process, the thickness of this supplemental dielectric will equal the height of described grid at least.Usually be arranged on 500 to
Between, as
Or
Deng.
In addition,, can not stay in the device architecture, in order to remove conveniently the comparatively loose material that it can form for the chemical gaseous phase depositing process that utilizes low temperature because of can in subsequent step, being removed in this supplemental dielectric.
Step 503: utilize photoetching process on described supplemental dielectric, to form the grid hole figure.
Fig. 8 is the device profile schematic diagram behind the formation grid hole figure in the specific embodiment of the invention, as shown in Figure 8, utilizes photoetching process that substrate is carried out graphical treatment, forms grid hole figure 605 on supplemental dielectric.In this step photoetching process, be that the photoresist corresponding with area of grid removed, the size of removing the zone is assumed to be a1.
Because of the top dimension of the grid hole that forms in the present embodiment greater than bottom size, and the size of the defined grid hole figure of photoresist is identical with grid hole top dimension a1 in this step, also greater than grid size design load a (measure-alike) with gate bottom, reduced the technology difficulty of photoetched grid, reduce the photoetching rework rate, improved production efficiency and finished product rate.
Wherein, grid hole top dimension a1 can be provided with than grid size design load a big 5 to 20nm, concrete data can be earlier determined the bottom size of grid to be formed according to the type of described semiconductor device, and (design load a) and height, again according to the shallow doped drain that forms later, be arranged in described grid both sides in the degree of subsequent thermal annealing process to described grid diffuse underneath, determine the top dimension of grid to be formed, but grid hole top dimension a1.
For the following device of 65nm, because of it requires very strictly to manufactured size, the variable quantity of tolerance is little, and requires the top of the grid that obtains and the size of bottom all accurately strictly to be controlled.The scope that its a1 is bigger than a is less usually, can be between 5 to 10nm, as be 5nm, 6nm, 7nm, 8nm, 9nm or 10nm etc.
Step 504: with described grid hole figure is mask, and the described supplemental dielectric of etching forms grid hole to exposing described pad oxide.
Fig. 9 is the device profile schematic diagram that forms in the specific embodiment of the invention behind the grid hole, as shown in Figure 9, utilizes grid hole figure that photoresist forms 605 supplemental dielectric 603 to be carried out etching, formation grid hole 610 for mask.This step etching technics can utilize dry etching or wet etching method to realize, in the present embodiment, employing be dry etching method, formed grid hole 610 as shown in Figure 9.
The characteristics of dry etch process itself have determined the sidewall of its formation to be difficult to real the realization vertically, there is certain inclination in the capital, therefore, in the practical operation, also can form the grid hole of top under the usual etch technological condition greater than the bottom, can to a certain degree alleviate occur in the prior art under grid, spread the problems such as device performance variation that cause because of ion.In the present embodiment, in order to widen the difference in size of grid hole top and bottom, the etching gas of the bigger carbon containing fluorine of carbon fluorine has been adopted, as CF obviously greater than the grid hole 610 of bottom in formation top as shown in Figure 9
4, it can produce more polymer, forms the bigger etching section (promptly obtaining the grid hole 610 of top greater than the bottom) in angle of inclination.
In concrete the application, can also be according to the top portions of gates (the grid hole dimension of picture of photoetching) that will realize and the difference in size between bottom (gate design value), and the height of grid determines the process conditions (or say according to gate lateral wall angle of inclination) of this step etching grid hole, and concrete adjustable process conditions comprise that used etching gas is (as CF
4, CF
8, C
5F
8, C
4F
6, CHF
3Deng), etching pressure, etching power etc.But the scope of this adjustment is limited, and in the present embodiment, the difference in size between a1 and a can tune between 5 to 20nm.
In the present embodiment, the grid hole size a1 that photoetching is set is 75nm, and the design load a of grid is 65nm, and the design load of gate height is 100nm.In order to obtain the top is 75nn, and the bottom is the grid of 65nm, need etching formation top be 75nm in this step, and the bottom is the grid hole of 65nm.In addition, in the present embodiment, the thickness of supplemental dielectric 603 is set to consistent with gate height, and its thickness is 100nm.
In such cases, the process conditions of etching formation grid hole are as follows in the present embodiment: utilize plasma etching equipment at room temperature to carry out etching, chamber pressure is arranged between 5 to 20mTorr, as is 5mTorr, 10mTorr, 15mTorr or 20mTorr etc.; Etching power adjustments to 200 is between the 600W, as is 200W, 300W, 400W or 600W etc.
The etching gas of the carbon containing fluorine that feeds in the etching process is CF
4, its flow set as is 30sccm, 40sccm, 50sccm, 60sccm, 70sccm or 80sccm etc. between 30 to 80sccm.In addition, in order to adjust what of polymer more neatly, also fed oxygen in the present embodiment simultaneously, its flow as is 10sccm, 15sccm, 20sccm, 25sccm or 30sccm etc. between 10 to 30sccm.
In the present embodiment, also added assist gas in this step etching process, as argon gas, its flow can be between 150 to 250sccm, as are 150sccm, 180sccm, 200sccm or 250sccm etc.This assist gas can be regulated the concentration of etching gas in the chamber on the one hand, and then changes etch rate; Also can be used for adjusting the pressure of chamber on the other hand, make it remain on set point.
Because supplemental dielectric is a pad oxide 602 603 times, the etch rate between the two can make this step etching stopping on pad oxide 602 than higher easily, obtains comparatively even, consistent etching result.
Step 505: the deposit spathic silicon layer, to fill described grid hole.
Figure 10 is the device profile schematic diagram behind the deposit spathic silicon layer in the specific embodiment of the invention, as shown in figure 10, behind the formation grid hole, remove the residual photoresist of substrate surface, utilize the method for chemical vapour deposition (CVD) to form one deck polysilicon layer 607 then, to fill grid hole 610.Because the existence of grid hole 610, the polysilicon layer 607 that forms according to pattern on substrate also presents rough state, after filling is finished, need carry out planarization to this polysilicon layer.
Step 506: the described polysilicon layer of planarization is to exposing described supplemental dielectric.
Figure 11 is the device profile schematic diagram behind the planarization polysilicon layer in the specific embodiment of the invention, as shown in figure 11, in the present embodiment, utilizes chemical and mechanical grinding method (CMP) that polysilicon layer 607 has been carried out planarization.Because of supplemental dielectric 603 used silicon nitride material and the grinding rates between the polycrystalline silicon material differ bigger, this step planarization can stop at supplemental dielectric 603 places uniformity, has only stayed populated polysilicon layer 607 in grid hole 610.
Step 507: remove described supplemental dielectric, form grid.
Figure 12 is the device profile schematic diagram behind the formation grid in the specific embodiment of the invention, as shown in figure 12, adopt dry etch process or wet corrosion technique to remove supplemental dielectric 603, because of corrosion or the different of etch rate between supplemental dielectric 603 and the polysilicon layer 607 guarantee that supplemental dielectric 603 is removed fully, the polysilicon layer 607 that is positioned at grid hole then is kept perfectly, and forms polysilicon gate.Specifically be to utilize hot phosphoric acid in the present embodiment, removed supplemental dielectric 603 with the method for wet etching.
As shown in figure 12, after utilizing the present embodiment method to form the grid that top dimension is big, bottom size is little, utilize the ion injection mode to form shallow doped drain (LDD district) in the polysilicon gate both sides again, because the top portions of gates broad that forms, the distance between the LDD district 620 of grid both sides that ion injects back formation is identical with top portions of gates size a1, compares with design load also apart from far away.
Figure 13 is the device profile schematic diagram after the annealing in the specific embodiment of the invention, as shown in figure 13, when carrying out thermal annealing with the foreign ion in LDD district that activate to inject, though the diffusion of ion to gate bottom also taken place, but apart from each other when injecting because of it, though diffusion back distance has diminished, just become more near design load a, having alleviated in the conventional method makes the LDD zone distance shorten because of ion to the grid diffuse underneath, problems such as and then the overlap capacitance between the device grids that causes and the source/drain electrode (overlap capacitance) becomes big, and the operating rate of device is slack-off.
After forming grid, also need form the metal silicide of low-resistance on conductive regions such as top portions of gates and LDD district surface.Because the grid size a that the top dimension a1 that utilizes the polysilicon gate that method in the present embodiment forms requires during greater than designs, when forming metal silicide in the back, can provide larger sized space at top portions of gates, help to form high-quality low resistance metal silicide, improve the electrical property of device.
In addition, in the actual production, can also utilize the above-mentioned thinking of present embodiment to make semiconductor device by the following method:
A, provide substrate;
B, on described substrate, form pad oxide;
C, form supplemental dielectric on described pad oxide, this supplemental dielectric can be formed by silicon nitride material or silicon oxy-nitride material, and its thickness can be identical with gate height to be formed; Remove for convenient, it can also utilize the chemical gaseous phase depositing process of low temperature to form.
D, according to the grid size design load of described semiconductor device determine grid to be formed bottom size and the height, in the degree of subsequent thermal annealing process, determine the top dimension of grid to be formed according to the shallow doped drain that forms later, be arranged in described grid both sides to described grid diffuse underneath;
E, utilize photoetching process to form the grid hole figure on described supplemental dielectric, the size of the grid hole that described grid hole figure is limited is identical with the top dimension of described grid; And the two is all greater than the bottom size of grid to be formed, particularly, and can be than gate bottom size big 5 to 20nm;
Because the top dimension of grid hole to be formed is greater than bottom size, and the size of the defined grid hole figure of photoresist is identical with the grid hole top dimension in this step, also greater than grid size design load a (measure-alike) with gate bottom, reduced the technology difficulty of photoetched grid, reduce the photoetching rework rate, improved production efficiency and finished product rate.
F, determine the angle of inclination of described gate lateral wall to be formed according to described top portions of gates size, bottom size and gate height;
G, determine the process conditions of etching grid hole,, when the needs angle of inclination is big (when sidewall is more oblique), can select for use to produce the more carbon fluorine of polymer than higher carbon containing fluorine gas as selecting to used etching gas according to described angle of inclination;
H, be mask, to exposing described pad oxide, form grid hole according to the described supplemental dielectric of process conditions etching of described etching grid hole with described grid hole figure;
I, deposit spathic silicon layer are to fill described grid hole;
J, the described polysilicon layer of planarization are to exposing described supplemental dielectric;
K, utilize dry etching or wet etching method to remove described supplemental dielectric, form grid;
L, utilizing ion implantation technology, is that mask forms shallow doped drain with described grid;
M, carry out thermal anneal process to activate the ion that injects in the described shallow doped drain;
When carrying out this thermal annealing with the foreign ion in LDD district that activate to inject in this step, though the diffusion of ion to gate bottom also can take place, but apart from each other when injecting because of it, diffusion back distance just becomes near design load a, having alleviated in the conventional method makes the LDD zone distance shorten because of ion to the grid diffuse underneath, problems such as and then the overlap capacitance between the device grids that causes and the source/drain electrode (overlap capacitance) becomes big, and the operating rate of device is slack-off.
N, form metal silicide at described top portions of gates and described shallow doped drain surface.
Because the grid size a that the top dimension a1 of the polysilicon gate that forms requires during greater than designs, when forming metal silicide in the back, can provide larger sized space at top portions of gates, help to form high-quality low resistance metal silicide, improve the electrical property of device.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (18)
1. the formation method of a grating of semiconductor element is characterized in that, comprises step:
The substrate that forms pad oxide is provided;
On the pad oxide of described substrate, form supplemental dielectric;
Utilize photoetching process on described supplemental dielectric, to form the grid hole figure;
With described grid hole figure is mask, and the described supplemental dielectric of etching forms grid hole to exposing described pad oxide;
The deposit spathic silicon layer is to fill described grid hole;
The described polysilicon layer of planarization is to exposing described supplemental dielectric;
Remove described supplemental dielectric, form grid.
2. formation method as claimed in claim 1, it is characterized in that: the size of the grid hole that described grid hole figure is limited is identical with the top dimension of described grid, and the top dimension of described grid is by the gate bottom size identical with the grid size design load, and the shallow doped drain that forms later, be arranged in described grid both sides is determined to the degree of described grid diffuse underneath to be formed at the subsequent thermal annealing process.
3. formation method as claimed in claim 2 is characterized in that: the process conditions of described etching determine that by the angle of inclination of described gate lateral wall described angle of inclination is by top dimension, the bottom size and highly definite of described grid.
4. formation method as claimed in claim 1 or 2 is characterized in that: the top dimension of described grid compares big 5 to 20nm with the bottom size of described grid.
5. formation method as claimed in claim 1 is characterized in that: used etching gas is that the carbon fluorine is than high carbon containing fluorine gas during the described supplemental dielectric of etching.
6. formation method as claimed in claim 1 is characterized in that: the thickness of described supplemental dielectric equals the height of described grid at least.
7. formation method as claimed in claim 1 is characterized in that: described supplemental dielectric is formed by silicon nitride material or silicon oxy-nitride material.
8. formation method as claimed in claim 1 is characterized in that: described supplemental dielectric utilizes the chemical gaseous phase depositing process of low temperature to form.
9. formation method as claimed in claim 1 is characterized in that: described removal supplemental dielectric utilizes wet etching method to realize.
10. the formation method of a semiconductor device is characterized in that, comprises step:
Substrate is provided;
On described substrate, form pad oxide;
On described pad oxide, form supplemental dielectric;
Utilize photoetching process on described supplemental dielectric, to form the grid hole figure;
With described grid hole figure is mask, and the described supplemental dielectric of etching forms grid hole to exposing described pad oxide;
The deposit spathic silicon layer is to fill described grid hole;
The described polysilicon layer of planarization is to exposing described supplemental dielectric;
Remove described supplemental dielectric, form grid;
Utilizing ion implantation technology, is that mask forms shallow doped drain with described grid;
Carry out thermal anneal process to activate the ion that injects in the described shallow doped drain;
Form metal silicide at described top portions of gates and described shallow doped drain surface.
11. formation method as claimed in claim 10, it is characterized in that: the size of the grid hole that described grid hole figure is limited is identical with the top dimension of described grid, and the top dimension of described grid is by the bottom size of the grid identical with the grid size design load, and the shallow doped drain that forms later, be arranged in described grid both sides is determined to the degree of described grid diffuse underneath at the subsequent thermal annealing process.
12. formation method as claimed in claim 10 is characterized in that: the process conditions of described etching determine that by the angle of inclination of described gate lateral wall described angle of inclination is by top dimension, the bottom size and highly definite of described grid.
13. as claim 10 or 11 described formation methods, it is characterized in that: the top dimension of described grid compares big 5 to 20nm with the bottom size of described grid.
14. formation method as claimed in claim 10 is characterized in that: used etching gas is that the carbon fluorine is than high carbon containing fluorine gas during the described supplemental dielectric of etching.
15. formation method as claimed in claim 10 is characterized in that: the thickness of described supplemental dielectric equals the height of described grid to be formed at least.
16. formation method as claimed in claim 10 is characterized in that: described supplemental dielectric is formed by silicon nitride material or silicon oxy-nitride material.
17. formation method as claimed in claim 10 is characterized in that: described supplemental dielectric utilizes the chemical gaseous phase depositing process of low temperature to form.
18. formation method as claimed in claim 10 is characterized in that: described removal supplemental dielectric utilizes wet etching method to realize.
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| CN200810225922A CN101740368A (en) | 2008-11-06 | 2008-11-06 | Methods for forming semiconductor device and grid electrode thereof |
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| CN200810225922A CN101740368A (en) | 2008-11-06 | 2008-11-06 | Methods for forming semiconductor device and grid electrode thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446726A (en) * | 2010-10-13 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal gate |
| CN103137449A (en) * | 2011-12-01 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Production methods of grid and transistor |
| CN103165451A (en) * | 2011-12-08 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Structure of semiconductor device and manufacture method |
| CN105336588A (en) * | 2014-05-29 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
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2008
- 2008-11-06 CN CN200810225922A patent/CN101740368A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446726A (en) * | 2010-10-13 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal gate |
| CN102446726B (en) * | 2010-10-13 | 2013-10-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal gate |
| CN103137449A (en) * | 2011-12-01 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Production methods of grid and transistor |
| CN103137449B (en) * | 2011-12-01 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of grid, the manufacture method of transistor |
| CN103165451A (en) * | 2011-12-08 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Structure of semiconductor device and manufacture method |
| CN103165451B (en) * | 2011-12-08 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | The structure of semiconductor device and manufacture method |
| CN105336588A (en) * | 2014-05-29 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
| CN105336588B (en) * | 2014-05-29 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
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