CN103094072A - Method of improving uniformity of photoetching critical size of wafer upper gate electrode - Google Patents
Method of improving uniformity of photoetching critical size of wafer upper gate electrode Download PDFInfo
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- CN103094072A CN103094072A CN2011103412141A CN201110341214A CN103094072A CN 103094072 A CN103094072 A CN 103094072A CN 2011103412141 A CN2011103412141 A CN 2011103412141A CN 201110341214 A CN201110341214 A CN 201110341214A CN 103094072 A CN103094072 A CN 103094072A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
Abstract
The invention relates to a method of improving the uniformity of a photoetching critical size of a wafer upper gate electrode, and further relates to an improved dielectric medium antireflection coating. The method of improving the uniformity of the photoetching critical size of the wafer upper gate electrode comprises the following steps of providing a wafer and forming a gate electrode layer on the surface of the wafer; depositing silicon oxynitride (SiON) on the surface of the gate electrode layer to form an dielectric medium antireflection coating, wherein deviation of the thickness of any position of the dielectric medium antireflection coating and a target thickness is smaller than 2%; and coating photoresist on the dielectric medium antireflection coating to form photoetching patterns of the gate electrode in an exposure mode. The improved dielectric medium antireflection coating (DARC) is used in the method. Because the uniformity of the thickness of the SiON in the DARC is improved, the uniformity of the critical size of a critical size gate electrode can be effectively controlled and adjusted, and the purpose of solving leakage of the rim of the wafer is achieved. Compared with the traditional method of adjusting photoetching forms, plate-making and confirmation need not conducting again, time of improvement of yield is shortened and cost is reduced.
Description
[technical field]
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of method of improving grid photoetching critical dimension uniformity on wafer, also relate to a kind of dielectric anti-reflection coating.
[background technology]
In CMOSFET pipe (CMOS) chip manufacturing, the processing procedure of polysilicon (poly) grid is one very important operation, and the size of polysilicon gate critical size (poly CD) can directly affect the various electrical parameters of device.Therefore the inhomogeneity control of polysilicon gate critical size become extremely important.
In a kind of traditional 0.16 micron grid length (LG) processing procedure, after the polysilicon gate photoetching, the uniformity of critical size is bad, especially in the edge of wafer, the polysilicon gate critical size has been located little more than 10nm than crystal circle center, cause at wafer probing (Chip Probing, CP) electric leakage that the time, special pattern appears in crystal round fringes was lost efficacy, and had a strong impact on product yield and client's confidence, very important that solves therefore that crystal round fringes electric leakage Problem of Failure becomes.
At present in order to solve crystal round fringes polysilicon gate critical size problem less than normal, main way is by the debugging of parameter in the formula (recipe) of polysilicon gate photoetching process is controlled, and generally can regulate the parameters such as focal length in photoetching process, NA (numerical aperture), sigma, energy, photoresist thickness and do improvement.
But the adjustment of these parameters can have influence on the size of photoresist profile (PR profile) and critical size, (OPC) also has corresponding impact on the optical approach effect correction, therefore high to the method cost of parameter adjustment in the photoetching process formula, efficient is low.
[summary of the invention]
Based on this, be necessary to provide a kind of cost lower, the method for improving grid photoetching critical dimension uniformity on wafer that efficient is high.
A kind of method of improving grid photoetching critical dimension uniformity on wafer comprises the following steps: wafer is provided, forms grid layer at described crystal column surface; At described grid layer surface deposition silicon oxynitride, form the dielectric anti-reflection coating, the thickness at described dielectric anti-reflection coating any place and the deviation of target thickness are all less than 2%; Apply photoresist on described dielectric anti-reflection coating, exposure forms the photoengraving pattern of grid.
Preferably, the THICKNESS CONTROL of described dielectric anti-reflection coating exists
In, the N value is controlled in 2.09～2.11, and the K value is controlled in 0.62～0.66.
Preferably, described deposit is chemical vapor deposition, and reacting gas comprises SiH
4, N
2O and He, SiH
4Flow be 69～89sccm, N
2The flow of O is 130～230sccm, and the flow of He is 1800～2200sccm, and the reaction pressure of described deposit is 4～7Torr, and the reaction power of described deposit is 80～120W.
Preferably, described SiH
4Flow be 75sccm.
Preferably, described N
2The flow of O is 210sccm.
Preferably, the flow of described He is 1900sccm.
Preferably, the reaction pressure of described deposit is 5.5Torr.
Preferably, the reaction power of described deposit is 95W.
Preferably, the board model used of described deposit is Producer.
Also be necessary to provide the dielectric anti-reflection coating after a kind of the improvement.
A kind of dielectric anti-reflection coating is located at the surface of grid layer, and material is silicon oxynitride, and the thickness at described dielectric anti-reflection coating any place and the deviation of target thickness are all less than 2%.
The above-mentioned method of improving grid photoetching critical dimension uniformity on wafer, use the dielectric anti-reflection coating (DARC) after a kind of improve, by improving the uniformity of the thickness of SiON in DARC, effectively control and adjust the uniformity of polysilicon gate critical size, reach the purpose that solves the crystal round fringes electric leakage.Adjust the method for photoetching formula with traditional passing through and compare, do not need again make a plate and verify, shortened time and cost that yield improves.
[description of drawings]
Fig. 1 is the flow chart that improves the method for grid photoetching critical dimension uniformity on wafer in an embodiment;
Fig. 2 forms the wafer polysilicon gate critical size of polysilicon gate with the curve chart of wafer back gauge variation by follow-up technique after a kind of AMAT5000 of use board traditional handicraft deposit SiON dielectric anti-reflection coating;
The comparison diagram of Fig. 3 response curve that to be curve shown in Figure 2 obtain with the parameter that adopts Producer board and the first preferred embodiment;
Fig. 4 is the curve chart of the thickness evenness before and after the SiON depositing technics improves;
Fig. 5 is the inhomogeneity curve chart of N value before and after the SiON depositing technics improves;
Fig. 6 is the inhomogeneity curve chart of K value before and after the SiON depositing technics improves;
Fig. 7 is the electric leakage fail data figure of wafer before and after the SiON depositing technics improves.
[embodiment]
For purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
In traditional photoetching process, generally use antireflecting coating (ARC) technique to reduce standing wave effect.Material is that the dielectric anti-reflection coating (Dielectric Anti-reflective Coating, DARC) of SiON (silicon oxynitride) is a kind of in ARC, is usually used in the photoetching process of polysilicon gate.Find through inventor's research and experiment, by improving the uniformity of the dielectric anti-reflection coating on polysilicon gate, the critical size problem less than normal than design load of the polysilicon gate of crystal round fringes be can effectively solve, thereby edge current leakage Problem of Failure, the yields of improving product solved.
In order to make the dielectric anti-reflection coating can obtain good uniformity, find by a large amount of experiments, in the technique of deposit SiON, the scope of the scope of the thickness of the variation of each technological parameter and dielectric anti-reflection coating, N value, K value, N value, K value has close relationship.For example within the specific limits, thickness and reaction pressure, reaction power, N
2The flow of O, SiH
4Flow be directly proportional, be inversely proportional to the flow of He; N value, K value and SiH
4Flow, the flow of He be directly proportional, with reaction pressure, reaction power, N
2The flow of O is inversely proportional to; N value, K value are directly proportional to the flow of reaction power, He, with reaction pressure, SiH
4Flow, N
2The flow of O is inversely proportional to.
Be aided with great many of experiments according to above-mentioned relation, as shown in Figure 1, the invention provides a kind of method of improving grid photoetching critical dimension uniformity on wafer, comprise the following steps:
S110 provides wafer, forms grid layer at crystal column surface.The material of this grid layer is polysilicon.
S120 at grid layer surface deposition silicon oxynitride, forms the dielectric anti-reflection coating, controls the deviation of the thickness at dielectric anti-reflection coating any place and target thickness all less than 2%.Be that thickness is very even.
S130 applies photoresist on the dielectric anti-reflection coating, exposure forms the photoengraving pattern of grid.
The mode of deposit is chemical vapor deposition (Chemical Vapor Deposition, CVD), and the reacting gas of deposit comprises SiH
4, N
2O and He, SiH
4Flow be 69～89sccm, N
2The flow of O is 130～230sccm, and the flow of He is 1800～2200sccm, and the reaction pressure of deposit is 4～7Torr, and the reaction power of deposit is 80～120W.
Experimental data shows in above-mentioned parameter area, the uniformity of the thickness of dielectric anti-reflection coating, N value, K value, and the critical size of polysilicon gate just can significantly improve in the problem that crystal round fringes reduces.Understandable, the inventor has determined separately preferred value a: SiH of each parameter on this basis by experiment
4Flow be 75sccm, N
2The flow of O is 210sccm, and the flow of He is 1900sccm, and the reaction pressure of deposit is 5.5Torr, and the reaction power of deposit is 95W, and the thickness of dielectric anti-reflection coating is
Following table is the value of each parameter in the first preferred embodiment.
| The reaction pressure of deposit | 5.5Torr |
| SiH 4Flow | 75sccm |
| N 2The flow of O | 210sccm |
| The reaction power of deposit | 95W |
| The flow of He | 1900sccm |
The inventor also uses respectively model to be the deposit board of AMAT5000 and the model deposit board deposit dielectric anti-reflection coating as Producer, find to use the Producer board with respect to the dielectric anti-reflection coating of AMAT5000 board deposit, the uniformity of N value, K value, thickness all is improved, thereby makes the uniformity of the critical size of polysilicon gate also be improved.
Fig. 2 forms the wafer polysilicon gate critical size of polysilicon gate with the curve chart of wafer back gauge variation by follow-up technique after a kind of AMAT5000 of use board traditional handicraft deposit SiON dielectric anti-reflection coating.Abscissa represents the distance with crystal round fringes, and ordinate represents the critical size of polysilicon gate, can see that the critical size of polysilicon gate is larger at wafer middle part and edge gap.
The comparison diagram of Fig. 3 response curve that to be curve shown in Figure 1 obtain with the parameter that adopts Producer board and the first preferred embodiment.The uniformity that can see the critical size of polysilicon gate has obtained very big improvement.Fig. 4,5,6 is respectively thickness, N value, the inhomogeneity curve chart of K value that uses AMAT5000 board traditional handicraft and Producer board the first preferred embodiment deposit SiON dielectric anti-reflection coating (being before and after the SiON depositing technics improves).The uniformity that can see thickness, N value, K value has all obtained very big improvement.Referring to Fig. 3, although expectation obtains
SiON, but that reality still has is approaching
Error.Fig. 7 is the electric leakage fail data figure of wafer before and after the SiON depositing technics improves.After employing Producer board the first preferred embodiment deposit SiON dielectric anti-reflection coating, the average leakage rate of DIE has dropped to below 1%.
The above-mentioned method of improving grid photoetching critical dimension uniformity on wafer, use the dielectric anti-reflection coating (DARC) after a kind of improve, the uniformity of K value, N value and thickness by improving SiON in DARC, effectively control and adjust the uniformity of polysilicon gate critical size, reach the purpose that solves the crystal round fringes electric leakage.Adjust the method for photoetching formula with traditional passing through and compare, do not need again make a plate and verify, shortened time and cost that yield improves, promote the client to product confidence.
The above embodiment has only expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.Should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. method of improving grid photoetching critical dimension uniformity on wafer comprises the following steps:
Wafer is provided, forms grid layer at described crystal column surface;
At described grid layer surface deposition silicon oxynitride, form the dielectric anti-reflection coating, the thickness at described dielectric anti-reflection coating any place and the deviation of target thickness are all less than 2%;
Apply photoresist on described dielectric anti-reflection coating, exposure forms the photoengraving pattern of grid.
2. the method for improving grid photoetching critical dimension uniformity on wafer according to claim 1, is characterized in that, the THICKNESS CONTROL of described dielectric anti-reflection coating exists
In, the N value is controlled in 2.09～2.11, and the K value is controlled in 0.62～0.66.
3. the method for improving grid photoetching critical dimension uniformity on wafer according to claim 1 and 2, is characterized in that, described deposit is chemical vapor deposition, and reacting gas comprises SiH
4, N
2O and He, SiH
4Flow be 69～89sccm, N
2The flow of O is 130～230sccm, and the flow of He is 1800～2200sccm, and the reaction pressure of described deposit is 4～7Torr, and the reaction power of described deposit is 80～120W.
4. the method for improving grid photoetching critical dimension uniformity on wafer according to claim 3, is characterized in that described SiH
4Flow be 75sccm.
5. the method for improving grid photoetching critical dimension uniformity on wafer according to claim 3, is characterized in that described N
2The flow of O is 210sccm.
6. the method for improving grid photoetching critical dimension uniformity on wafer according to claim 3, is characterized in that, the flow of described He is 1900sccm.
7. the method for improving grid photoetching critical dimension uniformity on wafer according to claim 3, is characterized in that, the reaction pressure of described deposit is 5.5Torr.
8. the method for improving grid photoetching critical dimension uniformity on wafer according to claim 3, is characterized in that, the reaction power of described deposit is 95W.
9. the method for improving grid photoetching critical dimension uniformity on wafer according to claim 3, is characterized in that, the board model that described deposit is used is Producer.
10. dielectric anti-reflection coating is located at the surface of grid layer, and material is silicon oxynitride, it is characterized in that, the thickness at described dielectric anti-reflection coating any place and the deviation of target thickness are all less than 2%.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110341214.1A CN103094072B (en) | 2011-11-01 | 2011-11-01 | Improve the method for gate lithography critical dimension uniformity on wafer |
| PCT/CN2012/083354 WO2013064025A1 (en) | 2011-11-01 | 2012-10-23 | Method for improving gate photo-etching key size uniformity on wafer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110341214.1A CN103094072B (en) | 2011-11-01 | 2011-11-01 | Improve the method for gate lithography critical dimension uniformity on wafer |
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|---|---|
| CN103094072A true CN103094072A (en) | 2013-05-08 |
| CN103094072B CN103094072B (en) | 2016-03-30 |
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| WO (1) | WO2013064025A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111696849A (en) * | 2019-03-13 | 2020-09-22 | 上海新微技术研发中心有限公司 | Composite film, composite silicon wafer, and preparation method and application thereof |
| CN113391520A (en) * | 2021-05-14 | 2021-09-14 | 上海华力集成电路制造有限公司 | Coating method of photoresist and photoetching method thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112802797B (en) * | 2020-12-29 | 2023-08-15 | 上海华力集成电路制造有限公司 | Method for improving uniformity of critical dimension in wafer surface |
| CN113140505B (en) * | 2021-03-18 | 2023-08-11 | 上海华力集成电路制造有限公司 | Method for manufacturing through hole |
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- 2012-10-23 WO PCT/CN2012/083354 patent/WO2013064025A1/en active Application Filing
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| CN102194686A (en) * | 2010-03-12 | 2011-09-21 | 东京毅力科创株式会社 | Plasma etching method, plasma etching apparatus, and computer-readable storage medium |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111696849A (en) * | 2019-03-13 | 2020-09-22 | 上海新微技术研发中心有限公司 | Composite film, composite silicon wafer, and preparation method and application thereof |
| CN113391520A (en) * | 2021-05-14 | 2021-09-14 | 上海华力集成电路制造有限公司 | Coating method of photoresist and photoetching method thereof |
Also Published As
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| CN103094072B (en) | 2016-03-30 |
| WO2013064025A1 (en) | 2013-05-10 |
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